US20030173677A1

US20030173677A1 - Semiconductor device having a capacitor and method for the manufacture thereof

Info

Publication number: US20030173677A1
Application number: US10/412,256
Authority: US
Inventors: Bee-Lyong Yang; Seaung-Suk Lee; Suk-Kyoung Hong; Nam-Soo Kang
Original assignee: Hyundai Electronics Industries Co Ltd
Current assignee: SCIENTIFIC AND PRODUCTION ENTERPRISE BURINTEKH (BURINTEKH LTD) LLC; SK Hynix Inc
Priority date: 2000-07-06
Filing date: 2003-04-14
Publication date: 2003-09-18
Also published as: US6642100B2; US20020020868A1; US20030006443A1; KR20020004539A; JP2002043541A; TW498548B

Abstract

A semiconductor device for use in a memory cell including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer and composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al_xO_y) layer.

Description

FIELD OF THE INVENTION

The present invention relates to a semiconductor device and, more particularly, to a semiconductor device having a capacitor structure for use in a memory cell and a method for the manufacture thereof.

DESCRIPTION OF THE PRIOR ART

As is well known, a dynamic random access memory (DRAM) with a memory cell comprised of a transistor and a capacitor has a higher degree of integration mainly by down-sizing through micronization. However, there is still a demand for downsizing the area of the memory cell.

To meet this demand, several methods have been proposed, such as a trench type or a stack type capacitor, which is arranged three-dimensionally in a memory device to reduce the cell area available to the capacitor. However, the process of manufacturing a three-dimensionally arranged capacitor is a long and tedious one and consequently incurs high manufacturing costs. Therefore, there is a strong demand for a new memory device that can reduce the cell area while securing a requisite volume of information without requiring complex manufacturing steps.

Thus, to meet the demand, DRAM devices employ a high dielectric material as a capacitor thin film, such as barium strontium titanate (BST) and tantalum oxide (Ta ₂O₅). While DRAM is small, inexpensive, fast, and expends little power, DRAM memory has problems in that it is volatile and has to be refreshed many times each second.

In an attempt to solve the above problems of conventional DRAM, there has been proposed a ferroelectric random access memory (FeRAM) where a capacitor thin film with ferroelectric properties such as strontium bismuth tantalate (SBT) and lead zirconate titanate (PZT) is used for a capacitor in place of a conventional silicon oxide film or a silicon nitride film. FeRAM has a non-volatile property due to remnant polarization of a ferroelectric material and it can operate at lower voltages.

In manufacturing a memory device such as DRAM and FeRAM, there is a step of forming a passivation layer on top of a metal interconnection layer, for protecting the semiconductor device from exposure to detrimental environmental factors such as moisture, particles or the like. The passivation layer is formed by using a method such as plasma enhanced chemical vapor deposition (PECVD) in hydrogen rich ambient. However, during the formation of the passivation layer, the hydrogen gas generated by the PECVD process degrades the capacitor of the memory cell. That is, the hydrogen gas and ions penetrate to a top electrode and a side of the capacitor, reaching to the capacitor thin film and reacting with oxygen atoms constituting the ferroelectric material of the capacitor thin film.

In addition, while an inter-metal dielectric, such as one made of a spin on glass base, is formed after a formation of a metal interconnection, hydrogen atoms may diffuse into the capacitor, thereby degrading the capacitor structure.

These problems, therefore, tend to make it difficult to obtain the desired reproducibility, reliability and yield in fabricating the memory cell.

SUMMARY OF THE INVENTION

It is, therefore, an object of the present invention to provide a semiconductor device incorporating therein a hydrogen barrier layer provided with an aluminum oxide (Al _xO_y) layer to protect a capacitor from hydrogen damage during the formation of an inter-metal dielectric (IMD) layer and a passivation layer.

It is another object of the present invention to provide a method for manufacturing a semiconductor device incorporating therein a hydrogen barrier layer provided with an aluminum oxide (Al _xO_y) layer to protect a capacitor from hydrogen damage during the formation of the IMD layer and the passivation layer.

In accordance with one aspect of the present invention, there is provided a semiconductor device for use in a memory cell, including an active matrix provided with a transistor and a first insulating layer formed around the transistor; a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film; a second insulating layer formed on top of the transistor and the capacitor structure; a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al _xO_y) layer.

In accordance with another aspect of the present invention, there is provided a method for manufacturing a semiconductor device including the steps of a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor; b) forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material; c) forming a second insulating layer on top of the capacitor structure and transistor; d) forming a metal interconnection layer and patterning the metal interconnection into a predetermined configuration to electrically connect the transistor to the capacitor structure; and e) forming a hydrogen barrier layer provided with an aluminum oxide (Al _xO_y) on top of the metal interconnection.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects and features of the present invention will become apparent from the following description of the preferred embodiments given in conjunction with the accompanying drawings, in which: [0013]
FIG. 1 is a cross sectional view setting forth a semiconductor device in accordance with a preferred embodiment of the present invention; and [0014]
FIGS. 2A to [0015] 2G are cross sectional views setting forth a method for the manufacture of the semiconductor memory device in accordance with the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

There are provided in FIG. 1 and FIGS. 2A to [0016] 2G cross sectional views of a semiconductor device 100 for use in a memory cell and cross sectional views setting forth a method for the manufacture thereof in accordance with a-preferred embodiment of the present invention. It, should be noted that like parts appearing in FIG. 1 and FIGS. 2A to 2G are represented by like reference numerals.
In FIG. 1, there is provided a cross sectional view of the [0017] inventive semiconductor device 100 including an active matrix 110, a capacitor structure 150, a second insulating layer 126, a bit line 134, a metal interconnection 136, a hydrogen barrier layer 138 provided with an aluminum oxide (Al_xO_y) layer, and an inter-metal dielectric (IMD) layer 140 formed on the bit line 134 and the hydrogen barrier layer 138. In the embodiment of the present invention, the IMD layer 140 is formed in a shape of a triple layer provided with a SiON layer having a thickness of about 100 nm, a SOG layer having a thickness of about 400 nm and a SRO (silicon rich oxide) layer having a thickness of about 400 nm. The IMD layer 140 is accomplished by using a method such as the CVD or the PVD. The hydrogen barrier layer 138 is formed to a thickness ranging from 2 nm to 100 nm by using a method such as an atomic layer deposition (ALD) and a physical vapor deposition (PVD). Here, the hydrogen barrier layer 138 plays a role in preventing the capacitor of the semiconductor device 100 from being degraded by hydrogen penetration thereinto, because the diffusion velocities of hydrogen atoms markedly decrease in the Al_xO_ylayer.
In addition, a [0018] passivation layer 144 is formed on top of the bit line 134, the IMD layer 140 and the second insulating layer 126 by using a plasma enhanced chemical vapor deposition (PECVD) technique, which is carried out at a high temperature ranging from approximately 320° C. to approximately 400° C., in hydrogen rich ambient. In the present invention, the passivation layer 144 is a double layer provided with an undoped silicate glass (USG) layer and a Si₃N₄layer.
In the [0019] semiconductor device 100, the bit line 134 is electrically connected to a diffusion region 106A and a top electrode of the capacitor structure 150 is electrically connected to another diffusion region 106 through the metal interconnection 136, such that the bit line 134 and the metal interconnection 136 are electrically disconnected from each other. A bottom electrode of the capacitor structure 150 may be connected to a plate line (not shown) to apply a common constant potential thereto. Further, between the bottom and the top electrodes, there is a capacitor thin film made of a ferroelectric material such as SBT (SrBiTaO_x), PZT (PbZrTiO_x) or the like. Here, a reference numeral 125 denotes a TiN adhesion layer formed on the top electrode, for enhancing the connection between the top electrode and the metal interconnection 136.
FIGS. 2A to [0020] 2G are schematic cross sectional views setting forth the method for manufacture of a semiconductor memory device 100 in accordance with the preferred embodiment of the present invention.
The process for manufacturing the [0021] semiconductor device 100 begins with the preparation of an active matrix 110 including a semiconductor substrate 102, an isolation region 104, diffusion regions 106, 106A, a gate oxide 112, a gate line 113, a spacer 114 and a first insulating layer 116, as shown in FIG. 2A. One of the diffusion regions serves as a source and the other diffusion region serves as a drain. The first insulating layer 116 is made of a material such as boron-phosphor-silicate glass (BPSG) or medium temperature oxide (MTO) or the like.
Thereafter, a [0022] buffer layer 118, e.g., made of Ti or TiO_x,is formed on top of the first insulating layer 116 with a thickness ranging from 50 nm to 250 nm. A first metal layer 120, a dielectric layer 122 and a second metal layer 124 with a thickness in the range of 20 nm to 200 nm are formed on top of the buffer layer 118, subsequently. In the preferred embodiment, the dielectric layer 122 is made of a ferroelectric material such as strontium bismuth tantalate (SBT), lead zirconate titanate (PZT) or the like and is formed by using a method such as a spin coating or a chemical vapor deposition (CVD).
In an ensuing step as shown in FIG. 2B, the [0023] second metal layer 124 is patterned into a first predetermined configuration to obtain a top electrode 124A and a capacitor thin film 122A. The dielectric layer 122, the first metal layer 120 and the buffer layer 118 are then patterned into a second predetermined configuration to obtain a capacitor thin film 122A and a bottom electrode structure, thereby forming a capacitor structure 150 having a buffer 118A, a bottom electrode 120A, a capacitor thin film 122A and a top electrode 124A. It is preferable that the bottom electrode 120A have a size different from that of the top electrode 124A in order to form a plate line (not shown) during the following processes.
In a next step as shown in FIG. 2C, a second [0024] insulating layer 126, made of a material such as BPSG, MTO or double layer consisting of BPSG and tetra-ethyl-ortho-silicate (TEOS)-based oxide, is formed on top of the capacitor structure 150 and the first insulating layer 116 by using a method such as CVD. The second insulating layer 126 is flattened by means of a BPSG flow process or chemical mechanical polishing (CMP), as shown in FIG. 2C. In order to densify the second insulating layer 126, an annealing process is carried out at a temperature ranging from approximately 500° C. to approximately 900° C. for at least 10minutes in N₂/O₂ambient.
In an ensuing step, as shown in FIG. 2D, a [0025] first opening 128 and a second opening 130 are formed at positions over the diffusion regions 106A, 106 through the second and the first insulating layers, 126, 116, respectively, by using a method such as a photolithography and a plasma etching, e.g., reactive ion etching (RIE). A third opening 132 is formed at a position over the capacitor structure 150 through the second insulating layer 126 by using a method such as photolithography and plasma etching. Finally, a TiN layer 125 is formed on top electrode 124A of the capacitor structure 150 through the third opening 132, for enhancing the connection between the top electrode 124A and a metal interconnection 136. But, the TiN layer 125 may be omitted.
Thereafter, the metal interconnection layer, e.g., made of Ti/TiN/Al, is formed over the entire surface including the interiors of the [0026] openings 128, 130, 132 and is patterned into a third configuration to form a bit line 134 and a metal interconnection 136, as shown in FIG. 2E.
In a next step, as shown in FIG. 2F, a [0027] hydrogen barrier layer 138 made of an aluminum oxide layer (Al_xO_y) is formed on top of the metal interconnection 136 by using a method such as an atomic layer deposition (ALD) and a physical vapor deposition (PVD). Thereafter, an inter-metal dielectric (IMD) layer 140 made of a spin on glass (SOG) layer is formed on top of the bit line 134 and the hydrogen barrier layer 138. In the embodiment of the present invention, the IMD layer 140 is formed in the shape of a triple layer provided with a SiON layer of 100 nm, a SOG layer of 400 nm and a SRO (silicon rich oxide) layer of 400 nm. The IMD layer is formed by using a method such as the CVD or the PVD. It is noted that the hydrogen barrier layer 138 should cover the capacitor structure 150 sufficiently to protect the capacitor structure 150 effectively from hydrogen damage.
Finally, as shown in FIG. 2G, a [0028] passivation layer 144, e.g., a double layer provided with an undoped silicate glass (USG) and Si₃N₄, is formed on the entire surface by using a method such as a plasma enhanced chemical vapor deposition (PECVD) method to protect the semiconductor device 100 from exposure to detrimental environmental factors such as moisture, particles or the like. The formation of the passivation layer is carried out at a high temperature ranging from approximately 320° C. to 400° C., in hydrogen rich ambient.
By structuring the [0029] semiconductor device 100 of the present invention as aforementioned, it is possible to prevent the capacitor structure 150 from being damaged by hydrogen penetration thereinto. That is, by means of the formation of the hydrogen barrier layer 138 provided with the Al_xO_ylayer, hydrogen damage is effectively avoided because diffusion velocities of hydrogen atoms are remarkably decreased in the Al_xO_ylayer.
While the present invention has been described with respect to the particular embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the scope of the invention as defined in the following claims. [0030]

Claims

What is claimed is:

1. A semiconductor device for use in a memory cell, comprising:

an active matrix provided with a transistor and a first insulating layer formed around the transistor;

a capacitor structure, formed on top of the first insulating layer, composed of a bottom electrode, a capacitor thin film placed on top of the bottom electrode and a top electrode formed on top of the capacitor thin film;

a second insulating layer formed on top of the transistor and the capacitor structure;

a metal interconnection formed on top of the second insulating layer and the active matrix to electrically connect the transistor to the capacitor structure; and

a hydrogen barrier layer formed on top of the metal interconnection, wherein the hydrogen barrier layer is made of an aluminum oxide (Al_xO_y) layer.

2. The semiconductor device as recited in claim 1, wherein the hydrogen barrier layer is formed to a thickness ranging from approximately 2 nm to 100 nm by using a method selected from the group consisting of an atomic layer deposition (ALD) and a physical vapor deposition (PVD).

3. The semiconductor device as recited in claim 1, wherein the metal interconnection includes a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al) and combinations thereof.

4. The semiconductor device of claim 1, further comprising:

a TiN adhesion layer for connecting the metal interconnection and the top electrode, formed on top of the top electrode;

an inter-metal dielectric (IMD) layer formed on top of the hydrogen barrier layer; and

a passivation layer formed on top of the metal interconnection by using a plasma enhanced CVD in a hydrogen rich ambient.

5. The semiconductor as recited in claim 4, wherein the IMD layer is a triple layer provided with a SiON layer of 100 nm in thickness, a SOG (spin on glass) layer of 400 nm in thickness, and a SRO (silicon rich oxide) layer of 400 nm in thickness.

6. The semiconductor device as recited in claim 4, wherein the passivation layer is a double layer provided with an undoped silicate glass (USG) layer and a Si₃N₄layer.

7. The semiconductor device as recited in claim 1, wherein the capacitor thin film includes a material selected from the group consisting of SBT (SrBiTaO_x) and PZT (PbZrTiO_x).

8. A method for manufacturing a semiconductor device, comprising steps of:

a) preparing an active matrix provided with a transistor and a first insulating layer formed around the transistor;

b) forming a capacitor structure on top of the first insulating layer, wherein the capacitor structure includes a capacitor thin film made of a ferroelectric material;

c) forming a second insulating layer on top of the capacitor structure and the transistor;

d) forming a metal interconnection layer and patterning the metal interconnection layer into a predetermined configuration to electrically connect the transistor to the capacitor structure; and

e) forming a hydrogen barrier layer provided with an aluminum oxide (Al_xO_y) layer on top of the metal interconnection.

9. The method as recited in claim 8, wherein the hydrogen barrier layer is formed to a thickness ranging from approximately 2 nm to approximately 100 nm by using a method selected from the group consisting of an atomic layer deposition (ALD) and a physical vapor deposition (PVD).

10. The method as recited in claim 8, wherein the metal interconnection includes a material selected from the group consisting of titanium (Ti), titanium nitride (TiN), aluminum (Al) and combinations thereof.

11. The method as recited in claim 8, further comprising steps of:

f) forming a TiN adhesion layer on top of the top electrode for connecting the metal interconnection and a top electrode;

g) forming an inter-metal dielectric (IMD) layer on top of the hydrogen barrier layer; and

h) forming a passivation layer on top of the metal interconnection by using a plasma enhanced CVD in a hydrogen rich ambient.

12. The method as recited in claim 11, wherein the IMD layer is a triple layer provided with a SiON layer of 100 nm in thickness, a SOG layer of 400 nm in thickness, and a SRO (silicon rich oxide) layer of 400 nm in thickness.

13. The method as recited in claim 11, wherein the passivation layer is a double layer provided with an undoped silicate glass (USG) layer and a Si₃N₄layer.

14. The method as recited in claim 11, wherein the step h) is carried out at a temperature ranging from approximately 320° C. to approximately 400° C.

15. The method as recited in claim 8, wherein the capacitor thin film includes a material selected from the group consisting of SBT (SrBiTaO_x) and PZT (PbZrTiO_x).

16. The method as recited in claim 8, wherein the second insulating layer is a double layer provided with a boron-phosphor-silicate-glass (BPSG) layer and a tetra-ethyl-ortho-silicate (TEOS)-based oxide layer.

17. The method as recited in claim 8, after the step c), further comprising the step of annealing the second insulating layer for densification at a temperature ranging from approximately 500° C. to approximately 900° C. for at least 10 minutes in nitrogen and oxygen ambient.