US20030164303A1 - Method of metal electro-plating for IC package substrate - Google Patents
Method of metal electro-plating for IC package substrate Download PDFInfo
- Publication number
- US20030164303A1 US20030164303A1 US10/289,312 US28931202A US2003164303A1 US 20030164303 A1 US20030164303 A1 US 20030164303A1 US 28931202 A US28931202 A US 28931202A US 2003164303 A1 US2003164303 A1 US 2003164303A1
- Authority
- US
- United States
- Prior art keywords
- package substrate
- plating
- electro
- resisting agent
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 239000000758 substrate Substances 0.000 title claims abstract description 49
- 238000009713 electroplating Methods 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 14
- 239000002184 metal Substances 0.000 title claims description 14
- 229910052751 metal Inorganic materials 0.000 title claims description 14
- 239000003795 chemical substances by application Substances 0.000 claims abstract description 18
- 239000011248 coating agent Substances 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 12
- 238000005530 etching Methods 0.000 claims abstract description 7
- 238000007747 plating Methods 0.000 claims abstract description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims abstract description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052802 copper Inorganic materials 0.000 claims abstract description 4
- 239000010949 copper Substances 0.000 claims abstract description 4
- 230000004907 flux Effects 0.000 claims abstract description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 3
- 229910052737 gold Inorganic materials 0.000 claims abstract description 3
- 239000010931 gold Substances 0.000 claims abstract description 3
- 229910052759 nickel Inorganic materials 0.000 claims abstract description 3
- 230000001681 protective effect Effects 0.000 claims abstract description 3
- 229910000679 solder Inorganic materials 0.000 claims abstract description 3
- 230000009977 dual effect Effects 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/24—Reinforcing the conductive pattern
- H05K3/243—Reinforcing the conductive pattern characterised by selective plating, e.g. for finish plating of pads
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/03—Conductive materials
- H05K2201/0332—Structure of the conductor
- H05K2201/0335—Layered conductors or foils
- H05K2201/0352—Differences between the conductors of different layers of a multilayer
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
- H05K2203/14—Related to the order of processing steps
- H05K2203/1476—Same or similar kind of process performed in phases, e.g. coarse patterning followed by fine patterning
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
- H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
- H05K3/061—Etching masks
- H05K3/064—Photoresists
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/22—Secondary treatment of printed circuits
- H05K3/28—Applying non-metallic protective coatings
- H05K3/282—Applying non-metallic protective coatings for inhibiting the corrosion of the circuit, e.g. for preserving the solderability
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/42—Plated through-holes or plated via connections
- H05K3/425—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern
- H05K3/427—Plated through-holes or plated via connections characterised by the sequence of steps for plating the through-holes or via connections in relation to the conductive pattern initial plating of through-holes in metal-clad substrates
Definitions
- the present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plating metal to form a circuit.
- FIGS. 1A and 1B show a conventional dual surface package substrate where the circuits on each layer are connected with plated through holes.
- the electro-plating method of the substrate is normally the conventional type where at an appropriate position, an electro-plating lead is extended to the plating bar and is then cut off upon completion. At this instance plating tails remain on the substrate and such residues will generate heat while working. In addition, noise will be generated to affect the integrity of signal.
- a main object of the present invention is to provide a method of metal electro-plating for IC package substrate, which overcomes the above-mentioned drawbacks.
- the present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plated metal to form a circuit.
- Yet a further object of the present invention is to provide a method of metal electro-plating IC package substrate, wherein the top side and the lateral sides of the electro-plated layer can be completely covered, and the quality of the circuit will not be damaged in the following processes of substrate manufacturing.
- FIG. 1A is a schematic view showing the residual lead wire of a metal electro-plating in a conventional package substrate.
- FIG. 1B is a sectional view of FIG. 1A.
- FIGS. 2A to I are schematic views showing the metal electro-plating method in accordance with the present invention.
- the method of metal electro-plating for IC package substrate comprises the steps of:
- an electro-plated metallic circuit without plating lines on the package substrate is obtained and the electro-plated metal perfectly covers the top face and lateral face of the copper wire. Thus short circuit due to lateral etching can be avoided.
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Electroplating Methods And Accessories (AREA)
- Manufacturing Of Printed Wiring (AREA)
Abstract
A method of metal-electro-plating for IC package substrate comprising the steps of: forming vias on the package substrate coated with copper film on both sides thereof; electro-plating the vias to form electrical conductive holes between the top layer and the bottom layer of the package substrate; coating a resisting agent where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate; etching the pattern to form circuit without plating lines on the top layer of the substrate, and removing the resisting agent; coating with a resisting agent on the top side and the bottom side of the package substrate but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent; electro-plating the substrate with nickel and gold, and removing the resisting agent; fabricating the circuit on the bottom side of the package substrate and coating with a resisting agent to cover the entire top side and where the circuit is to be formed on the bottom side; etching the substrate to obtain the circuit on the bottom side of the package substrate; and coating solder resist on the region other than the circuit section and applying pre-flux onto the circuit section to form into a protective film.
Description
- (a) Technical Field of the Invention
- The present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plating metal to form a circuit.
- (b) Description of the Prior Art
- FIGS. 1A and 1B show a conventional dual surface package substrate where the circuits on each layer are connected with plated through holes. The electro-plating method of the substrate is normally the conventional type where at an appropriate position, an electro-plating lead is extended to the plating bar and is then cut off upon completion. At this instance plating tails remain on the substrate and such residues will generate heat while working. In addition, noise will be generated to affect the integrity of signal.
- Accordingly, a main object of the present invention is to provide a method of metal electro-plating for IC package substrate, which overcomes the above-mentioned drawbacks.
- The present invention relates to a metal electro-plating for IC package substrate, and in particular, to a method of electro-plated metal to form a circuit.
- Accordingly, it is an object of the present invention to provide a method of metal electro-plating for IC package substrate, wherein the copper film layer of the bottom layer of the package substrate is used as plating bar such that the circuit on the top side of the substrate does not require electro-plating lead wires and no residual lead wires are left over the substrate which causes unnecessary heat and noise.
- Yet a further object of the present invention is to provide a method of metal electro-plating IC package substrate, wherein the top side and the lateral sides of the electro-plated layer can be completely covered, and the quality of the circuit will not be damaged in the following processes of substrate manufacturing.
- The foregoing object and summary provide only a brief introduction to the present invention. To fully appreciate these and other objects of the present invention as well as the invention itself, all of which will become apparent to those skilled in the art, the following detailed description of the invention and the claims should be read in conjunction with the accompanying drawings. Throughout the specification and drawings identical reference numerals refer to identical or similar parts.
- Many other advantages and features of the present invention will become manifest to those versed in the art upon making reference to the detailed description and the accompanying sheets of drawings in which a preferred structural embodiment incorporating the principles of the present invention is shown by way of illustrative example.
- FIG. 1A is a schematic view showing the residual lead wire of a metal electro-plating in a conventional package substrate.
- FIG. 1B is a sectional view of FIG. 1A.
- FIGS. 2A to I are schematic views showing the metal electro-plating method in accordance with the present invention.
- The following descriptions are of exemplary embodiments only, and are not intended to limit the scope, applicability or configuration of the invention in any way. Rather, the following description provides a convenient illustration for implementing exemplary embodiments of the invention. Various changes to the described embodiments may be made in the function and arrangement of the elements described without departing from the scope of the invention as set forth in the appended claims.
- Referring to FIG. 2, the method of metal electro-plating for IC package substrate. In accordance with the present invention, the method of metal electro-plating for IC package substrate comprises the steps of:
- (a) forming
vias 4 on thepackage substrate 1 coated withcopper film 11 on both sides thereof (shown as FIG. 2A); - (b) electro-plating the
vias 4 to form electrical conductive holes between the top layer and the bottom layer of the package substrate 1 (referring to FIG. 2B); - (c) coating a resisting
agent 2 where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate 1 (referring to FIG. 2C); - (d) etching the pattern to form
circuit 3 without plating lines on the top layer of thesubstrate 1, and removing the resisting agent 2 (referring to FIG. 2D); - (e) coating with a resisting
agent 4 on the top side and the bottom side of thepackage substrate 1 but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent 4 (as shown in FIG. 2E); - (f) Electro-plating the substrate with nickel and gold (layer 31), and removing the resisting
agent 4; - (g) fabricating the
circuit 32 on the bottom side of thepackage substrate 1 and coating with a resistingagent 4 to cover the entire top side and where thecircuit 32 is to be formed on the bottom side (referring to FIG. 2G); - (h) etching the
substrate 1 to obtain thecircuit 32 on the bottom side of the package substrate 1 (referring to FIG. 2H); and - (i) coating solder resist 2 on the region other than the
circuit section circuit section 32 to form into a protective film 6 (referring to FIG. 2I). - In view of the present invention, an electro-plated metallic circuit without plating lines on the package substrate is obtained and the electro-plated metal perfectly covers the top face and lateral face of the copper wire. Thus short circuit due to lateral etching can be avoided.
- It will be understood that each of the elements described above, or two or more together may also find a useful application in other types of methods differing from the type described above.
- While certain novel features of this invention have been shown and described and are pointed out in the annexed claim, it is not intended to be limited to the details above, since it will be understood that various omissions, modifications, substitutions and changes in the forms and details of the device illustrated and in its operation can be made by those skilled in the art without departing in any way from the spirit of the present invention.
Claims (1)
1. A method of metal electro-plating for IC package substrate comprising the steps of:
(a) forming vias on the package substrate coated with copper film on both sides thereof;
(b) electro-plating the vias to form electrical conductive holes between the top layer and the bottom layer of the package substrate;
(c) coating a resisting agent where the patterns should be formed on the top layer and on the entire bottom layer of the package substrate;
(d) etching the pattern to form circuit without plating lines on the top layer of the substrate, and removing the resisting agent;
(e) coating with a resisting agent on the top side and the bottom side of the package substrate but the wiring position to be electro-plated as surface finish for wire-bonding electro-plating on the top side of the package substrate not being applied with the resisting agent;
(f) electro-plating the substrate with nickel and gold, and removing the resisting agent;
(g) fabricating the circuit on the bottom side of the package substrate and coating with a resisting agent to cover the entire top side and where the circuit is to be formed on the bottom side;
(h) etching the substrate to obtain the circuit on the bottom side of the package substrate; and
(i) coating solder resist on the region other than the circuit section and applying pre-flux onto the circuit section to form into a protective film.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| TW091104213 | 2002-03-04 | ||
| TW091104213A TW544877B (en) | 2002-03-04 | 2002-03-04 | Method for electroplating IC encapsulated substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US20030164303A1 true US20030164303A1 (en) | 2003-09-04 |
Family
ID=27802808
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US10/289,312 Abandoned US20030164303A1 (en) | 2002-03-04 | 2002-11-07 | Method of metal electro-plating for IC package substrate |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US20030164303A1 (en) |
| JP (1) | JP2003253486A (en) |
| TW (1) | TW544877B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060102384A1 (en) * | 2004-10-27 | 2006-05-18 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
| US20070045834A1 (en) * | 2005-08-31 | 2007-03-01 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| SG130074A1 (en) * | 2005-09-01 | 2007-03-20 | Micron Technology Inc | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| CN109561602A (en) * | 2017-09-27 | 2019-04-02 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and preparation method thereof |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100660027B1 (en) | 2006-01-25 | 2006-12-20 | 삼성전기주식회사 | Manufacturing Method of Printed Circuit Board Using Plating Lead Wire |
| CN101932206B (en) * | 2009-06-25 | 2012-06-13 | 富葵精密组件(深圳)有限公司 | Fabrication method of multi-layer circuit board |
| CN111188070A (en) * | 2020-01-22 | 2020-05-22 | 惠州中京电子科技有限公司 | Manufacturing method for electroplating nickel, silver and gold on IC packaging board |
-
2002
- 2002-03-04 TW TW091104213A patent/TW544877B/en not_active IP Right Cessation
- 2002-10-30 JP JP2002315472A patent/JP2003253486A/en active Pending
- 2002-11-07 US US10/289,312 patent/US20030164303A1/en not_active Abandoned
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060102384A1 (en) * | 2004-10-27 | 2006-05-18 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
| EP1806956A4 (en) * | 2004-10-27 | 2007-11-21 | Ibiden Co Ltd | Multilayer printed wiring board and method for manufacturing multilayer printed wiring board |
| US7626829B2 (en) | 2004-10-27 | 2009-12-01 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
| US20100000087A1 (en) * | 2004-10-27 | 2010-01-07 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of the multilayer printed wiring board |
| US8353103B2 (en) | 2004-10-27 | 2013-01-15 | Ibiden Co., Ltd. | Manufacturing method of multilayer printed wiring board |
| US8737087B2 (en) | 2004-10-27 | 2014-05-27 | Ibiden Co., Ltd. | Multilayer printed wiring board and manufacturing method of multilayer printed wiring board |
| US20070045834A1 (en) * | 2005-08-31 | 2007-03-01 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| US7326591B2 (en) | 2005-08-31 | 2008-02-05 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| US20080099931A1 (en) * | 2005-08-31 | 2008-05-01 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| US7915726B2 (en) | 2005-08-31 | 2011-03-29 | Micron Technology, Inc. | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| SG130074A1 (en) * | 2005-09-01 | 2007-03-20 | Micron Technology Inc | Interconnecting substrates for microelectronic dies, methods for forming vias in such substrates, and methods for packaging microelectronic devices |
| CN109561602A (en) * | 2017-09-27 | 2019-04-02 | 鹏鼎控股(深圳)股份有限公司 | Circuit board and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2003253486A (en) | 2003-09-10 |
| TW544877B (en) | 2003-08-01 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: ORIENT SEMICONDUCTOR ELECTRONICS LIMITED, TAIWAN Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:HUANG, FU-YU;CHUANG, CHIN-HUI;TSENG, YA-SHIN;AND OTHERS;REEL/FRAME:013474/0730 Effective date: 20021017 |
|
| STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |