US20030145300A1 - Layout tracking solutions - Google Patents
Layout tracking solutions Download PDFInfo
- Publication number
- US20030145300A1 US20030145300A1 US10/059,592 US5959202A US2003145300A1 US 20030145300 A1 US20030145300 A1 US 20030145300A1 US 5959202 A US5959202 A US 5959202A US 2003145300 A1 US2003145300 A1 US 2003145300A1
- Authority
- US
- United States
- Prior art keywords
- cell
- cells
- data structure
- information
- user
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
- 238000000034 method Methods 0.000 claims abstract description 29
- 238000013461 design Methods 0.000 claims abstract description 28
- 238000003860 storage Methods 0.000 claims description 4
- 230000008676 import Effects 0.000 claims description 3
- 238000004519 manufacturing process Methods 0.000 claims description 3
- 235000006508 Nelumbo nucifera Nutrition 0.000 claims description 2
- 240000002853 Nelumbo nucifera Species 0.000 claims description 2
- 235000006510 Nelumbo pentapetala Nutrition 0.000 claims description 2
- 230000008901 benefit Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 3
- 230000004048 modification Effects 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 238000012938 design process Methods 0.000 description 2
- 238000011161 development Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000004088 simulation Methods 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 239000012467 final product Substances 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
- 238000003786 synthesis reaction Methods 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
Definitions
- the subject of this application relates generally to the field of integrated circuit (IC) design, and more particularly to layout tracking solutions.
- FIG. 1 illustrates an exemplarily flow diagram of a typical design process 100 for ICs in accordance with the prior art.
- the process can be generally divided into a front end design phase and a back end development phase.
- an engineer designs and develops a logical representation of an IC from a set of specifications in form of a schematic (step 102 ).
- the schematic is then loaded into a computer from which a circuit netlist is generated.
- the netlist defines the entire IC design including all components and interconnections.
- the IC information may be developed using hardware description language (HDL) and synthesis.
- HDL hardware description language
- a designer can then simulate the functionality of a given circuit at a step 106 .
- the circuit simulation process may involve several iterations of design modifications and improvements, until the circuit design is finalized at a step 108 .
- a final circuit layout (physical description) is developed based on the schematic design of the front end.
- various building blocks (or cells), as defined by the finalized circuit schematic, are placed within a predefined floor plan.
- the various building circuit blocks are typically predefined and made available in a cell library.
- a plurality of cells are selected from one or more cell libraries and the cell interconnects are determined. More particularly, groups of cells may be interconnected to function as a flip-flop, shift registers, and the like.
- step 112 The routing of wires to interconnect the cells and achieve the aforementioned goals is preformed during a routing step 112 , typically referred to as conducting paths, wires or nets. Accordingly, in the step 112 , interconnects between circuit elements are routed throughout the layout. In a step 114 , the accuracy of the layout is verified against the schematic and if no errors or design rule violations are found at a step 116 , the circuit layout information is used for the process of fabrication in a step 118 .
- the present invention which may be implemented on a general-purpose digital computer, includes novel methods and apparatus to provide layout tracking solutions, utilizing single or multiple processors.
- a method of tracking a plurality of cell layouts includes dividing a circuit layout design into a plurality of cell; providing a list of the plurality of cells; permitting a user to select a cell from the list of cells; permitting the user to enter cell information for the selected cell; providing a first data structure and a second data structure, the first data structure including cellname information regarding the selected cell and the second data structure including cell information for the selected cell; and sequentially storing the entered cell information for the selected cell from the first and second data structures. It is envisioned that the sequentially stored cell information provides data on a status of the plurality of cell layouts.
- the first data structure and/or the second data structure can be linked list.
- a graphical user interface for tracking status of a plurality of layout cells.
- the GUI includes a first frame including a name list of a plurality of cells being tracked; a second frame including a plurality of fields to enter data for a selected cell from the name list; a third frame to include comments regarding the selected cell; and a fourth frame to include a message regarding the selected cell.
- the GUI further includes a plurality of buttons.
- FIG. 1 illustrates an exemplarily flow diagram of a typical design process 100 for ICs in accordance with the prior art
- FIG. 2 illustrates an exemplary computer system 200 in which the present invention may be embodied
- FIG. 3 illustrates an exemplary tool 300 in accordance with an embodiment of the present invention.
- FIG. 4 illustrates an exemplary report 400 in accordance with an embodiment of the present invention.
- FIG. 2 illustrates an exemplary computer system 200 in which the present invention may be embodied in certain embodiments.
- the system 200 comprises a central processor 202 , a main memory 204 , an input/output (I/O) controller 206 , a keyboard 208 , a pointing device 210 (e.g., mouse, track ball, pen device, or the like), a display device 212 , a mass storage 214 (e.g., hard disk, optical drive, or the like), and a network interface 218 .
- Additional input/output devices, such as a printing device 216 may be included in the system 200 as desired.
- the various components of the system 200 communicate through a system bus 220 or similar architecture.
- the computer system 200 includes a Sun Microsystems computer utilizing a SPARC microprocessor available from several vendors (including Sun Microsystems of Palo Alto, Calif.).
- a Sun Microsystems computer utilizing a SPARC microprocessor available from several vendors (including Sun Microsystems of Palo Alto, Calif.).
- SPARC microprocessor available from several vendors (including Sun Microsystems of Palo Alto, Calif.).
- any type of computer system may be utilized to embody the present invention, including those made by Hewlett Packard of Palo Alto, Calif., and IBM-compatible personal computers utilizing Intel microprocessor, which are available from several vendors (including IBM of Armonk, N.Y.).
- two or more processors can be utilized to provide speedup in operations.
- the network interface 218 provides communication capability with other computer systems on a same local network, on a different network connected via modems and the like to the present network, or to other computers across the Internet.
- the network interface 218 can be implemented in Ethernet, Fast Ethernet, wide-area network (WAN), leased line (such as T1, T3, optical carrier 3 (OC3), and the like), digital subscriber line (DSL and its varieties such as high bit-rate DSL (HDSL), integrated services digital network DSL (IDSL), and the like), time division multiplexing (TDM), asynchronous transfer mode (ATM), satellite, cable modem, and FireWire.
- WAN wide-area network
- leased line such as T1, T3, optical carrier 3 (OC3), and the like
- DSL and its varieties such as high bit-rate DSL (HDSL), integrated services digital network DSL (IDSL), and the like
- TDM time division multiplexing
- ATM asynchronous transfer mode
- satellite cable modem
- FireWire FireWire
- the computer system 200 may utilize operating systems such as Solaris, Windows (and its varieties such as NT, 2000, XP, ME, and the like), HP-UX, IBM-AIX, Unix, Berkeley software distribution (BSD) Unix, Linux, Apple Unix (AUX), and the like. Also, it is envisioned that in certain embodiments, the computer system 200 is a general purpose computer capable of running any number of applications such as those available from companies including Oracle, Siebel, Unisys, Microsoft, Vignette, IBM, Avanti, Synopsis, and the like.
- FIG. 3 illustrates an exemplary tool 300 in accordance with an embodiment of the present invention.
- the tool 300 can in some embodiments be used to help mass designers, their project managers, or more generally a user in recording and tracking layout work schedules. It is envisioned that each mass designer is generally assigned a cell (or a group of cells) for a given project. Each cell is envisioned to contain layout information about a portion of a given design. Also, cells may be divided such that each cell can be assigned to a given designer who can individually complete the task of providing the layout for that cell.
- the tool 300 includes four frames.
- the first frame (cellname list 302 ) is utilized to obtain a list of cells from a responsible party such as a mass designer. It is envisioned that the designed can specify the cell list either by creating a file and adding each cellname to that file or creating subdirectories with the names matching the cellnames.
- the second frame (mass designer inputs 304 ) is utilized to allow a designer (or other appropriate user) access for entering the required data for a given cellname.
- a button 305 may be utilized to load information regarding a selected cellname from the cellname list 302 into the mass designer inputs frame 304 .
- a button 306 may be utilized to reload the cellname list data into the cellname list 302 .
- the reload button 306 can be utilized to allow a user to reload the cellname list from, for example, a file stored on a computer system or a server (locally and/or remotely) while running the tool 300 . This feature is supported to allow users to refresh or update the list 302 without terminating the tool 300 .
- the inputs for the mass designers inputs frame 304 may include a mass designer's name, a project name, a cellname, a schematic version number, a layout start date, a layout end date, a design rule check (DRC) start date, a DRC end date, a layout verses schematic (LVS) start date, and LVS end date, methodology check start date, a methodology check end date, and a miscellaneous information field. It is envisioned that fewer or more fields may be utilized to provide mass designer inputs frame 304 depending on the issues being addressed.
- the third frame (comments 308 ) can be utilized to allow a user to enter general comments such as messages regarding a given cellname that may need to be communicated to other personal involved in the project or as a reminder to the user.
- the fourth frame (message 310 ) is utilized to display messages created by the system including those created by the tool 300 . It is also envisioned that the frames discussed herein (and more generally any fields discussed herein) may be scrollable in X, Y, and Z axes.
- the tool 300 may also provide access to other functionality such as those illustrated in FIG. 3 as buttons 312 - 322 .
- the submit button 312 allows a user to submit the input provided to generate a report.
- the update button 314 allows a user to store the data entered into the mass designer inputs frame ( 304 ) to a nonvolatile memory.
- the view button 316 permits a user to generate a viewable report of the available cell information.
- the clear button 318 can be utilized to clear all the messages provided in the message frame 310 .
- the exit button 320 can be utilized to terminate the tool 300 .
- the help button 322 can provide access to information, which may assist a user in utilizing the tool 300 and its functionalities.
- Advantages of implying a link list configuration with the tool 300 include no limitation on the number of entries, temporary storage of data without having to open and save a file, providing a non-fragmented file, and utilization of system resources such as an exception handler provided in, for example, Solaris systems by Sun Microsystems, which would save any unrecorded data prior to an involuntary termination of a program (such as the tool 300 ).
- the cell information may be stored in a library, cell, and/or view configuration where the library is a directory name (parent), the cell is a subdirectory of library (child), and the view is a subdirectory of cell (grandchild, where all the actual binary data that contains a design may reside).
- a hierarchical structure may be utilized to store and/or organize the actual data for a design.
- FIG. 4 illustrates an exemplary report 400 in accordance with an embodiment of the present invention.
- the report 400 includes information about a same cellname (sf_cell_name1).
- Report sections 410 - 413 include the cell information in a chronological order. The information provided in sections 410 - 413 are, in the most part, similar to those entered by a user in the mass designers frame 304 of FIG. 3.
- the report sections 410 - 413 also include a tracking date field (optional) which can track the exact date and time of when the data was entered into a tool such as the tool 300 of FIG. 3. It is envisioned that the cell information can be stored in sequential manner such that different user inputs for a given cell are recorded to ensure that the report reflects accurate tracking of changes associated with a given cell.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
Description
- The subject of this application relates generally to the field of integrated circuit (IC) design, and more particularly to layout tracking solutions.
- As IC fabrication technology improves, manufacturers are able to integrate additional functionality onto a single silicon substrate. As the number of these functions increases, however, so does the complexity of the designs. Often to meet deadlines, many designers work on a same design simultaneously. The partial designs will then need to be put together to make a final product. The timing is of the essence in making sure that the many portions of the design are finished relatively simultaneously. Also, it is imperative that strict deadlines are followed, in part, because a later design stage may depend on information regarding a preceding stage before meaningful design may be commenced.
- As circuits are quickly becoming more complicated, layout tracking, as with many other design scheduling techniques, is becoming increasingly computerized for efficiency purposes. Also, as circuit designs grow in complexity, it is imperative to decrease the number of computer resources and hours spent on tracking these design layouts. This is extremely important with respect to layout tracking. Especially, in the current climate of competition, it is imperative that the layout tracking be performed accurately such that designers' time is not wasted in waiting for completion of a previous design stage.
- FIG. 1 illustrates an exemplarily flow diagram of a
typical design process 100 for ICs in accordance with the prior art. The process can be generally divided into a front end design phase and a back end development phase. During the front end phase, an engineer designs and develops a logical representation of an IC from a set of specifications in form of a schematic (step 102). At astep 104, the schematic is then loaded into a computer from which a circuit netlist is generated. The netlist defines the entire IC design including all components and interconnections. - Moreover, the IC information may be developed using hardware description language (HDL) and synthesis. With the aid of circuit simulation tools available on computers, a designer can then simulate the functionality of a given circuit at a
step 106. The circuit simulation process may involve several iterations of design modifications and improvements, until the circuit design is finalized at astep 108. - The back end development involves several steps during which a final circuit layout (physical description) is developed based on the schematic design of the front end. In a
step 110, various building blocks (or cells), as defined by the finalized circuit schematic, are placed within a predefined floor plan. For ICs designed based on array or standard cell technology, the various building circuit blocks are typically predefined and made available in a cell library. For example, during thestep 110, a plurality of cells are selected from one or more cell libraries and the cell interconnects are determined. More particularly, groups of cells may be interconnected to function as a flip-flop, shift registers, and the like. The routing of wires to interconnect the cells and achieve the aforementioned goals is preformed during arouting step 112, typically referred to as conducting paths, wires or nets. Accordingly, in thestep 112, interconnects between circuit elements are routed throughout the layout. In astep 114, the accuracy of the layout is verified against the schematic and if no errors or design rule violations are found at astep 116, the circuit layout information is used for the process of fabrication in astep 118. - The present invention, which may be implemented on a general-purpose digital computer, includes novel methods and apparatus to provide layout tracking solutions, utilizing single or multiple processors.
- In an embodiment, a method of tracking a plurality of cell layouts is disclosed. The method includes dividing a circuit layout design into a plurality of cell; providing a list of the plurality of cells; permitting a user to select a cell from the list of cells; permitting the user to enter cell information for the selected cell; providing a first data structure and a second data structure, the first data structure including cellname information regarding the selected cell and the second data structure including cell information for the selected cell; and sequentially storing the entered cell information for the selected cell from the first and second data structures. It is envisioned that the sequentially stored cell information provides data on a status of the plurality of cell layouts. In various embodiments the first data structure and/or the second data structure can be linked list.
- In another embodiment, a graphical user interface (GUI) for tracking status of a plurality of layout cells is disclosed. The GUI includes a first frame including a name list of a plurality of cells being tracked; a second frame including a plurality of fields to enter data for a selected cell from the name list; a third frame to include comments regarding the selected cell; and a fourth frame to include a message regarding the selected cell. In certain embodiments, the GUI further includes a plurality of buttons.
- The present invention maybe better understood and it's numerous objects, features, and advantages made apparent to those skilled in the art by reference to the accompanying drawings in which:
- FIG. 1 illustrates an exemplarily flow diagram of a
typical design process 100 for ICs in accordance with the prior art; - FIG. 2 illustrates an
exemplary computer system 200 in which the present invention may be embodied; - FIG. 3 illustrates an
exemplary tool 300 in accordance with an embodiment of the present invention; and - FIG. 4 illustrates an
exemplary report 400 in accordance with an embodiment of the present invention. - The use of the same reference symbols in different drawings indicates similar or identical items.
- In the following description, numerous details are set forth. It will be apparent, however, to one skilled in the art, that the present invention may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present invention.
- Reference in the specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. The appearances of the phrase “in one embodiment” in various places in the specification are not necessarily all referring to the same embodiment.
- FIG. 2 illustrates an
exemplary computer system 200 in which the present invention may be embodied in certain embodiments. Thesystem 200 comprises acentral processor 202, amain memory 204, an input/output (I/O)controller 206, akeyboard 208, a pointing device 210 (e.g., mouse, track ball, pen device, or the like), adisplay device 212, a mass storage 214 (e.g., hard disk, optical drive, or the like), and anetwork interface 218. Additional input/output devices, such as aprinting device 216, may be included in thesystem 200 as desired. As illustrated, the various components of thesystem 200 communicate through asystem bus 220 or similar architecture. - In an embodiment, the
computer system 200 includes a Sun Microsystems computer utilizing a SPARC microprocessor available from several vendors (including Sun Microsystems of Palo Alto, Calif.). Those with ordinary skill in the art understand, however, that any type of computer system may be utilized to embody the present invention, including those made by Hewlett Packard of Palo Alto, Calif., and IBM-compatible personal computers utilizing Intel microprocessor, which are available from several vendors (including IBM of Armonk, N.Y.). Also, instead of a single processor, two or more processors (whether on a single chip or on separate chips) can be utilized to provide speedup in operations. - The
network interface 218 provides communication capability with other computer systems on a same local network, on a different network connected via modems and the like to the present network, or to other computers across the Internet. In various embodiments, thenetwork interface 218 can be implemented in Ethernet, Fast Ethernet, wide-area network (WAN), leased line (such as T1, T3, optical carrier 3 (OC3), and the like), digital subscriber line (DSL and its varieties such as high bit-rate DSL (HDSL), integrated services digital network DSL (IDSL), and the like), time division multiplexing (TDM), asynchronous transfer mode (ATM), satellite, cable modem, and FireWire. Moreover, thecomputer system 200 may utilize operating systems such as Solaris, Windows (and its varieties such as NT, 2000, XP, ME, and the like), HP-UX, IBM-AIX, Unix, Berkeley software distribution (BSD) Unix, Linux, Apple Unix (AUX), and the like. Also, it is envisioned that in certain embodiments, thecomputer system 200 is a general purpose computer capable of running any number of applications such as those available from companies including Oracle, Siebel, Unisys, Microsoft, Vignette, IBM, Avanti, Synopsis, and the like. - FIG. 3 illustrates an
exemplary tool 300 in accordance with an embodiment of the present invention. Thetool 300 can in some embodiments be used to help mass designers, their project managers, or more generally a user in recording and tracking layout work schedules. It is envisioned that each mass designer is generally assigned a cell (or a group of cells) for a given project. Each cell is envisioned to contain layout information about a portion of a given design. Also, cells may be divided such that each cell can be assigned to a given designer who can individually complete the task of providing the layout for that cell. - As illustrated, the
tool 300 includes four frames. The first frame (cellname list 302) is utilized to obtain a list of cells from a responsible party such as a mass designer. It is envisioned that the designed can specify the cell list either by creating a file and adding each cellname to that file or creating subdirectories with the names matching the cellnames. The second frame (mass designer inputs 304) is utilized to allow a designer (or other appropriate user) access for entering the required data for a given cellname. Abutton 305 may be utilized to load information regarding a selected cellname from thecellname list 302 into the massdesigner inputs frame 304. A button 306 may be utilized to reload the cellname list data into thecellname list 302. It is also envisioned that the reload button 306 can be utilized to allow a user to reload the cellname list from, for example, a file stored on a computer system or a server (locally and/or remotely) while running thetool 300. This feature is supported to allow users to refresh or update thelist 302 without terminating thetool 300. - As illustrated in FIG. 3, the inputs for the mass
designers inputs frame 304 may include a mass designer's name, a project name, a cellname, a schematic version number, a layout start date, a layout end date, a design rule check (DRC) start date, a DRC end date, a layout verses schematic (LVS) start date, and LVS end date, methodology check start date, a methodology check end date, and a miscellaneous information field. It is envisioned that fewer or more fields may be utilized to provide massdesigner inputs frame 304 depending on the issues being addressed. - The third frame (comments308) can be utilized to allow a user to enter general comments such as messages regarding a given cellname that may need to be communicated to other personal involved in the project or as a reminder to the user. The fourth frame (message 310) is utilized to display messages created by the system including those created by the
tool 300. It is also envisioned that the frames discussed herein (and more generally any fields discussed herein) may be scrollable in X, Y, and Z axes. - The
tool 300 may also provide access to other functionality such as those illustrated in FIG. 3 as buttons 312-322. The submit button 312 allows a user to submit the input provided to generate a report. The update button 314 allows a user to store the data entered into the mass designer inputs frame (304) to a nonvolatile memory. The view button 316 permits a user to generate a viewable report of the available cell information. The clear button 318 can be utilized to clear all the messages provided in themessage frame 310. The exit button 320 can be utilized to terminate thetool 300. The help button 322 can provide access to information, which may assist a user in utilizing thetool 300 and its functionalities. - When inputs are obtained and the submit button is pressed, it is envisioned that all the data input are added to a first linked list where all the cellnames can be linked to. Each cell defined in the linked list can also be defined as a linked list itself where all user inputs can be stored. Having used these two linked lists, a user can submit multiple runs for the same cell without causing performance concerns. It is envisioned that once a layout job is done, a user can click on the exit button320 and all the data from the linked list can be written to a file. Therefore, data can be stored and organized in a sequential fashion. It is also envisioned that the
tool 300 has an advantage of avoiding opening and closing the same file multiple times. This is an especially important performance consideration because opening and closing files generally degrades the performance of a computer system due, in part, to the required wait periods for reading and writing files. - It is also envisioned that once the exit button320 is pressed, a file can be generated to store the selected cellname. Therefore, if a user happens to exit the
tool 300 and reload it, the last selected cellname will be retrieved from the stored file. It is also envisioned that a user may click on the view button 316 to import the stored report data into an appropriate application for further formatting, sorting, and the like. An example of such an application is StarOffice by Sun Microsystems, Inc., of Palo Alto, Calif., Excel by Microsoft Corporation of Redmond, Wash., and Lotus 123 by IBM. Advantages of implying a link list configuration with thetool 300 include no limitation on the number of entries, temporary storage of data without having to open and save a file, providing a non-fragmented file, and utilization of system resources such as an exception handler provided in, for example, Solaris systems by Sun Microsystems, which would save any unrecorded data prior to an involuntary termination of a program (such as the tool 300). - It is further envisioned that different data structures may be utilized to store the cellnames discussed with respect to the current invention. For example, the cell information may be stored in a library, cell, and/or view configuration where the library is a directory name (parent), the cell is a subdirectory of library (child), and the view is a subdirectory of cell (grandchild, where all the actual binary data that contains a design may reside). Thus, a hierarchical structure may be utilized to store and/or organize the actual data for a design.
- FIG. 4 illustrates an
exemplary report 400 in accordance with an embodiment of the present invention. As illustrated, thereport 400 includes information about a same cellname (sf_cell_name1). Report sections 410-413 include the cell information in a chronological order. The information provided in sections 410-413 are, in the most part, similar to those entered by a user in the mass designers frame 304 of FIG. 3. As shown, the report sections 410-413 also include a tracking date field (optional) which can track the exact date and time of when the data was entered into a tool such as thetool 300 of FIG. 3. It is envisioned that the cell information can be stored in sequential manner such that different user inputs for a given cell are recorded to ensure that the report reflects accurate tracking of changes associated with a given cell. - The foregoing description has been directed to specific embodiments. It will be apparent to those with ordinary skill in the art that modifications may be made to the described embodiments, with the attainment of all or some of the advantages. For example, the schemes, data structures, and methods described herein can also be extended to other applications. Also, while the techniques disclosed herein have been discussed with respect to mass designers, they could equally be applied to a general computer user. Therefore, it is the object of the appended claims to cover all such variations and modifications as come within the spirit and scope of the invention.
Claims (26)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/059,592 US20030145300A1 (en) | 2002-01-28 | 2002-01-28 | Layout tracking solutions |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/059,592 US20030145300A1 (en) | 2002-01-28 | 2002-01-28 | Layout tracking solutions |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030145300A1 true US20030145300A1 (en) | 2003-07-31 |
Family
ID=27609839
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/059,592 Abandoned US20030145300A1 (en) | 2002-01-28 | 2002-01-28 | Layout tracking solutions |
Country Status (1)
Country | Link |
---|---|
US (1) | US20030145300A1 (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070300199A1 (en) * | 2006-06-27 | 2007-12-27 | Fujitsu Limited | Design data creating method, design data creating apparatus and computer readable information recording medium |
US20090064077A1 (en) * | 2007-09-04 | 2009-03-05 | Prasanti Uppaluri | Layout versus schematic error system and method |
US10331843B1 (en) * | 2016-09-27 | 2019-06-25 | Altera Corporation | System and method for visualization and analysis of a chip view including multiple circuit design revisions |
Citations (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5107441A (en) * | 1990-10-31 | 1992-04-21 | Otis Engineering Corporation | System for evaluating the flow performance characteristics of a device |
US5553276A (en) * | 1993-06-30 | 1996-09-03 | International Business Machines Corporation | Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units |
US5787006A (en) * | 1996-04-30 | 1998-07-28 | Micron Technology, Inc. | Apparatus and method for management of integrated circuit layout verification processes |
US5884284A (en) * | 1995-03-09 | 1999-03-16 | Continental Cablevision, Inc. | Telecommunication user account management system and method |
US5910895A (en) * | 1997-06-13 | 1999-06-08 | Teradyne, Inc. | Low cost, easy to use automatic test system software |
US5983277A (en) * | 1996-10-28 | 1999-11-09 | Altera Corporation | Work group computing for electronic design automation |
US6009250A (en) * | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Selective flattening in layout areas in computer implemented integrated circuit design |
US6058252A (en) * | 1995-01-19 | 2000-05-02 | Synopsys, Inc. | System and method for generating effective layout constraints for a circuit design or the like |
US6077308A (en) * | 1997-08-21 | 2000-06-20 | Micron Technology, Inc. | Creating layout for integrated circuit structures |
US6157947A (en) * | 1998-02-09 | 2000-12-05 | Fujitsu Limited | Method, apparatus, system, and program storage device for distributing intellectual property |
US6155725A (en) * | 1994-04-19 | 2000-12-05 | Lsi Logic Corporation | Cell placement representation and transposition for integrated circuit physical design automation system |
US6237128B1 (en) * | 1997-10-01 | 2001-05-22 | International Business Machines Corporation | Method and apparatus for enabling parallel layout checking of designing VLSI-chips |
US6550046B1 (en) * | 1998-10-08 | 2003-04-15 | Conexant Systems, Inc. | Method for automated placement of cells in an integrated circuit layout |
US6571374B1 (en) * | 2000-02-28 | 2003-05-27 | International Business Machines Corporation | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips |
US6578174B2 (en) * | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
US6643683B1 (en) * | 2000-05-08 | 2003-11-04 | International Business Machines Corporation | Interactive client-server environment for performing collaborative timing analysis of circuit designs |
US6742165B2 (en) * | 2001-03-28 | 2004-05-25 | Mips Technologies, Inc. | System, method and computer program product for web-based integrated circuit design |
-
2002
- 2002-01-28 US US10/059,592 patent/US20030145300A1/en not_active Abandoned
Patent Citations (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5107441A (en) * | 1990-10-31 | 1992-04-21 | Otis Engineering Corporation | System for evaluating the flow performance characteristics of a device |
US5553276A (en) * | 1993-06-30 | 1996-09-03 | International Business Machines Corporation | Self-time processor with dynamic clock generator having plurality of tracking elements for outputting sequencing signals to functional units |
US6155725A (en) * | 1994-04-19 | 2000-12-05 | Lsi Logic Corporation | Cell placement representation and transposition for integrated circuit physical design automation system |
US6058252A (en) * | 1995-01-19 | 2000-05-02 | Synopsys, Inc. | System and method for generating effective layout constraints for a circuit design or the like |
US5884284A (en) * | 1995-03-09 | 1999-03-16 | Continental Cablevision, Inc. | Telecommunication user account management system and method |
US6115546A (en) * | 1996-04-30 | 2000-09-05 | Micron Technology, Inc. | Apparatus and method for management of integrated circuit layout verification processes |
US5787006A (en) * | 1996-04-30 | 1998-07-28 | Micron Technology, Inc. | Apparatus and method for management of integrated circuit layout verification processes |
US5983277A (en) * | 1996-10-28 | 1999-11-09 | Altera Corporation | Work group computing for electronic design automation |
US5910895A (en) * | 1997-06-13 | 1999-06-08 | Teradyne, Inc. | Low cost, easy to use automatic test system software |
US6077308A (en) * | 1997-08-21 | 2000-06-20 | Micron Technology, Inc. | Creating layout for integrated circuit structures |
US6009250A (en) * | 1997-09-30 | 1999-12-28 | Synopsys, Inc. | Selective flattening in layout areas in computer implemented integrated circuit design |
US6237128B1 (en) * | 1997-10-01 | 2001-05-22 | International Business Machines Corporation | Method and apparatus for enabling parallel layout checking of designing VLSI-chips |
US6157947A (en) * | 1998-02-09 | 2000-12-05 | Fujitsu Limited | Method, apparatus, system, and program storage device for distributing intellectual property |
US6550046B1 (en) * | 1998-10-08 | 2003-04-15 | Conexant Systems, Inc. | Method for automated placement of cells in an integrated circuit layout |
US6571374B1 (en) * | 2000-02-28 | 2003-05-27 | International Business Machines Corporation | Invention to allow multiple layouts for a schematic in hierarchical logical-to-physical checking on chips |
US6643683B1 (en) * | 2000-05-08 | 2003-11-04 | International Business Machines Corporation | Interactive client-server environment for performing collaborative timing analysis of circuit designs |
US6742165B2 (en) * | 2001-03-28 | 2004-05-25 | Mips Technologies, Inc. | System, method and computer program product for web-based integrated circuit design |
US6578174B2 (en) * | 2001-06-08 | 2003-06-10 | Cadence Design Systems, Inc. | Method and system for chip design using remotely located resources |
Cited By (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20070300199A1 (en) * | 2006-06-27 | 2007-12-27 | Fujitsu Limited | Design data creating method, design data creating apparatus and computer readable information recording medium |
EP1873664A1 (en) * | 2006-06-27 | 2008-01-02 | Fujitsu Limited | Design data creating method, apparatus and computer readable information recording medium |
US7574684B2 (en) | 2006-06-27 | 2009-08-11 | Fujitsu Limited | Design data creating method, design data creating apparatus and computer readable information recording medium |
US20090064077A1 (en) * | 2007-09-04 | 2009-03-05 | Prasanti Uppaluri | Layout versus schematic error system and method |
US8181137B2 (en) * | 2007-09-04 | 2012-05-15 | Cadence Design Systems, Inc. | Layout versus schematic error system and method |
US8397194B2 (en) | 2007-09-04 | 2013-03-12 | Cadence Design Systems, Inc. | Layout versus schematic error system and method |
US10331843B1 (en) * | 2016-09-27 | 2019-06-25 | Altera Corporation | System and method for visualization and analysis of a chip view including multiple circuit design revisions |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US5831869A (en) | Method of compacting data representations of hierarchical logic designs used for static timing analysis | |
Aoyama | Web-based agile software development | |
Bersoff et al. | Impacts of life cycle models on software configuration management. | |
US5983277A (en) | Work group computing for electronic design automation | |
US5696693A (en) | Method for placing logic functions and cells in a logic design using floor planning by analogy | |
US7325215B2 (en) | Timing violation debugging inside place and route tool | |
US5654898A (en) | Timing-driven integrated circuit layout through device sizing | |
US6954915B2 (en) | System and methods for pre-artwork signal-timing verification of an integrated circuit design | |
US6026220A (en) | Method and apparatus for incremntally optimizing a circuit design | |
US20040098689A1 (en) | Rapid chip management system | |
JP2005517223A (en) | Method for generating design constraints for modules of hierarchical integrated circuit design system | |
US20090172622A1 (en) | Automatic block composition tool for composing custom blocks having non-standard library cells in an integrated circuit design flow | |
WO2003048995A1 (en) | Method of concurrent visualization of process module outputs | |
WO2005119442A2 (en) | Methods and systems for cross-probing in integrated circuit design | |
US20080263480A1 (en) | Language and templates for use in the design of semiconductor products | |
US6910194B2 (en) | Systems and methods for timing a linear data path element during signal-timing verification of an integrated circuit design | |
Simpson | FPGA design | |
JP2910723B2 (en) | Semiconductor integrated circuit design support method, system using the method, and recording medium storing the method | |
US20050268268A1 (en) | Methods and systems for structured ASIC electronic design automation | |
US6836874B2 (en) | Systems and methods for time-budgeting a complex hierarchical integrated circuit | |
US7076410B1 (en) | Method and apparatus for efficiently viewing a number of selected components using a database editor tool | |
US7290224B2 (en) | Guided capture, creation, and seamless integration with scalable complexity of a clock specification into a design flow of an integrated circuit | |
US8239796B2 (en) | Method and system for synthesizing relative timing constraints on an integrated circuit design to facilitate timing verification | |
US20030145300A1 (en) | Layout tracking solutions | |
US7139744B2 (en) | Reorganizing data in log files for data tracking management |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:TRAN, TRUNG;REEL/FRAME:012544/0958 Effective date: 20020125 |
|
AS | Assignment |
Owner name: SUN MICROSYSTEMS, INC., CALIFORNIA Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF THE ASSIGNEE FILED ON 01-28-2002, RECORDED ON REEL 012544 FRAME 0958;ASSIGNOR:TRAN, TRUNG;REEL/FRAME:013409/0152 Effective date: 20021015 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |