+

US20030098489A1 - High temperature processing compatible metal gate electrode for pFETS and methods for fabrication - Google Patents

High temperature processing compatible metal gate electrode for pFETS and methods for fabrication Download PDF

Info

Publication number
US20030098489A1
US20030098489A1 US09/995,031 US99503101A US2003098489A1 US 20030098489 A1 US20030098489 A1 US 20030098489A1 US 99503101 A US99503101 A US 99503101A US 2003098489 A1 US2003098489 A1 US 2003098489A1
Authority
US
United States
Prior art keywords
metal
semi
dielectric layer
sio
conducting substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US09/995,031
Other languages
English (en)
Inventor
Ricky Amos
Douglas Buchanan
Cyril Cabral
Alessandro Callegari
Supratik Guha
Hyungjun Kim
Fenton McFeely
Vijay Narayanan
Kenneth Rodbell
John Yurkas
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
GlobalFoundries Inc
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Priority to US09/995,031 priority Critical patent/US20030098489A1/en
Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AMOS, RICKY, BUCHANAN, DOUGLAS A., CABRAL, JR. CYRIL, CALLEGARI, ALESSANDRO C., GUHA, SUPRATIK, KIM, HYUNGJUN, MCFEELY, FENTON R., NARAYANAN, VIJAY, RODBELL, KENNETH P., YURKAS, JOHN J.
Priority to TW091132960A priority patent/TWI241713B/zh
Priority to JP2003548315A priority patent/JP2005510882A/ja
Priority to PCT/US2002/038476 priority patent/WO2003046998A1/fr
Priority to KR1020047002963A priority patent/KR100754311B1/ko
Priority to AU2002357054A priority patent/AU2002357054A1/en
Publication of US20030098489A1 publication Critical patent/US20030098489A1/en
Priority to US12/197,845 priority patent/US7863083B2/en
Assigned to GLOBALFOUNDRIES U.S. 2 LLC reassignment GLOBALFOUNDRIES U.S. 2 LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: INTERNATIONAL BUSINESS MACHINES CORPORATION
Assigned to GLOBALFOUNDRIES INC. reassignment GLOBALFOUNDRIES INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: GLOBALFOUNDRIES U.S. 2 LLC, GLOBALFOUNDRIES U.S. INC.
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
    • H10D64/665—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes the conductor comprising a layer of elemental metal contacting the insulator, e.g. tungsten or molybdenum
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28079—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a single metal, e.g. Ta, W, Mo, Al
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/3003—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma

Definitions

  • the present invention generally relates to a metal gate electrode for p-type field effect transistors and a method for fabricating the electrode and more particularly, relates to a metal gate electrode that is compatible with high temperature processing of p-type FETs and a method for fabricating the electrode.
  • CMOS complimentary metal oxide semiconductor
  • deposition methods for the gate metals which include thermal evaporation (from Knudsen cells) and chemical vapor deposition are preferable since they lead to minimal gate dielectric damage and minimal long-term reliability problems.
  • Other physical vapor deposition processes such as sputtering and e-beam evaporation lead to gate dielectric damage which is thought to be a long-term reliability problem even if some damage may be repaired by a forming gas or by a hydrogen anneal treatment.
  • chemical vapor deposition has the advantage over thermal evaporation in that it can be used to fill higher aspect ratio damascene features allowing for a wider variety of metal gate integration schemes.
  • MOS metal oxide semiconductor
  • the invention provides a method for fabricating a CMOS gate electrode by using a Re, Rh, Pt, Ir or Ru metal.
  • the work functions of these metals make them compatible with current pFET requirements. For instance, when Re is used, it can withstand the the high hydrogen pressures necessary to produce properly passivated interfaces without undergoing chemical changes. Its thermal stability on SiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 and a variety of other dielectrics makes it compatible with post processing temperatures up to 1000° C.
  • the pFET metal gate avoids the problem of poly-Si depletion and allows for a reduction in the effective capacitance of the device gate stack.
  • the use of a metal gate allows for a thicker gate dielectric than would otherwise be required with a poly-Si gate.
  • the thermal stability of these metal gate materials make them fully compatible with standard post-processing techniques, i.e. activation anneals and the like.
  • the electrode fabrication utilizing Re, Rh, Ir, Pt and Ru in the present invention method is achieved by using a low temperature/low pressure CVD technique with Re 2 (CO) 10 as the source material when Re is to be deposited.
  • a metal oxide semiconductor device which includes a semi-conducting substrate that has source and drain regions; a gate dielectric layer of less than 100 ⁇ thickness on the semi-conducting substrate; and a gate formed of a metal selected from the group consisting of Re, Rh, Ir, Pt and Ru on top of the gate dielectric layer.
  • the gate dielectric layer may have a thickness preferably less than 50 ⁇ .
  • the gate dielectric layer may be formed of a material selected from SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof, or may be formed of a material selected from Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 , La 2 O 3 and mixtures thereof including silicates and nitrogen additions.
  • the dielectric layer may be formed of SiO 2
  • the semi-conducting substrate may be formed of silicon.
  • the semi-conducting substrate may be p-type or n-type.
  • the semi-conducting conducting substrate may be formed of a material selected from the group consisting of silicon, SiGe, SOI, Ge, GaAs and organic semiconductors.
  • the present invention is further directed to a field effect transistor that includes a semi-conducting substrate that has at least one source and one drain region; a gate dielectric layer of less than 100 ⁇ thickness on the semi-conducting substrate; and a gate formed of a metal selected from the group consisting of Re, Rh, Ir, Pt and Ru on top of the gate dielectric layer.
  • the gate dielectric layer may have a thickness preferably less than 50 ⁇ , and may be formed of a material selected from the group consisting of SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof.
  • the dielectric material layer may further be formed of a material selected from Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 , La 2 O 3 and mixtures thereof including silicates and nitrogen additions.
  • the semi-conducting substrate may be p-type or n-type, or may be formed of a material selected from silicon, SiGe, SOI and GaAs. In one specific embodiment, the semi-conducting substrate of the FET is formed of silicon while the gate dielectric layer is formed of SiO 2 .
  • the present invention is still further directed to a method for forming a metal contact in a semiconductor device which can be carried out by the operating steps of depositing a dielectric material layer of less than 100 ⁇ thickness on an active surface of the pre-processed semi-conducting substrate; depositing a layer of metal selected from the group consisting of Re, Rh, Pt, Ir and Ru by a chemical vapor deposition method; patterning the metal layer and forming a metal electrode on the dielectric layer; and passivating the metal electrode and the dielectric layer in forming gas (Ar/H 2 or N 2 /H 2 ).
  • the method for forming a metal contact in a semiconductor device may further include the step of depositing the dielectric layer by a material selected from Si0 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures thereof to a small thickness, preferably to less than 50 ⁇ .
  • the dielectric material layer may further be deposited of a material such as Al 2 O 3 , HfO 2 , ZrO 2 , Y 2 O 3 , La 2 O 3 or mixtures thereof including silicates and nitrogen additions.
  • the method may further include the step of depositing a metal layer of Re by using Re 2 (CO) 10 as a source material by the chemical vapor deposition technique.
  • the method may further include the step of passivating the metal electrode and the dielectric material layer by annealing in forming gas.
  • the method may further include the step of passivating the metal electrode and the dielectric material layer in a high pressure hydrogen process.
  • the method may further include the step of depositing the metal layer in a substantially uniform thickness, or having a thickness variation of less than 10% across the semi-conducting substrate.
  • FIG. 1A is a graph illustrating the results of optical scattering analysis during annealing of a 50 nm CVD Re film on 500 nm SiO 2 in forming gas at 3° C./Sec up to 1000° C. to determine changes in surface roughness or index of refraction.
  • FIG. 1B is a graph of a contour plot of detraction versus temperature that follows the (002) orientation of Re on SiO 2 during annealing in forming gas at 3° C./sec up to 1000° C.
  • FIG. 2A is a graph illustrating the results of optical scattering analysis conducted during annealing of a 30 nm PVD Re film on 300 nm Al 2 O 3 in a forming gas at 3° C./Sec up to 1000° C. to determine changes in surface roughness or index of refraction.
  • FIG. 2B is a graph of a contour plot of detraction angle versus temperature that follows the (002) orientation of Re on Al 2 O 3 during annealing in forming gas at 3° C./sec up to 1000° C.
  • FIG. 3A is a graph showing that PVD 30 nm films of Re, Rh, Pt and Ir deposited on SiO 2 after undergoing various thermal treatments in a forming gas at 3° C./Sec to 450° C., 550° C., 750° and 1000° C. maintain resistivities below 50 micro-Ohm-cm
  • FIG. 3B is a graph similar to FIG. 3A but on a Al 2 O 3 substrate, instead of on SiO 2 .
  • FIG. 4A shows a standard theta/two theta x-ray defraction difractogram indicating a strong Re (002) textured peak at about 40.5° two theta.
  • FIG. 4B is a graph showing a chi scan (fiber plot) further indicating the textured nature of the Re film.
  • FIG. 5 is a graph illustrating typical C-V data for an Re capacitor structure formed with an SiO 2 thickness of about 4.3 nm as-deposited and after a 400° C. forming gas anneal.
  • FIG. 6 is a graph illustrating typical high frequency and quasi-static C-V data for an Re capacitor structure that has an oxide thickness of about 20 nm after a high pressure hydrogen annealing process.
  • FIG. 7 is a graph illustrating C-V data for an Re capacitor structure that has an SiO 2 thickness of 2 nm as-deposited and after a forming gas anneal treatment.
  • FIG. 8 is a graph illustrating I-V data for an Re capacitor structure that has an SiO 2 thickness of 2 nm as-deposited and after a 400° C. forming gas anneal.
  • FIG. 9 is a graph illustrating C-V data for an Re capacitor structure formed on an Al 2 O 3 dielectric that has a ness of about 6 nm.
  • the present invention discloses a method for fabricating a CMOS gate electrode incorporating Re, Rh, Pt, Ir or Ru metal.
  • the work functions of these metals make them compatible with current p-FET requirements.
  • the requirements of the p-FET gate material, presented below, are divided into four sections of deposition techniques, physical characterization, electrical characterization and integration.
  • the Re electrode fabrication in the present invention is achieved by using a low temperature/low pressure CVD technique with Re 2 (CO) 10 as the source material.
  • the method of the present invention comprises the steps of (a) depositing a uniform layer of Re directly onto a dielectric material such as an ultra-thin gate dielectric material, the dielectric material being positioned on a semiconductor substrate, the deposition is carried out by CVD using Re 2 (CO) 10 as the source material under conditions which are sufficient to form the Re layer; and (b) patterning the structure formed in step (a) using simple patterning process including Al deposition and selective wet etching of the structure or standard lithographic techniques to form a test capacitor or MOS transistor containing the p-channel Re gate on the dielectric material.
  • the present invention also provides MOS devices such as FETs which include at least one p-channel Re gate prepared in accordance with the method of the present invention.
  • MOS devices such as FETs which include at least one p-channel Re gate prepared in accordance with the method of the present invention.
  • the devices of the present invention exhibit gate leakage comparable to prior devices prepared in accordance with existing technology and they exhibit the accepted values for metal-gate work functions.
  • the Re electrode is fabricated by a method which includes the steps of:
  • the present invention provides a method for fabricating p-channel Re gates directly onto dielectric materials which are present on MOS devices.
  • the p-channel Re gates produced in accordance with the present method are compatible with ultra-thin gate dielectric materials found on MOS; devices and have resistivity values no greater than 3 ⁇ of the ideal bulk value at a film thickness of 100 nm.
  • a layer of Re is directly deposited on the surface of a dielectric material which is on top of a semiconductor substrate by employing CVD using Re 2 (CO) 10 as the source material under conditions which are sufficient to form Re layer on the dielectric material.
  • the structure containing the Re layer is then patterned using conventional techniques known to those skilled in the art.
  • the CVD apparatus includes a load-locked, coldwall stainless steel reactor which includes a graphite sample holder cartridge.
  • the reactor further includes a boron nitride heater assembly for heating the sample during deposition and two ultra-high vacuum turbo-molecular pumps for controlling the pressure during the deposition providing base pressure of 10 ⁇ 7 torr.
  • the method is not restricted by the method of heating or the material comprising the heater or the nature of the sample holder.
  • the source material dirhenium decacarbonyl (Re 2 (CO) 10 ) is introduced into reactor chamber via a stainless steel valve and is directed to a test wafer which is contained within the reactor.
  • the source material, Re 2 (CO) 10 which is a white solid, is contained in a glass tube and maintained at a constant temperature ranging from 20° C. to 70° C. during the deposition.
  • the precursor is delivered by using Ar (or any inert gas) as a carrier gas and the chamber pressure during growth is controlled by the flow of the Ar carrier gas and the substrate temperature.
  • CVD of Re 2 (CO) 10 occurs at temperatures from about 300° C. to about 550° C. More preferably, the CVD deposition of Re occurs at a temperature from about 350° C. to about 450° C.
  • the total pressure of the reactor (precursor arid carrier gas) during CVD is about 3 E-2 torr.
  • the CVD process typically is carried out for a time period of from about 10 minutes to about 5 hrs. Higher deposition rates can be achieved by using higher precursor temperatures and higher carrier gas flow.
  • a layer of having a thickness of from about 2 nm to about 200 nm, more preferably from about 20 nm to about 100 nm is deposited directly the dielectric material.
  • the ultra-thin dielectric materials employed in the present invention include SiO 2 , nitrided SiO 2 , Si 3 N 4 , metal oxides and mixtures or combinations thereof.
  • the dielectrics employed in the present invention may be grown, deposited or reacted by using techniques known to those skilled in the art.
  • the gate dielectric materials mentioned herein above Si 0 2 lightly nitrided SiO 2 (5% or less total nitride content), Al 2 0 3 , HfO 2 , or ZrO 2 , Y 2 O 3 , are preferred.
  • the samples are patterned using Al as hard masks or standard lithographic techniques known to those skilled in the art. This includes positioning photoresists on the surface of the CVD Re layer; developing the photoresists and removing, via etching techniques, those areas that do not contain the photoresists. Etching may be carried out using wet or dry techniques well known to those skilled in the art.
  • the chemical etchant is selected from the group consisting of H 2 O 2 , chromic acid, phosphoric acid, acetic acid, and the like thereof.
  • the preferred chemical etchant employed in the present invention is H 2 O 2 .
  • dry chemical etching is employed in the present invention, it may be carried out by reactive ion etching (RIE), ion beam etching (IBE) or laser ablation.
  • Test specimens were fabricated using thermally grown silicon dioxide thin films having thicknesses ranging from 2 nm to 20.0 nm for formation of MOS capacitors. Additional experiments were performed on device structure wafers containing dielectric thicknesses from 1 nm to 2 nm and on Al 2 O 3 layers grown by molecular beam epitaxy. Films were grown on p-type or n-type wafers with resistivities between about 0.1 ohm-cm to about 0.2 ohm-cm. Re films were deposited on the test wafers in blanket fashion. Specifically, Re depositions were carried out in a load-locked stainless steel reactor with a base pressure of about 10 ⁇ 7 torr.
  • Dirhenium decacarbonyl, Re 2 (CO) 10 was used as the source gas and admitted into the reactor via a stainless steel valve and directed onto the sample.
  • the precursor delivery rate was controlled by using Ar as a carrier gas.
  • the samples were introduced on a graphite sample holder cartridge which in turn was introduced into a heater assembly located within the reactor chamber.
  • the deposition was conducted in a temperature range of 200° C.-550° C.
  • the growth rate in the system was typically about 0.1 to 1.5 nm/minute depending on precursor and deposition temperature.
  • thermal stability (preferably up to 1000° C.) from agglomeration, from reaction with the dielectric (formation of an interlayer between the gate metal and the dielectric) and reaction with the annealing ambient (forming gas (FG) or hydrogen (H)) is required of the metal gate material.
  • a second requirement is low resistivity, 1 ⁇ 2 milliOhm-cm for the gate contact and more preferably, lower than 50 micro-Ohm-cm for gate contact plus local interconnect use (similar to that with silicides).
  • Rhenium has a resistivity lower than 50 micro-Ohm-cm after a 1000° C. FG anneal treatment on both SiO 2 and Al 2 O 3 dielectrics.
  • the thermal stability of various gate materials in contact with both SiO 2 and Al 2 O 3 dielectrics was investigated using three techniques employing a synchrotron light source.
  • the techniques include time resolved x-ray diffraction analysis used to determine if the metal electrode undergoes an interaction with the dielectric layer or FG annealing ambient, optical scattering and resistance analysis as a function of temperature used to determine if the film undergoes agglomeration or thermal degradation. All three techniques were monitored simultaneously while the samples were heated from 100° C. to 1000° C. in FG. It was determined that for the stack of 30 nm Re, Rh, Pt or Ir on 500 nm SiO 2 or 300 nm Al 2 O 3 , there was no thermal degradation or reactions during the anneal treatments.
  • FIGS. 1 and 2 show the results from a 50 nm CVD Re/500 nm SiO 2 and 30 nm PVD Re/300 nm Al 2 O 3 stack annealed to 1000° C. in FG.
  • FIGS. 1 a and 2 a show that no changes occur in the optical scattering signal indication that the metal surface remains smooth during the anneal treatment.
  • FIG. 1A shows the optical scattering analysis at two different lateral length scales (0.5 and 5 micro meters). Changes indicate surface roughness developing in the film leading to thermal degradation. In this case no changes are seen indicating the film is not agglomerating.
  • FIG. 1B shows the results from annealing a 50 nm CVD Re film on 500 nm SiO2 in FG at 3° C./sec up to 1000° C. The contour plot (diffraction angle vs. temperature with scale indicating x-ray intensity, upper and lower regions of lowest intensity and center region highest intensity) follows the (002) orientation of Re as a function of temperature.
  • FIG. 2A shows the optical scattering analysis at two different lateral length scales (0.5 and 5 micro meters). Changes would indicate surface roughness developing in the film leading to thermal degradation. In this case, no changes are seen indicating the film is not agglomerating.
  • FIG. 2B shows the results from annealing a 30 nm PVD Re film on 300 nm Al 2 O 3 in FG at 3° C./sec up to 1000° C.
  • the contour plot (diffraction angle vs. Temperature with color scale indicating x-ray intensity, top and bottom regions lowest intensity and center region highest intensity) follows the (002) orientation of Re as a function of temperature. Notice the peak moves linearly to lower angles on annealing due to lattice expansion. There are no indications of additional peaks or a decrease in intensity of the (002) peak which would signify a reaction with the dielectric or annealing ambient.
  • the time resolved techniques employed did not show any indication of thermal degradation or reactions for the Re, Rh, Pt and Ir gate materials in contact with SiO 2 or Al 2 0 3 .
  • the time resolved x-ray diffraction technique would only be sensitive to a reaction between the gate metal and the dielectric which forms an interlayer greater than about 4-5 nm in thickness.
  • x-ray reflectivity analysis was used. With this technique, roughness changes at the metal—dielectric interface on the order of a few angstrom's can be detected which would indicate an interaction.
  • the technique also allows the determination of thickness changes in the layers present and in that manner, if the dielectric layer gets thinner or if an interlayer forms this would indicate an interaction between the metal and the dielectric.
  • This technique provides is an indication of the surface roughness of the films. Table 1 summarizes the results. It is noted that as-deposited, the CVD Re films have a 6-7 times higher surface roughness compared to PVD. After a 450° C./30 min. Forming gas anneal treatment, the interface roughness of the Re, Rh and Ir samples increase only slightly indicating very little interaction between the metal and dielectric. The Pt film actually became smoother after the FG anneal treatment.
  • FIGS. 3A and 3B show that PVD 30 nm films of Re, Rh, Pt, and Ir after undergoing various thermal treatments (annealing in FG at 3° C./sec to 450° C., 550° C., 750° C., and 1000° C.) maintain resistivities below 50 micro-Ohm-cm.
  • FIG. 3A shows the results for films deposited on 500 nm SiO 2 and FIG. 3B on a 300 nm Al 2 O 3 dielectric. These results indicate that the films are thermally stable and can be used in a standard high temperature integration scheme not only as the gate contact but also as local interconnects.
  • FIG. 4A shows a standard theta/two theta x-ray diffraction difractogram which indicates the strong Re (002) textured peak at about 40.5° two theta.
  • FIG. 4B shows a chi scan (fiber plot) further indicating the highly textured nature of the film.
  • capacitors were patterned using evaporated 60 nm thick Al dots as a hard mask for wet etching.
  • the rhenium film was wet-etched using H 2 O 2 . Capacitor structures were thus formed with areas ranging from about 1 E-6 to about 1 E-2 cm 2 Additionally, Re films were patterned by wet etching using standard lithography techniques for device structure wafers.
  • FIG. 5 shows typical C-V data for Re gate capacitor structures formed on an SiO 2 dielectric which had a thickness of about 4.3 nm. Data is shown for capacitors formed on n-type silicon wafers. The dotted and solid lines show the C-V data before and after a standard post metal gate deposition forming gas anneal (FGA) step which is carried out in 10% H in nitrogen at 400° C. for about 30 minutes.
  • FGA standard post metal gate deposition forming gas anneal
  • C-V data shows interface state densities in the low 3 ⁇ 4 E 11 cm ⁇ 2 eV ⁇ 1 for samples subjected to FGA.
  • the as-deposited sample has some defect states as seen in FIG. 5, which can be removed by a standard FGA step.
  • C-V data were obtained for other Re capacitors with dielectric thickness ranging from 2 ⁇ 20 nm and the work function was determined to be 5.0 eV. This, in itself, demonstrates that the Fermi-level of the metal gate is situated very close to silicon valence band edge indicating that Re is an appropriate choice for p-FET MOS structure.
  • the conventional FGA produces an acceptable range of interface state densities, it can be improved by using newly developed high pressure H 2 annealing process.
  • the process is performed in a load lock chamber using a He lamp heater.
  • the patterned samples are loaded in the chamber and maintained at 350° C. and high pressure H 2 is introduced, typically 400 torr for 30 minutes.
  • the interface state densities are reduced to (3 ⁇ 4) E 10 cm ⁇ 2 eV ⁇ 1 .
  • FIG. 6 shows typical high frequency and quasi-static C-V data for Re capacitor structures having an oxide thickness of about 20 nm after the high pressure annealing process.
  • C-V and I-V data for capacitor device structures employing Re having an oxide thickness of 2 nm are shown in FIGS. 7 and 8.
  • the dotted and solid lines show the C-V and I-V data before and after a standard FGA step.
  • FIG. 9 shows C-V data for Re capacitor structures formed on Al 2 O 3 dielectrics having a thickness of about 6 nm.
  • the capacitor is formed on an n-type silicon wafer.
  • the flat band voltage was about 0.48 eV, which is essentially the same as on SiO 2 .
  • FIG. 9 is a high frequency and quasi-static capacitance-voltage plot for a Re capacitor structure formed in accordance with the present invention on an Al 2 O 3 film having a thickness of 6 nm after the FGA.
  • the integration scheme chosen determines the maximum temperature the gate metal/dielectric will have to withstand.
  • the stack will have to withstand 1000° C. thermal treatments. For at least a few seconds, as mentioned above, Re, Rh, Pt, Ir and Ru can withstand such treatments without thermal degradation.
  • Two additional possible integration schemes include having the metal/dielectric combination in place before source and drain silicide formation but not before the activation anneals. In this case the combination would have to withstand anneal treatments at 750° C. for CoSi 2 formation.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thin Film Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
US09/995,031 2001-11-29 2001-11-29 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication Abandoned US20030098489A1 (en)

Priority Applications (7)

Application Number Priority Date Filing Date Title
US09/995,031 US20030098489A1 (en) 2001-11-29 2001-11-29 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
TW091132960A TWI241713B (en) 2001-11-29 2002-11-08 High temperature processing compatible metal gate electrode for pFETs and method for fabrication
AU2002357054A AU2002357054A1 (en) 2001-11-29 2002-11-27 High temperature processing compatible metal gate electrode for pfets and method for fabrication
KR1020047002963A KR100754311B1 (ko) 2001-11-29 2002-11-27 금속 산화물 반도체 소자, 전계 효과 트랜지스터 및 이에 제공되는 금속 접점 형성 방법
PCT/US2002/038476 WO2003046998A1 (fr) 2001-11-29 2002-11-27 Electrode grille metallique compatible avec un traitement haute temperature destinee a des tec de type p et procede de fabrication
JP2003548315A JP2005510882A (ja) 2001-11-29 2002-11-27 高温プロセスに適合するｐＦＥＴ用金属ゲート電極およびその製作方法
US12/197,845 US7863083B2 (en) 2001-11-29 2008-08-25 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/995,031 US20030098489A1 (en) 2001-11-29 2001-11-29 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/197,845 Division US7863083B2 (en) 2001-11-29 2008-08-25 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

Publications (1)

Publication Number Publication Date
US20030098489A1 true US20030098489A1 (en) 2003-05-29

Family

ID=25541322

Family Applications (2)

Application Number Title Priority Date Filing Date
US09/995,031 Abandoned US20030098489A1 (en) 2001-11-29 2001-11-29 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
US12/197,845 Expired - Fee Related US7863083B2 (en) 2001-11-29 2008-08-25 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

Family Applications After (1)

Application Number Title Priority Date Filing Date
US12/197,845 Expired - Fee Related US7863083B2 (en) 2001-11-29 2008-08-25 High temperature processing compatible metal gate electrode for pFETS and methods for fabrication

Country Status (6)

Country Link
US (2) US20030098489A1 (fr)
JP (1) JP2005510882A (fr)
KR (1) KR100754311B1 (fr)
AU (1) AU2002357054A1 (fr)
TW (1) TWI241713B (fr)
WO (1) WO2003046998A1 (fr)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060068097A1 (en) * 2004-09-30 2006-03-30 Tokyo Electron Limited method for forming a passivated metal layer
US20060068588A1 (en) * 2004-09-30 2006-03-30 Tokyo Electron Limited Low-pressure deposition of ruthenium and rhenium metal layers from metal carbonyl precursors
US20070142619A1 (en) * 2002-03-15 2007-06-21 Lucent Technologies Inc. Forming electrical contacts to a molecular layer
US20100099223A1 (en) * 2007-11-01 2010-04-22 Infineon Technologies Ag Integrated circuit device and method
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4718272B2 (ja) * 2005-08-10 2011-07-06 東京エレクトロン株式会社 レニウム系膜の成膜方法、ゲート電極の形成方法、半導体装置の製造方法、およびコンピュータ読取可能な記憶媒体
US8420473B2 (en) 2010-12-06 2013-04-16 International Business Machines Corporation Replacement gate devices with barrier metal for simultaneous processing
EP2676291A1 (fr) * 2011-02-14 2013-12-25 Natcore Technology, Inc. Procédé d'amélioration de l'effet de passivation de films sur un substrat
US8836048B2 (en) 2012-10-17 2014-09-16 International Business Machines Corporation Field effect transistor device having a hybrid metal gate stack

Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040610A (en) * 1997-04-08 2000-03-21 Kabushiki Kaisha Toshiba Semiconductor device
US6043536A (en) * 1998-05-19 2000-03-28 Kabushiki Kaisha Toshiba Semiconductor device
US6238933B1 (en) * 1999-05-06 2001-05-29 Ramtron International Corporation Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors
US6248673B1 (en) * 2000-02-23 2001-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Hydrogen thermal annealing method for stabilizing microelectronic devices
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
US20010032995A1 (en) * 2000-01-19 2001-10-25 Jon-Paul Maria Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same
US6403997B1 (en) * 1997-06-30 2002-06-11 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor devices
US6458695B1 (en) * 2001-10-18 2002-10-01 Chartered Semiconductor Manufacturing Ltd. Methods to form dual metal gates by incorporating metals and their conductive oxides
US20020155689A1 (en) * 2001-04-20 2002-10-24 Ahn Kie Y. Highly reliable gate oxide and method of fabrication
US6476454B2 (en) * 2000-03-27 2002-11-05 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US20030011080A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method of fabricating sio2 spacers and annealing caps
US6512297B2 (en) * 1998-05-07 2003-01-28 Mitsubishi Denki Kabushiki Kaisha CVD source material for forming an electrode, and electrode and wiring film for capacitor formed therefrom
US6514843B2 (en) * 2001-04-27 2003-02-04 International Business Machines Corporation Method of enhanced oxidation of MOS transistor gate corners
US6541320B2 (en) * 2001-08-10 2003-04-01 International Business Machines Corporation Method to controllably form notched polysilicon gate structures
US6614079B2 (en) * 2001-07-19 2003-09-02 International Business Machines Corporation All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
US6664186B1 (en) * 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US20040080001A1 (en) * 1999-03-01 2004-04-29 Kiyoshi Takeuchi Complementary integrated circuit and method of manufacturing same

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03227562A (ja) 1990-02-01 1991-10-08 Nec Corp 絶縁ゲート電界効果トランジスタとその製造方法
JP3332676B2 (ja) 1994-08-02 2002-10-07 キヤノン株式会社 電子放出素子、電子源及び画像形成装置と、それらの製造方法
US5514628A (en) * 1995-05-26 1996-05-07 Texas Instruments Incorporated Two-step sinter method utilized in conjunction with memory cell replacement by redundancies
US5895274A (en) * 1996-01-22 1999-04-20 Micron Technology, Inc. High-pressure anneal process for integrated circuits
US5789312A (en) 1996-10-30 1998-08-04 International Business Machines Corporation Method of fabricating mid-gap metal gates compatible with ultra-thin dielectrics
JP3892588B2 (ja) 1997-12-26 2007-03-14 株式会社東芝 半導体装置およびその製造方法
US6008091A (en) * 1998-01-27 1999-12-28 Lucent Technologies Inc. Floating gate avalanche injection MOS transistors with high K dielectric control gates
JP3439370B2 (ja) * 1999-04-21 2003-08-25 Ｎｅｃエレクトロニクス株式会社 半導体メモリ装置の製造方法
US6376349B1 (en) * 2000-01-19 2002-04-23 Motorola, Inc. Process for forming a semiconductor device and a conductive structure
US6984591B1 (en) * 2000-04-20 2006-01-10 International Business Machines Corporation Precursor source mixtures

Patent Citations (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6040610A (en) * 1997-04-08 2000-03-21 Kabushiki Kaisha Toshiba Semiconductor device
US6403997B1 (en) * 1997-06-30 2002-06-11 Kabushiki Kaisha Toshiba Method for manufacturing semiconductor devices
US6512297B2 (en) * 1998-05-07 2003-01-28 Mitsubishi Denki Kabushiki Kaisha CVD source material for forming an electrode, and electrode and wiring film for capacitor formed therefrom
US6043536A (en) * 1998-05-19 2000-03-28 Kabushiki Kaisha Toshiba Semiconductor device
US20040080001A1 (en) * 1999-03-01 2004-04-29 Kiyoshi Takeuchi Complementary integrated circuit and method of manufacturing same
US6238933B1 (en) * 1999-05-06 2001-05-29 Ramtron International Corporation Polarization method for minimizing the effects of hydrogen damage on ferroelectric thin film capacitors
US20010032995A1 (en) * 2000-01-19 2001-10-25 Jon-Paul Maria Lanthanum oxide-based gate dielectrics for integrated circuit field effect transistors and methods of fabricating same
US6300208B1 (en) * 2000-02-16 2001-10-09 Ultratech Stepper, Inc. Methods for annealing an integrated device using a radiant energy absorber layer
US6248673B1 (en) * 2000-02-23 2001-06-19 Taiwan Semiconductor Manufacturing Company, Ltd. Hydrogen thermal annealing method for stabilizing microelectronic devices
US6476454B2 (en) * 2000-03-27 2002-11-05 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6664186B1 (en) * 2000-09-29 2003-12-16 International Business Machines Corporation Method of film deposition, and fabrication of structures
US20020155689A1 (en) * 2001-04-20 2002-10-24 Ahn Kie Y. Highly reliable gate oxide and method of fabrication
US6514843B2 (en) * 2001-04-27 2003-02-04 International Business Machines Corporation Method of enhanced oxidation of MOS transistor gate corners
US20030011080A1 (en) * 2001-07-11 2003-01-16 International Business Machines Corporation Method of fabricating sio2 spacers and annealing caps
US6614079B2 (en) * 2001-07-19 2003-09-02 International Business Machines Corporation All-in-one disposable/permanent spacer elevated source/drain, self-aligned silicide CMOS
US6541320B2 (en) * 2001-08-10 2003-04-01 International Business Machines Corporation Method to controllably form notched polysilicon gate structures
US6458695B1 (en) * 2001-10-18 2002-10-01 Chartered Semiconductor Manufacturing Ltd. Methods to form dual metal gates by incorporating metals and their conductive oxides

Cited By (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20070142619A1 (en) * 2002-03-15 2007-06-21 Lucent Technologies Inc. Forming electrical contacts to a molecular layer
US11043571B2 (en) 2002-08-12 2021-06-22 Acorn Semi, Llc Insulated gate field effect transistor having passivated schottky barriers to the channel
US11355613B2 (en) 2002-08-12 2022-06-07 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11056569B2 (en) 2002-08-12 2021-07-06 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US11018237B2 (en) 2002-08-12 2021-05-25 Acorn Semi, Llc Method for depinning the fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10937880B2 (en) 2002-08-12 2021-03-02 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US10950707B2 (en) 2002-08-12 2021-03-16 Acorn Semi, Llc Method for depinning the Fermi level of a semiconductor at an electrical junction and devices incorporating such junctions
US20060068097A1 (en) * 2004-09-30 2006-03-30 Tokyo Electron Limited method for forming a passivated metal layer
US7189431B2 (en) 2004-09-30 2007-03-13 Tokyo Electron Limited Method for forming a passivated metal layer
WO2006038954A1 (fr) * 2004-09-30 2006-04-13 Tokyo Electron Limited Depot a basse pression de couches metalliques a base de ruthenium et de rhenium a partir de precurseurs de carbonyle metalliques
KR101178663B1 (ko) * 2004-09-30 2012-08-30 인터내셔널 비지네스 머신즈 코포레이션 패시배이팅된 금속층을 형성하기 위한 방법
WO2006039219A1 (fr) * 2004-09-30 2006-04-13 Tokyo Electron Limited Procede et systeme pour former une couche metallique passivee
US20060068588A1 (en) * 2004-09-30 2006-03-30 Tokyo Electron Limited Low-pressure deposition of ruthenium and rhenium metal layers from metal carbonyl precursors
US20100099223A1 (en) * 2007-11-01 2010-04-22 Infineon Technologies Ag Integrated circuit device and method
US8187964B2 (en) 2007-11-01 2012-05-29 Infineon Technologies Ag Integrated circuit device and method
US10879366B2 (en) 2011-11-23 2020-12-29 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11610974B2 (en) 2011-11-23 2023-03-21 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US11804533B2 (en) 2011-11-23 2023-10-31 Acorn Semi, Llc Metal contacts to group IV semiconductors by inserting interfacial atomic monolayers
US10872964B2 (en) 2016-06-17 2020-12-22 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US11843040B2 (en) 2016-06-17 2023-12-12 Acorn Semi, Llc MIS contact structure with metal oxide conductor
US10833199B2 (en) 2016-11-18 2020-11-10 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US11462643B2 (en) 2016-11-18 2022-10-04 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height
US12034078B2 (en) 2016-11-18 2024-07-09 Acorn Semi, Llc Nanowire transistor with source and drain induced by electrical contacts with negative Schottky barrier height

Also Published As

Publication number Publication date
JP2005510882A (ja) 2005-04-21
KR20040053117A (ko) 2004-06-23
WO2003046998A1 (fr) 2003-06-05
AU2002357054A1 (en) 2003-06-10
TW200300605A (en) 2003-06-01
US7863083B2 (en) 2011-01-04
TWI241713B (en) 2005-10-11
KR100754311B1 (ko) 2007-09-03
US20080311745A1 (en) 2008-12-18

Similar Documents

Publication Publication Date Title
US7863083B2 (en) High temperature processing compatible metal gate electrode for pFETS and methods for fabrication
US7667278B2 (en) Metal carbide gate structure and method of fabrication
US5789312A (en) Method of fabricating mid-gap metal gates compatible with ultra-thin dielectrics
US7042033B2 (en) ULSI MOS with high dielectric constant gate insulator
KR100204083B1 (ko) 다중충 구조에서의 테신 산소 확산 장벽
US6017784A (en) Manufacture method of semiconductor device with suppressed impurity diffusion from gate electrode
US6787451B2 (en) Semiconductor device and manufacturing method thereof
US7671471B2 (en) Method for making a semiconductor device having a high-k dielectric layer and a metal gate electrode
US6743668B2 (en) Process for forming a metal oxy-nitride dielectric layer by varying the flow rate of nitrogen into the chamber
US7820503B2 (en) Semiconductor device and manufacturing method of the same
US20050130380A1 (en) Semiconductor device structures including metal silicide interconnects and dielectric layers at substantially the same fabrication level
Ohmi ULSI reliability through ultraclean processing
US7867918B1 (en) Semiconductor topography including a thin oxide-nitride stack and method for making the same
US6635938B1 (en) Semiconductor device and manufacturing method thereof
US6284636B1 (en) Tungsten gate method and apparatus
TWI285922B (en) Dual-tank etch method for oxide thickness control
US20070267706A1 (en) Formation of low leakage thermally assisted radical nitrided dielectrics
Burte et al. Cobalt disilicide formed by rapid thermal annealing and throughmetal arsenic implantation
EP1437766A2 (fr) Transistor MOS et sa méthode de fabrication
Clevenger et al. Symposium
Han Fabrication and device characterization of alternative gate stacks using the non self-aligned gate process
JPH01266745A (ja) 半導体装置の製造方法
Gopalan by Sundararaman Gopalan

Legal Events

Date Code Title Description
AS Assignment

Owner name: INTERNATIONAL BUSINESS MACHINES CORPORATION, NEW Y

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:AMOS, RICKY;BUCHANAN, DOUGLAS A.;CABRAL, JR. CYRIL;AND OTHERS;REEL/FRAME:012332/0260

Effective date: 20011017

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

AS Assignment

Owner name: GLOBALFOUNDRIES U.S. 2 LLC, NEW YORK

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:INTERNATIONAL BUSINESS MACHINES CORPORATION;REEL/FRAME:036550/0001

Effective date: 20150629

AS Assignment

Owner name: GLOBALFOUNDRIES INC., CAYMAN ISLANDS

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:GLOBALFOUNDRIES U.S. 2 LLC;GLOBALFOUNDRIES U.S. INC.;REEL/FRAME:036779/0001

Effective date: 20150910

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载