US20030038344A1 - Through-via vertical interconnects, through-via heat sinks and associated fabrication methods - Google Patents
Through-via vertical interconnects, through-via heat sinks and associated fabrication methods Download PDFInfo
- Publication number
- US20030038344A1 US20030038344A1 US10/227,089 US22708902A US2003038344A1 US 20030038344 A1 US20030038344 A1 US 20030038344A1 US 22708902 A US22708902 A US 22708902A US 2003038344 A1 US2003038344 A1 US 2003038344A1
- Authority
- US
- United States
- Prior art keywords
- substrate
- layer
- interconnect
- dielectric layer
- conductive
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Abandoned
Links
Images
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/0011—Working of insulating substrates or insulating layers
- H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4857—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/486—Via connections through the substrate with or without pins
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/15—Ceramic or glass substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
- H01L23/367—Cooling facilitated by shape of device
- H01L23/3677—Wire-like or pin-like cooling fins or heat sinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5383—Multilayer substrates
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5384—Conductive vias through the substrate with or without pins, e.g. buried coaxial conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/03—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
- H01L25/0657—Stacked arrangements of devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of semiconductor or other solid state devices
- H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, the devices being individual devices of subclass H10D or integrated devices of class H10
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/40—Arrangement of two or more semiconductor lasers, not provided for in groups H01S5/02 - H01S5/30
- H01S5/42—Arrays of surface emitting lasers
- H01S5/423—Arrays of surface emitting lasers having a vertical cavity
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/46—Manufacturing multilayer circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/05001—Internal layers
- H01L2224/05005—Structure
- H01L2224/05009—Bonding area integrally formed with a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13023—Disposition the whole bump connector protruding from the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/13099—Material
- H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
- H01L2224/16146—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked the bump connector connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06513—Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06541—Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
- H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
- H01L2225/06503—Stacked arrangements of devices
- H01L2225/06589—Thermal management, e.g. cooling
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12044—OLED
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/0206—Substrates, e.g. growth, shape, material, removal or bonding
- H01S5/0207—Substrates having a special shape
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/02—Structural details or components not essential to laser action
- H01S5/022—Mountings; Housings
- H01S5/0235—Method for mounting laser chips
- H01S5/02355—Fixing laser chips on mounts
- H01S5/0237—Fixing laser chips on mounts by soldering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01S—DEVICES USING THE PROCESS OF LIGHT AMPLIFICATION BY STIMULATED EMISSION OF RADIATION [LASER] TO AMPLIFY OR GENERATE LIGHT; DEVICES USING STIMULATED EMISSION OF ELECTROMAGNETIC RADIATION IN WAVE RANGES OTHER THAN OPTICAL
- H01S5/00—Semiconductor lasers
- H01S5/04—Processes or apparatus for excitation, e.g. pumping, e.g. by electron beams
- H01S5/042—Electrical excitation ; Circuits therefor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/03—Use of materials for the substrate
- H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/01—Dielectrics
- H05K2201/0137—Materials
- H05K2201/0179—Thin film deposited insulating layer, e.g. inorganic layer for printed capacitor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
- H05K2201/09—Shape and layout
- H05K2201/09209—Shape and layout details of conductors
- H05K2201/095—Conductive through-holes or vias
- H05K2201/09581—Applying an insulating coating on the walls of holes
Definitions
- the present invention relates to semiconductor devices, and more particularly to through-via vertical interconnects and through-via heat sinks and related methods for fabricating the same.
- substrate-to-substrate electrical and electro-optic interconnections were limited to connecting devices by wire bond techniques. This meant that in most instances, the substrates existed in a linear, two-dimensional orientation with wires connecting the desired devices.
- through-via interconnects i.e., connections made from one side of the substrate through to the opposite side of the substrate
- stacked configurations provide for a more compact packaging design and allow for fabrication of high-density devices, such as sensor or transducer arrays.
- through-via interconnects provide for interconnections between different series of devices.
- analog devices such as transistors or the like may be fabricated on one substrate while digital devices, such as data processing components may be fabricated on a second substrate.
- Cost constraints and fabrication concerns make it impractical to combine the analog and digital devices on a single substrate.
- through-via interconnects provide a means for connecting dissimilar devices in a dense, stacked packaging environment.
- through-via interconnects are fabricated using some level of high temperature processing.
- dielectric layers in the form of oxides are typically formed by a thermal oxidation process that occurs at temperatures in excess of 1000° C.
- Such high temperature processing limits the formation of the through-via interconnects to a front-end process (i.e., before devices are formed on the substrate).
- Most devices subsequently formed on the substrate would be negatively impacted from a functionality and reliability perspective if they were to be subject to such high temperature processing at the back-end of the overall fabrication process.
- Back-end processing of the through-via interconnects is desirable due to the manner in which substrate processing and device fabrication are typically undertaken.
- devices are formed on a thick substrate and then a significant portion of the backside of the substrate is etched away as a means of thinning the substrate post device formation.
- Forming the through-via interconnects prior to the substrate etch processing would be impractical because the aspect ratios of the vias would be so high that conformal deposition within the via walls could not be achieved.
- PECVD plasma-enhanced chemical vapor deposition
- other known low temperature processes do not provide for conformal deposition within the interior walls of the through-via.
- these processes are not able to provide conformal deposition to vias having high aspect ratios of 3:1, 4:1 or 5:1 (height of via to diameter of via).
- Conformal coverage of the walls of the via is required for further fabrication of the interconnect and insures proper electrical or optical signal transmission through the resulting interconnect.
- the present invention provides for improved through-via vertical interconnects and through-via heat sinks.
- the devices benefit from an organic dielectric layer that allows for low-temperature deposition processing.
- the low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry.
- the through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs.
- the interconnects can be formed with a high aspect ratio, in the range of about 10:1, substrate thickness to interconnect diameter.
- the invention is embodied in a through-via vertical interconnect device.
- the device comprises a substrate having at least one via formed therein, an organic dielectric layer disposed on the surface of the at least one via, and a first conductive layer disposed on the dielectric layer that forms a through-via vertical interconnect between a first generally planar surface of the substrate and a second generally planar surface of the substrate.
- the organic dielectric material comprises a parylene material such as Parylene C, N or D.
- the dielectric layer and first interconnect layer are disposed while the substrate is held at a temperature of less than about 300 degrees Celsius. This low temperature processing allows for the interconnects to be formed at the back-end of the manufacturing process, after active devices and electrical circuitry have been formed on the substrate.
- the device may comprise a diffusion barrier layer disposed on the surface of the at least one via between the dielectric layer and the first conductive layer and an adhesion-promoting device disposed between the first conductive layer and the layer adjacent to the first conductive layer.
- the through-via vertical interconnect will include a second conductive layer disposed on the first conductive layer, the second conductive layer serving the purpose of generally filling the at least one via.
- a method for fabricating through-via vertical interconnects comprises the steps of forming at least one via in a substrate, disposing an organic dielectric layer on the surface of the at least one via and disposing a first conductive interconnect layer on the dielectric layer such that the conductive interconnect layer forms a through-via vertical interconnect between a first generally planar surface of the substrate and a second generally planar surface of the substrate. Additionally, the steps of disposing the organic dielectric and the first conductive layer are accomplished while maintaining the substrate at a temperature of below about 300.
- the low temperature process is typically maintained by disposing the dielectric layer by vapor phase deposition, such as pyrolytic decomposition coupled with room temperature polymerization and disposing the first conductive interconnect layer by metal-organic chemical vapor deposition (MOCVD) processing.
- vapor phase deposition such as pyrolytic decomposition coupled with room temperature polymerization
- MOCVD metal-organic chemical vapor deposition
- the etch process will typically entail a deep reactive ion etch procedure that provides for vias having a high aspect ratio.
- the method for fabricating a through-via vertical interconnect may entail additional processing steps. These additional steps include disposing, between the dielectric layer and the first conductive interconnect layer, a diffusion barrier layer on the via surface of the at least one via.
- the diffusion barrier layer prevents diffusion of metal atoms in high temperature applications.
- the additional step of disposing an adhesion-promoting layer may be necessary to promote adhesion between the conductive layer and adjacent layers. In most applications it will be necessary to dispose a second conductive interconnect layer on the first conductive interconnect layer such that the second conductive interconnect layer generally fills the at least one via. In these applications the first conductive layer serves as a seed layer for the subsequently formed second conductive layer.
- a method for semiconductor manufacturing comprises the steps of fabricating active devices and/or electrical circuitry on the surface of a semiconductor substrate. Subsequent to the formation of the active devices and/or electrical circuitry, through-via vertical interconnects are formed in the substrate. Low temperature processing of the through-via vertical interconnects provides for the interconnects to be fabricated after the other structures, circuits and devices have been fabricated on the substrate.
- the invention is also embodied in a multi-substrate semiconductor device.
- the multi-layered semiconductor device will include a stack of two or more substrates.
- One or more of the substrates in the stack will include one or more through-via vertical interconnects.
- the one or more through-via vertical interconnects comprising vias formed in the substrate, an organic dielectric layer and a first conductive layer.
- the through-via vertical interconnects are typically defined by being fabricated while the substrate is held at temperatures below about 300° C.
- the through-via interconnects serve to electrically connect devices and circuits on one substrate to devices and circuits on another substrate in the stack.
- the substrates in the stack may be formed all of the same material, e.g., silicon, or the substrates may be formed of dissimilar materials to accommodate electrical and electro-optical connections. Additionally, the multi-substrate device may comprise through-via heat sink structures that provide for a continuous path for heat flow through the entirety of the multiple-substrate semiconductor device.
- the present invention provides for improved through-via vertical interconnects and through-via heat sinks.
- the low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry.
- the through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs.
- the interconnects can be formed with a high aspect ratio, in the range of up to about 10:1, substrate thickness to interconnect diameter.
- FIG. 1 is a cross-sectional view of through-via vertical interconnects in a substrate, in accordance with an embodiment of the present invention.
- FIGS. 2 A- 2 D are cross-sectional views of various fabrication stages in the processing of through-via vertical interconnects, in accordance with an embodiment of the present invention.
- FIG. 3 is a flow diagram of a process for fabricating through-via vertical interconnects, in accordance with an embodiment of the present invention.
- FIG. 4 is a top view perspective of through-via vertical interconnects and through-via heat sink structures, in accordance with an embodiment of the present invention.
- FIG. 5 is a cross-sectional diagram of through-via heat sink and through-via vertical interconnect, in accordance with an alternate embodiment of the present invention.
- FIG. 6 is a cross-sectional diagram of a multiple-substrate semiconductor device implementing through-via vertical interconnects, through-via heat sinks and adhesive bonding, in accordance with an embodiment of the present invention.
- FIG. 7 is a cross-sectional diagram of a multiple-substrate semiconductor device implementing through-via vertical interconnects and solder bumping, in accordance with an embodiment of the present invention.
- FIG. 1 is a cross sectional diagram of a through-via vertical interconnect (TVI) in accordance with an embodiment of the present invention.
- the through-via vertical interconnect 10 includes a substrate 12 having one or more vias 14 formed therein.
- the substrate will typically comprise silicon although any other suitable substrate material may also be used to form the substrate. Examples of other suitable substrate materials include gallium arsenide, ceramic materials, glass materials and the like.
- the invention provides for vias that can be formed with high aspect ratios, typically in the range of about 4:1 to about 10:1; substrate thickness to via diameter ratio. For example, a 500 micrometer thick substrate will be able to accommodate vias having diameters as small as 50 micrometers. Such high aspect ratios are made possible by the capability of the invention to provide conformal layering of materials within the interior wall 16 of the vias 14 .
- the surface of the substrate 12 and the interior wall 16 of the one or more vias 14 have disposed thereon an organic dielectric layer 18 .
- the organic dielectric material will comprise a parylene material, such as Parylene C, N or D.
- the dielectric layer may be formed of oxides, nitrides or other compounds if a low-temperature (i.e., below 300° C.), conformal deposition technique is implemented.
- the dielectric layer provides electrical isolation between the substrate and the conductive elements of the one or more though-via vertical interconnects.
- the organic dielectric material will be formed by low temperature processing; i.e., processing below about 300 degrees Celsius (° C.), preferably about 200° C.
- a vapor phase deposition technique such as pyrolytic decomposition processing coupled with vacuum polymerization, may be used to form the dielectric layer at a temperature of about 200° C.
- the dielectric layer will typically have a thickness in the range of about 500 angstroms to about 5000 angstroms, preferably about 2000 angstroms.
- the through-via vertical interconnect 10 structure may also include optional diffusion barrier layer 20 .
- the diffusion barrier layer is implemented to prevent thermal diffusion of the subsequently formed conductive interconnect material.
- a diffusion barrier layer will typically be implemented in the through-via vertical interconnect structure if the resulting device is used in a high-temperature application, e.g., a sensor in an automotive application. In low temperature applications it may not be necessary to construct the interconnect of the present invention with a diffusion barrier layer.
- the diffusion barrier layer is typically disposed using conventional low-temperature CVD or sputtering techniques.
- the diffusion barrier layer may be formed of a refractory-metal nitride material, such as titanium nitride (TiN).
- the diffusion barrier layer will typically have a thickness in the range of about 500 angstroms to about 5000 angstroms, preferably about 2000 angstroms.
- an optional adhesion-promoting layer 22 between the dielectric layer 18 and the subsequently formed conductive interconnect materials.
- many conductive materials such as copper and gold have poor adhesion characteristics and require an adhesion-promoter to insure proper adhesion to adjacent layers in the construct.
- the diffusion barrier layer may provide adequate adhesion-promoting characteristics.
- the adhesion-promoting layer may be formed of TiN or any other suitable material.
- the adhesion promoting layer will typically have a thickness in the range of about 50 angstroms to about 200 angstroms, preferably about 100 angstroms.
- the adhesion-promoting layer can be formed by sputtering or any other suitable low temperature process.
- the through-via vertical interconnect 10 will include a first conductive layer 24 disposed on either the organic dielectric layer 18 or, if required, the diffusion barrier layer 20 or the adhesion-promoting layer 22 .
- the first conductive layer may act as a seed layer for a subsequently formed second conductive layer 26 that fills in the via in its entirety.
- the first conductive layer is typically formed by a metal-organic chemical vapor deposition (MOCVD) technique or any other suitable low-temperature process.
- the first conductive layer may comprise copper, gold or any other suitable conductive material.
- the first conductive layer will typically have a thickness in the range of about 0.5 micrometers to 5 micrometers, preferably about 1 micrometer.
- the processing of the second conductive layer will typically occur after a masking operation has defined the areas 28 on the surface of the substrate 12 that will form the conductive interconnect contacts leading to active devices (not shown in FIG. 1).
- the second conductive layer is typically formed by an electrochemical deposition technique or any other suitable low-temperature process.
- the second conductive layer may comprise copper, gold or any other suitable conductive material and will typically be equivalent to the material used to form the first conductive layer.
- the thickness of the second conductive layer will generally be dictated by the diameter of the via that requires filling.
- FIGS. 2 A- 2 D are cross-sectional diagrams of various stages in the fabrication process of a through-via vertical interconnect device, in accordance with a method of manufacturing embodiment of the present invention.
- the fabrication process implements low-temperature processing that allows for through-via vertical interconnects to be formed on the substrate after active devices and circuitry have been fabricated.
- FIG. 2A depicts a cross-sectional representation of a substrate 12 having one or more vias 14 formed therein.
- photolithographic patterning is used to define and pattern the regions on the substrate where the vias will be formed.
- an etch process such as deep reactive-ion etching, is implemented to create high-aspect through substrate vias.
- FIG. 2B depicts a cross-sectional representation of the through-via vertical interconnect structure following formation of the dielectric layer 18 and the optional diffusion barrier layer 20 .
- the dielectric layer is disposed by low temperature processing; i.e., processing below about 300 degrees Celsius (° C.), preferably about 200° C.
- a vapor phase deposition technique such as pyrolytic decomposition coupled with room temperature polymerization may be used to form the dielectric layer at a temperature of about 200° C.
- Pyrolytic decomposition involves vaporizing a monomer, heating the vapor to a cracking temperature to break bonds and condensing the products on the surface of the substrate to form a polymer (i.e., surface polymerization).
- the substrate construct While the vapor in the process exceeds the low temperature threshold of about 300° C., the substrate construct is kept at a low temperature (i.e., typically room temperature) to facilitate the surface polymerization process.
- the diffusion barrier layer is disposed by a low temperature processing technique, such as metal-organic chemical vapor deposition (MOCVD), ion beam sputtering deposition (IBSD) or a similar deposition process.
- MOCVD metal-organic chemical vapor deposition
- IBSD ion beam sputtering deposition
- FIG. 2C depicts a cross-sectional representation of the through-via vertical interconnect structure following formation of the optional adhesion promoting layer 22 and the first conductive layer 24 .
- the optional adhesion-promoting layer is typically used to promote adhesion between the subsequently formed conductive layer and the dielectric or diffusion barrier layers.
- the adhesion promoting layer may be disposed by a conventional sputtering technique or any other suitable semiconductor deposition technique may be used.
- the first conductive layer is disposed using a low temperature processing technique, such as MOCVD, IBSD or a similar semiconductor processing technique. In large diameter vias the first conductive layer forms the seed layer for subsequent processing of the second conductive layer which fills the via in its entirety.
- FIG. 2D depicts a cross-sectional diagram of the through-via vertical interconnect structure following formation of the second conductive layer 26 , planarization and an optional passivation layer 30 .
- the passivation layer helps to protect the circuitry and devices.
- the passivation layer may be fabricated from a suitable inorganic or organic material, such as silicon oxide, silicon nitride, silicon oxynitride, polyimide or benzocyclobutene (BCB).
- the passivation layer will typically have a thickness of about 0.5 micrometers to about 8.0 micrometers.
- the second conductive layer 26 After the second conductive layer 26 is deposited those areas of the first conductive layer 24 that do not underlie the second conductive layer are removed. Typically a chemical polish process is used to remove those portions of the first conductive layer. The polish process will expose back to either the dielectric layer 18 , the diffusion barrier layer 20 or, as shown in FIG. 2D, the adhesion promoting layer 22 . Subsequent to the removal/polish processing the optional passivation layer is disposed on the exposed areas of the dielectric layer 18 , the diffusion barrier layer 20 or, as shown in FIG. 2D, the adhesion promoting layer 22 . Typically, the passivation layer will comprise an organic dielectric material, such as benzocyclobutene (BCB) or an organic dielectric material, such as silicon oxynitride.
- BCB benzocyclobutene
- FIG. 3 is a flow diagram of the processing steps implemented to fabricate the through-via vertical interconnect device, in accordance with an embodiment of the present invention.
- the fabrication process provides for low temperature processing throughout, thus allowing for the vias to be formed after the fabrication of active circuitry on the substrate.
- one or more vias are formed in a substrate, typically an etch process is used to form vias having a high aspect ratio, such as deep reactive-ion etching or the like.
- an organic dielectric layer is disposed on the substrate and the interior surface of the one or more vias.
- the dielectric material will typically be disposed by a low temperature process that provides for the substrate to be held at a temperature below about 300 degrees Celsius while the deposition of the organic dielectric layer takes place.
- pyrolytic decomposition processing may be used whereby a monomer is vaporized, the vapor is heated to a cracking temperature and surface polymerization occurs on the substrate.
- a diffusion barrier layer is disposed on the dielectric layer.
- the diffusion barrier layer prevents the thermal diffusion of the conductive interconnect material.
- the diffusion barrier layer will typically be required if the resulting device is implemented in high temperature applications. In low temperature applications, the need to implement a diffusion barrier layer may be obviated.
- an adhesion promoting layer is disposed on either the dielectric layer or the diffusion layer.
- the adhesion-promoting layer may be required to promote adhesion between the dielectric layer or the diffusion barrier layer and the subsequently formed conductive layer.
- conductive layer materials, such as copper, gold and the like require an adhesion-promoting layer to sufficiently adhere to the underlying layer.
- the diffusion barrier layer and the adhesion-promoting layer will typically be disposed by a low temperature process that provides for the substrate to be held at a temperature below about 300 degrees Celsius.
- the first conductive interconnect layer is disposed on the dielectric layer (or intermediary layers, such as the diffusion barrier layer or the adhesion promoting layer).
- the first conductive interconnect layer will be disposed such that the conductive interconnect layer forms a through-via electrical interconnect between the first generally planar surface of the substrate and the second generally planar surface of the substrate.
- the first conductive layer will typically be formed by low temperature processing that provides for the substrate to be held at a temperature below about 300° C.
- the first conductive layer may be formed by MOCVD processing techniques or the like.
- lithographic patterning occurs whereby a photoresist is disposed, patterned and masked to define the via regions and the conductive contacts leading from the vias.
- a second conductive layer will be disposed to fill the via in its entirety.
- the second conductive layer will typically be formed by low temperature processing that provides for the substrate to be held at a temperature below about 300° C.
- the second conductive layer may be formed by conventional electroplating techniques or the like.
- FIG. 4 is a plan view diagram and FIG. 5 is a cross-sectional diagram of a heat sink structure that may be fabricated in unison with the through-via vertical interconnects, in accordance with an alternate embodiment of the present invention.
- the semiconductor substrate 10 has formed therein one or more heat sink apertures 40 .
- the heat sink aperture may be formed by creating an opening in the substrate using conventional chemical etching or mechanical machining methods. In one embodiment of the invention the aperture is formed by a through-wafer anisotropic chemical etching technique.
- the heat sink apertures will typically be formed during the same etch process that forms the through-wafer interconnect vias 42 , shown in FIG. 4 and FIG. 5.
- the heat sink structure 44 is designed in a multiple-branch configuration to give maximum surface area exposure to the thickness of the substrate. Additionally, the multiple-branch configuration allows for the heat sink structure to surround the one or more power-dissipating semiconductor devices 46 that are formed on the substrate.
- the apertures are filled with a thermally conductive material, such as a suitable metal material, preferably nickel, copper or the like.
- a thermally conductive material such as a suitable metal material, preferably nickel, copper or the like.
- Conventional chemical or mechanical deposition techniques are typically used to fill the heat sink apertures with the thermally conductive and form the heat sink structures 44 .
- a conventional electroplating technique may be used to fill the heat sink apertures.
- the filling of the apertures with thermally conductive material may be accomplished by the first and/or second conductive layer process steps used to form the conductive interconnect vias 42 .
- the heat sink structure will typically be thermally, and characteristically mechanically, connected to an external cooling device, such as a Peltier device or other thermoelectric modules (not shown in FIGS. 1 and 2).
- the cooling device serves to maintain the metal component of the heat sink at a temperature well below the operating temperature of the electronic device(s) formed on the substrate.
- heat will flow from the higher temperature regions, i.e., the power dissipating semiconductor devices 46 to the lower temperature regions, i.e., the through-via heat sink structure.
- the heat sink structure conducts the heat to the external cooling device.
- FIG. 6 is a cross-sectional representation of a multiple substrate stack incorporating through-via vertical interconnects and through substrate heat sinks, in accordance with an embodiment of the present invention.
- the illustrated embodiment comprises three stacked substrates 200 , 210 and 220 having active devices, through-via vertical interconnects that connect the active devices and through-via heat sink structures that dissipate the heat in the overall multi-substrate structure.
- the substrates may be similar materials (i.e., all silicon substrates), thus, providing for homogenous integration.
- the substrates may be dissimilar materials (i.e., silicon substrates and optical material substrates), thus providing for heterogeneous integration.
- the first substrate 200 comprises a first material and the second and third substrates 210 and 220 comprise a second material that is dissimilar from the first material.
- the first substrate 200 has a through-via vertical interconnect 230 that serves to electrically connect an active device 240 formed in the first substrate to an active device 250 formed in the second substrate 210 .
- the first substrate may have an active device in the form of a sensor or detector and this device is connected, through the via, to an analog device, such as an amplifier, in the second substrate.
- the second substrate 210 has a through-via vertical interconnect 260 that serves to connect an active device 270 formed in the second substrate to active device 280 formed in the third substrate 220 .
- the second substrate may have an analog device, such as an amplifier and this device is connected, through the via, to a processing or multiplexing device formed in the third substrate.
- the first substrate 200 has a through-via heat sink 290 that is generally aligned and connected to a heat sink structure 300 formed in the second substrate 210 .
- the generally aligned path provides for a continuous heat flow path to the underlying third substrate 220 , and an associated external cooling device (not shown in FIG. 6) and/or an area for heat release.
- the heat sink structures are generally aligned to provide for a continuous path, however, it is also possible to fabricate the heat sink structures or stack the wafers so as to provide for partially aligned or non-aligned configuration of the heat sinks.
- the multiple substrate stack embodiment will incorporate through-via heat sink structures that allow for heat flow to an external cooling device (not shown in FIG. 6).
- the external cooling device may be located on the third substrate 220 or in generally close proximity to the multiple substrate stack.
- the individual substrates of the stacked substrate configuration are fabricated individually and subsequently connected to one another by a conventional soldering, an adhesive bonding procedure or other suitable means of connecting adjoining substrates.
- an adhesive layer 310 is provided between the first and second substrates and the second and third substrates. The adhesive layer adheres to the backside of the substrates and the passivation layer 320 that is formed on the substrate above the active components, the through-wafer interconnects and the heat sinks.
- FIG. 7 depicts a cross-sectional representation of a multiple substrate stack incorporating through-via vertical interconnects, in accordance with an embodiment of the present invention.
- the illustrated embodiment comprises two stacked substrates 400 and 410 having active devices and through-via vertical interconnects that connect the active devices.
- the first substrate 400 has formed therein three through-via vertical interconnects 420 , 430 and 440 .
- the three through-via vertical interconnects provide electrical connection to optoelectronic devices 450 and 460 .
- the first substrate comprises gallium-arsenide (GaAs) and the optoelectronic devices are emissive devices such as vertical cavity surface emitting lasers (VCSELs) or light emitting diodes (LEDs).
- GaAs gallium-arsenide
- the optoelectronic devices are emissive devices such as vertical cavity surface emitting lasers (VCSELs) or light emitting diodes (LEDs).
- the VCSELs or LEDs may be disposed in an array formation on the surface of the first substrate.
- the second substrate 410 has active circuitry 470 and 480 disposed thereon as components in very large scale integration (VLSI) circuitry.
- the second substrate comprises silicon and the active circuitry devices are sensors.
- the first and second substrates in the embodiment shown in FIG. 7 are connected via solder bumps 490 .
- the solder bumps are in contact with the through via vertical interconnects 420 , 430 and 440 and contact pads 500 formed on the second substrate.
- Solder bump connections are shown by way of example only, other means of connecting the substrates, such as adhesive bonding or the like, may also be implemented without departing from the inventive concepts herein disclosed.
- the configuration shown in FIG. 7 provides for a scalable array of optoelectronic devices and eliminates wire bonds and surface leads, thereby, reducing interconnect inductance and capacitance.
- the present invention provides for an improved, through-via vertical interconnect, through-via heat sinks and the associated methods for fabricating the interconnects and heat sinks.
- an organic dielectric material such as a parylene compound
- low-temperature processing can be maintained throughout the fabrication process.
- the low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry.
- the through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs.
- the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter.
- the interconnects and heat sinks have heightened utility in multiple-substrate constructs. They provide a simple means of electrical connection between stacked substrates, thereby, eliminating unnecessary electrical bond wires and they provide the impetus for stacking substrates of dissimilar material types.
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Electromagnetism (AREA)
- Optics & Photonics (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
- The present application claims priority from U.S. Provisional Patent Application Serial No. 60/315,009, filed Aug. 24, 2001, the contents of which are incorporated by reference.
- The present invention relates to semiconductor devices, and more particularly to through-via vertical interconnects and through-via heat sinks and related methods for fabricating the same.
- At the advent of the semiconductor industry, substrate-to-substrate electrical and electro-optic interconnections were limited to connecting devices by wire bond techniques. This meant that in most instances, the substrates existed in a linear, two-dimensional orientation with wires connecting the desired devices. The advent of through-via interconnects (i.e., connections made from one side of the substrate through to the opposite side of the substrate) has led to stacked configurations of substrates that exist in a three-dimensional relationship. These stacked configurations provide for a more compact packaging design and allow for fabrication of high-density devices, such as sensor or transducer arrays.
- Additionally, through-via interconnects provide for interconnections between different series of devices. For example, analog devices, such as transistors or the like may be fabricated on one substrate while digital devices, such as data processing components may be fabricated on a second substrate. Cost constraints and fabrication concerns make it impractical to combine the analog and digital devices on a single substrate. Thus, through-via interconnects provide a means for connecting dissimilar devices in a dense, stacked packaging environment.
- Typically, through-via interconnects are fabricated using some level of high temperature processing. For instance, dielectric layers in the form of oxides are typically formed by a thermal oxidation process that occurs at temperatures in excess of 1000° C. Such high temperature processing limits the formation of the through-via interconnects to a front-end process (i.e., before devices are formed on the substrate). Most devices subsequently formed on the substrate would be negatively impacted from a functionality and reliability perspective if they were to be subject to such high temperature processing at the back-end of the overall fabrication process.
- Back-end processing of the through-via interconnects is desirable due to the manner in which substrate processing and device fabrication are typically undertaken. In many applications, devices are formed on a thick substrate and then a significant portion of the backside of the substrate is etched away as a means of thinning the substrate post device formation. Forming the through-via interconnects prior to the substrate etch processing would be impractical because the aspect ratios of the vias would be so high that conformal deposition within the via walls could not be achieved. Thus, the need exists in many applications to form the vias at the back-end of the process, after the devices have already been formed on the substrate and backside etching processes have ensued.
- To date, low temperature processing of through-via interconnects has been limited to such fabrication techniques as plasma-enhanced chemical vapor deposition (PECVD). However, PECVD and other known low temperature processes do not provide for conformal deposition within the interior walls of the through-via. In general, these processes are not able to provide conformal deposition to vias having high aspect ratios of 3:1, 4:1 or 5:1 (height of via to diameter of via). Conformal coverage of the walls of the via is required for further fabrication of the interconnect and insures proper electrical or optical signal transmission through the resulting interconnect.
- Therefore, the need exists to develop a through-via interconnect that provides for low-temperature processing and conformal deposition within high aspect ratios. The low-temperature processing will allow the through-via interconnects to be formed at the back-end of the overall semiconductor device processing flow.
- The present invention provides for improved through-via vertical interconnects and through-via heat sinks. The devices benefit from an organic dielectric layer that allows for low-temperature deposition processing. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 10:1, substrate thickness to interconnect diameter.
- The invention is embodied in a through-via vertical interconnect device. The device comprises a substrate having at least one via formed therein, an organic dielectric layer disposed on the surface of the at least one via, and a first conductive layer disposed on the dielectric layer that forms a through-via vertical interconnect between a first generally planar surface of the substrate and a second generally planar surface of the substrate. In one preferred embodiment, the organic dielectric material comprises a parylene material such as Parylene C, N or D.
- In many embodiments of the device, the dielectric layer and first interconnect layer are disposed while the substrate is held at a temperature of less than about 300 degrees Celsius. This low temperature processing allows for the interconnects to be formed at the back-end of the manufacturing process, after active devices and electrical circuitry have been formed on the substrate.
- Additionally, the device may comprise a diffusion barrier layer disposed on the surface of the at least one via between the dielectric layer and the first conductive layer and an adhesion-promoting device disposed between the first conductive layer and the layer adjacent to the first conductive layer. In most embodiments the through-via vertical interconnect will include a second conductive layer disposed on the first conductive layer, the second conductive layer serving the purpose of generally filling the at least one via.
- In an alternate embodiment of the invention, a method for fabricating through-via vertical interconnects comprises the steps of forming at least one via in a substrate, disposing an organic dielectric layer on the surface of the at least one via and disposing a first conductive interconnect layer on the dielectric layer such that the conductive interconnect layer forms a through-via vertical interconnect between a first generally planar surface of the substrate and a second generally planar surface of the substrate. Additionally, the steps of disposing the organic dielectric and the first conductive layer are accomplished while maintaining the substrate at a temperature of below about 300. The low temperature process is typically maintained by disposing the dielectric layer by vapor phase deposition, such as pyrolytic decomposition coupled with room temperature polymerization and disposing the first conductive interconnect layer by metal-organic chemical vapor deposition (MOCVD) processing. The etch process will typically entail a deep reactive ion etch procedure that provides for vias having a high aspect ratio.
- Additionally, the method for fabricating a through-via vertical interconnect may entail additional processing steps. These additional steps include disposing, between the dielectric layer and the first conductive interconnect layer, a diffusion barrier layer on the via surface of the at least one via. The diffusion barrier layer prevents diffusion of metal atoms in high temperature applications. The additional step of disposing an adhesion-promoting layer may be necessary to promote adhesion between the conductive layer and adjacent layers. In most applications it will be necessary to dispose a second conductive interconnect layer on the first conductive interconnect layer such that the second conductive interconnect layer generally fills the at least one via. In these applications the first conductive layer serves as a seed layer for the subsequently formed second conductive layer.
- In an alternate embodiment of the invention, a method for semiconductor manufacturing comprises the steps of fabricating active devices and/or electrical circuitry on the surface of a semiconductor substrate. Subsequent to the formation of the active devices and/or electrical circuitry, through-via vertical interconnects are formed in the substrate. Low temperature processing of the through-via vertical interconnects provides for the interconnects to be fabricated after the other structures, circuits and devices have been fabricated on the substrate.
- The invention is also embodied in a multi-substrate semiconductor device. The multi-layered semiconductor device will include a stack of two or more substrates. One or more of the substrates in the stack will include one or more through-via vertical interconnects. The one or more through-via vertical interconnects comprising vias formed in the substrate, an organic dielectric layer and a first conductive layer. The through-via vertical interconnects are typically defined by being fabricated while the substrate is held at temperatures below about 300° C. The through-via interconnects serve to electrically connect devices and circuits on one substrate to devices and circuits on another substrate in the stack. The substrates in the stack may be formed all of the same material, e.g., silicon, or the substrates may be formed of dissimilar materials to accommodate electrical and electro-optical connections. Additionally, the multi-substrate device may comprise through-via heat sink structures that provide for a continuous path for heat flow through the entirety of the multiple-substrate semiconductor device.
- Thus, the present invention provides for improved through-via vertical interconnects and through-via heat sinks. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of up to about 10:1, substrate thickness to interconnect diameter.
- FIG. 1 is a cross-sectional view of through-via vertical interconnects in a substrate, in accordance with an embodiment of the present invention.
- FIGS.2A-2D are cross-sectional views of various fabrication stages in the processing of through-via vertical interconnects, in accordance with an embodiment of the present invention.
- FIG. 3 is a flow diagram of a process for fabricating through-via vertical interconnects, in accordance with an embodiment of the present invention.
- FIG. 4 is a top view perspective of through-via vertical interconnects and through-via heat sink structures, in accordance with an embodiment of the present invention.
- FIG. 5 is a cross-sectional diagram of through-via heat sink and through-via vertical interconnect, in accordance with an alternate embodiment of the present invention.
- FIG. 6 is a cross-sectional diagram of a multiple-substrate semiconductor device implementing through-via vertical interconnects, through-via heat sinks and adhesive bonding, in accordance with an embodiment of the present invention.
- FIG. 7 is a cross-sectional diagram of a multiple-substrate semiconductor device implementing through-via vertical interconnects and solder bumping, in accordance with an embodiment of the present invention.
- The present invention now will be described more fully hereinafter with reference to the accompanying drawings, in which preferred embodiments of the invention are shown. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. Like numbers refer to like elements throughout.
- FIG. 1 is a cross sectional diagram of a through-via vertical interconnect (TVI) in accordance with an embodiment of the present invention. The through-via
vertical interconnect 10 includes asubstrate 12 having one ormore vias 14 formed therein. The substrate will typically comprise silicon although any other suitable substrate material may also be used to form the substrate. Examples of other suitable substrate materials include gallium arsenide, ceramic materials, glass materials and the like. The invention provides for vias that can be formed with high aspect ratios, typically in the range of about 4:1 to about 10:1; substrate thickness to via diameter ratio. For example, a 500 micrometer thick substrate will be able to accommodate vias having diameters as small as 50 micrometers. Such high aspect ratios are made possible by the capability of the invention to provide conformal layering of materials within theinterior wall 16 of thevias 14. - The surface of the
substrate 12 and theinterior wall 16 of the one ormore vias 14 have disposed thereon anorganic dielectric layer 18. In one embodiment of the invention the organic dielectric material will comprise a parylene material, such as Parylene C, N or D. In alternate embodiments, the dielectric layer may be formed of oxides, nitrides or other compounds if a low-temperature (i.e., below 300° C.), conformal deposition technique is implemented. The dielectric layer provides electrical isolation between the substrate and the conductive elements of the one or more though-via vertical interconnects. Typically, the organic dielectric material will be formed by low temperature processing; i.e., processing below about 300 degrees Celsius (° C.), preferably about 200° C. For example, a vapor phase deposition technique, such as pyrolytic decomposition processing coupled with vacuum polymerization, may be used to form the dielectric layer at a temperature of about 200° C. The dielectric layer will typically have a thickness in the range of about 500 angstroms to about 5000 angstroms, preferably about 2000 angstroms. - The through-via
vertical interconnect 10 structure may also include optionaldiffusion barrier layer 20. The diffusion barrier layer is implemented to prevent thermal diffusion of the subsequently formed conductive interconnect material. A diffusion barrier layer will typically be implemented in the through-via vertical interconnect structure if the resulting device is used in a high-temperature application, e.g., a sensor in an automotive application. In low temperature applications it may not be necessary to construct the interconnect of the present invention with a diffusion barrier layer. The diffusion barrier layer is typically disposed using conventional low-temperature CVD or sputtering techniques. The diffusion barrier layer may be formed of a refractory-metal nitride material, such as titanium nitride (TiN). It is also possible to implement other nitride materials, such as silicon nitride (SiNx), tantalum nitride (TaN), hafnium nitride (HfN) or the like. The diffusion barrier layer will typically have a thickness in the range of about 500 angstroms to about 5000 angstroms, preferably about 2000 angstroms. - It may also be advantageous to form an optional adhesion-promoting
layer 22 between thedielectric layer 18 and the subsequently formed conductive interconnect materials. As is known by those of ordinary skill in the art, many conductive materials such as copper and gold have poor adhesion characteristics and require an adhesion-promoter to insure proper adhesion to adjacent layers in the construct. In those applications that require adiffusion barrier layer 20, the diffusion barrier layer may provide adequate adhesion-promoting characteristics. However, in applications which do not require a diffusion barrier layer or applications in which the diffusion barrier layer does not provide adequate adhesion-promoting characteristics it may be necessary to provide for a separate adhesion-promoting layer. The adhesion-promoting layer may be formed of TiN or any other suitable material. The adhesion promoting layer will typically have a thickness in the range of about 50 angstroms to about 200 angstroms, preferably about 100 angstroms. The adhesion-promoting layer can be formed by sputtering or any other suitable low temperature process. - The through-via
vertical interconnect 10 will include a firstconductive layer 24 disposed on either theorganic dielectric layer 18 or, if required, thediffusion barrier layer 20 or the adhesion-promotinglayer 22. For vias having a large diameter the first conductive layer may act as a seed layer for a subsequently formed secondconductive layer 26 that fills in the via in its entirety. The first conductive layer is typically formed by a metal-organic chemical vapor deposition (MOCVD) technique or any other suitable low-temperature process. The first conductive layer may comprise copper, gold or any other suitable conductive material. The first conductive layer will typically have a thickness in the range of about 0.5 micrometers to 5 micrometers, preferably about 1 micrometer. - In large via structures it may be necessary to fill the vias in their entirety with an optional second
conductive layer 26. The processing of the second conductive layer will typically occur after a masking operation has defined theareas 28 on the surface of thesubstrate 12 that will form the conductive interconnect contacts leading to active devices (not shown in FIG. 1). The second conductive layer is typically formed by an electrochemical deposition technique or any other suitable low-temperature process. The second conductive layer may comprise copper, gold or any other suitable conductive material and will typically be equivalent to the material used to form the first conductive layer. The thickness of the second conductive layer will generally be dictated by the diameter of the via that requires filling. - FIGS.2A-2D are cross-sectional diagrams of various stages in the fabrication process of a through-via vertical interconnect device, in accordance with a method of manufacturing embodiment of the present invention. The fabrication process implements low-temperature processing that allows for through-via vertical interconnects to be formed on the substrate after active devices and circuitry have been fabricated.
- FIG. 2A depicts a cross-sectional representation of a
substrate 12 having one ormore vias 14 formed therein. Typically, photolithographic patterning is used to define and pattern the regions on the substrate where the vias will be formed. Once the patterning defines the regions, an etch process, such as deep reactive-ion etching, is implemented to create high-aspect through substrate vias. - FIG. 2B depicts a cross-sectional representation of the through-via vertical interconnect structure following formation of the
dielectric layer 18 and the optionaldiffusion barrier layer 20. The dielectric layer is disposed by low temperature processing; i.e., processing below about 300 degrees Celsius (° C.), preferably about 200° C. For example, a vapor phase deposition technique, such as pyrolytic decomposition coupled with room temperature polymerization may be used to form the dielectric layer at a temperature of about 200° C. Pyrolytic decomposition involves vaporizing a monomer, heating the vapor to a cracking temperature to break bonds and condensing the products on the surface of the substrate to form a polymer (i.e., surface polymerization). While the vapor in the process exceeds the low temperature threshold of about 300° C., the substrate construct is kept at a low temperature (i.e., typically room temperature) to facilitate the surface polymerization process. The diffusion barrier layer is disposed by a low temperature processing technique, such as metal-organic chemical vapor deposition (MOCVD), ion beam sputtering deposition (IBSD) or a similar deposition process. - FIG. 2C depicts a cross-sectional representation of the through-via vertical interconnect structure following formation of the optional
adhesion promoting layer 22 and the firstconductive layer 24. The optional adhesion-promoting layer is typically used to promote adhesion between the subsequently formed conductive layer and the dielectric or diffusion barrier layers. The adhesion promoting layer may be disposed by a conventional sputtering technique or any other suitable semiconductor deposition technique may be used. The first conductive layer is disposed using a low temperature processing technique, such as MOCVD, IBSD or a similar semiconductor processing technique. In large diameter vias the first conductive layer forms the seed layer for subsequent processing of the second conductive layer which fills the via in its entirety. - FIG. 2D depicts a cross-sectional diagram of the through-via vertical interconnect structure following formation of the second
conductive layer 26, planarization and anoptional passivation layer 30. The passivation layer helps to protect the circuitry and devices. The passivation layer may be fabricated from a suitable inorganic or organic material, such as silicon oxide, silicon nitride, silicon oxynitride, polyimide or benzocyclobutene (BCB). The passivation layer will typically have a thickness of about 0.5 micrometers to about 8.0 micrometers. - After the second
conductive layer 26 is deposited those areas of the firstconductive layer 24 that do not underlie the second conductive layer are removed. Typically a chemical polish process is used to remove those portions of the first conductive layer. The polish process will expose back to either thedielectric layer 18, thediffusion barrier layer 20 or, as shown in FIG. 2D, theadhesion promoting layer 22. Subsequent to the removal/polish processing the optional passivation layer is disposed on the exposed areas of thedielectric layer 18, thediffusion barrier layer 20 or, as shown in FIG. 2D, theadhesion promoting layer 22. Typically, the passivation layer will comprise an organic dielectric material, such as benzocyclobutene (BCB) or an organic dielectric material, such as silicon oxynitride. - FIG. 3 is a flow diagram of the processing steps implemented to fabricate the through-via vertical interconnect device, in accordance with an embodiment of the present invention. The fabrication process provides for low temperature processing throughout, thus allowing for the vias to be formed after the fabrication of active circuitry on the substrate. At
step 100 one or more vias are formed in a substrate, typically an etch process is used to form vias having a high aspect ratio, such as deep reactive-ion etching or the like. - At
step 110, an organic dielectric layer is disposed on the substrate and the interior surface of the one or more vias. The dielectric material will typically be disposed by a low temperature process that provides for the substrate to be held at a temperature below about 300 degrees Celsius while the deposition of the organic dielectric layer takes place. For example, pyrolytic decomposition processing may be used whereby a monomer is vaporized, the vapor is heated to a cracking temperature and surface polymerization occurs on the substrate. - At
optional step 120, a diffusion barrier layer is disposed on the dielectric layer. The diffusion barrier layer prevents the thermal diffusion of the conductive interconnect material. The diffusion barrier layer will typically be required if the resulting device is implemented in high temperature applications. In low temperature applications, the need to implement a diffusion barrier layer may be obviated. Atoptional step 130, an adhesion promoting layer is disposed on either the dielectric layer or the diffusion layer. The adhesion-promoting layer may be required to promote adhesion between the dielectric layer or the diffusion barrier layer and the subsequently formed conductive layer. Typically, conductive layer materials, such as copper, gold and the like require an adhesion-promoting layer to sufficiently adhere to the underlying layer. The diffusion barrier layer and the adhesion-promoting layer will typically be disposed by a low temperature process that provides for the substrate to be held at a temperature below about 300 degrees Celsius. - At
step 140, the first conductive interconnect layer is disposed on the dielectric layer (or intermediary layers, such as the diffusion barrier layer or the adhesion promoting layer). The first conductive interconnect layer will be disposed such that the conductive interconnect layer forms a through-via electrical interconnect between the first generally planar surface of the substrate and the second generally planar surface of the substrate. The first conductive layer will typically be formed by low temperature processing that provides for the substrate to be held at a temperature below about 300° C. For example the first conductive layer may be formed by MOCVD processing techniques or the like. - At
optional steps - FIG. 4 is a plan view diagram and FIG. 5 is a cross-sectional diagram of a heat sink structure that may be fabricated in unison with the through-via vertical interconnects, in accordance with an alternate embodiment of the present invention. The
semiconductor substrate 10 has formed therein one or moreheat sink apertures 40. The heat sink aperture may be formed by creating an opening in the substrate using conventional chemical etching or mechanical machining methods. In one embodiment of the invention the aperture is formed by a through-wafer anisotropic chemical etching technique. The heat sink apertures will typically be formed during the same etch process that forms the through-wafer interconnect vias 42, shown in FIG. 4 and FIG. 5. - In the embodiment shown in FIG. 4, the
heat sink structure 44 is designed in a multiple-branch configuration to give maximum surface area exposure to the thickness of the substrate. Additionally, the multiple-branch configuration allows for the heat sink structure to surround the one or more power-dissipatingsemiconductor devices 46 that are formed on the substrate. - Subsequent to the formation of the
heat sink apertures 40 in thesubstrate 10, the apertures are filled with a thermally conductive material, such as a suitable metal material, preferably nickel, copper or the like. Conventional chemical or mechanical deposition techniques are typically used to fill the heat sink apertures with the thermally conductive and form theheat sink structures 44. For example, a conventional electroplating technique may be used to fill the heat sink apertures. In this regard, the filling of the apertures with thermally conductive material may be accomplished by the first and/or second conductive layer process steps used to form theconductive interconnect vias 42. - The heat sink structure will typically be thermally, and characteristically mechanically, connected to an external cooling device, such as a Peltier device or other thermoelectric modules (not shown in FIGS. 1 and 2). The cooling device serves to maintain the metal component of the heat sink at a temperature well below the operating temperature of the electronic device(s) formed on the substrate. By natural conduction, heat will flow from the higher temperature regions, i.e., the power dissipating
semiconductor devices 46 to the lower temperature regions, i.e., the through-via heat sink structure. In turn, the heat sink structure conducts the heat to the external cooling device. - FIG. 6 is a cross-sectional representation of a multiple substrate stack incorporating through-via vertical interconnects and through substrate heat sinks, in accordance with an embodiment of the present invention. The illustrated embodiment comprises three stacked
substrates first substrate 200 comprises a first material and the second andthird substrates - In the illustrated embodiment the
first substrate 200 has a through-viavertical interconnect 230 that serves to electrically connect anactive device 240 formed in the first substrate to anactive device 250 formed in thesecond substrate 210. For example, the first substrate may have an active device in the form of a sensor or detector and this device is connected, through the via, to an analog device, such as an amplifier, in the second substrate. Thesecond substrate 210 has a through-viavertical interconnect 260 that serves to connect anactive device 270 formed in the second substrate toactive device 280 formed in thethird substrate 220. For example, the second substrate may have an analog device, such as an amplifier and this device is connected, through the via, to a processing or multiplexing device formed in the third substrate. - Additionally, the
first substrate 200 has a through-viaheat sink 290 that is generally aligned and connected to aheat sink structure 300 formed in thesecond substrate 210. The generally aligned path provides for a continuous heat flow path to the underlyingthird substrate 220, and an associated external cooling device (not shown in FIG. 6) and/or an area for heat release. In the embodiment shown the heat sink structures are generally aligned to provide for a continuous path, however, it is also possible to fabricate the heat sink structures or stack the wafers so as to provide for partially aligned or non-aligned configuration of the heat sinks. Typically, the multiple substrate stack embodiment will incorporate through-via heat sink structures that allow for heat flow to an external cooling device (not shown in FIG. 6). The external cooling device may be located on thethird substrate 220 or in generally close proximity to the multiple substrate stack. - The individual substrates of the stacked substrate configuration are fabricated individually and subsequently connected to one another by a conventional soldering, an adhesive bonding procedure or other suitable means of connecting adjoining substrates. In the embodiment shown in FIG. 6, an
adhesive layer 310 is provided between the first and second substrates and the second and third substrates. The adhesive layer adheres to the backside of the substrates and thepassivation layer 320 that is formed on the substrate above the active components, the through-wafer interconnects and the heat sinks. - FIG. 7 depicts a cross-sectional representation of a multiple substrate stack incorporating through-via vertical interconnects, in accordance with an embodiment of the present invention. The illustrated embodiment comprises two
stacked substrates first substrate 400 has formed therein three through-viavertical interconnects optoelectronic devices second substrate 410 hasactive circuitry vertical interconnects contact pads 500 formed on the second substrate. Solder bump connections are shown by way of example only, other means of connecting the substrates, such as adhesive bonding or the like, may also be implemented without departing from the inventive concepts herein disclosed. The configuration shown in FIG. 7 provides for a scalable array of optoelectronic devices and eliminates wire bonds and surface leads, thereby, reducing interconnect inductance and capacitance. - Accordingly, the present invention provides for an improved, through-via vertical interconnect, through-via heat sinks and the associated methods for fabricating the interconnects and heat sinks. By incorporating an organic dielectric material, such as a parylene compound, low-temperature processing can be maintained throughout the fabrication process. The low-temperature processing used to form the through-via interconnects and heat sinks allows for the formation of the interconnects and heat sinks at any point in the fabrication of the semiconductor device, including post-formation of active devices and associated circuitry. The through-via vertical interconnects of the present invention are fabricated so as to insure conformal thickness of the various layers that form the interconnect constructs. As such, the interconnects can be formed with a high aspect ratio, in the range of about 4:1 to about 10:1, substrate thickness to interconnect diameter. The interconnects and heat sinks have heightened utility in multiple-substrate constructs. They provide a simple means of electrical connection between stacked substrates, thereby, eliminating unnecessary electrical bond wires and they provide the impetus for stacking substrates of dissimilar material types.
- Many modifications and other embodiments of the invention will come to mind to one skilled in the art to which this invention pertains having the benefit of the teachings presented in the foregoing descriptions and the associated drawings. Therefore, it is to be understood that the invention is not to be limited to the specific embodiments disclosed and that modifications and other embodiments are intended to be included within the scope of the appended claims. Although specific terms are employed herein, they are used in a generic and descriptive sense only and not for purposes of limitation.
Claims (27)
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/227,089 US20030038344A1 (en) | 2001-08-24 | 2002-08-23 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
US10/834,224 US20040201095A1 (en) | 2001-08-24 | 2004-04-29 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US31500901P | 2001-08-24 | 2001-08-24 | |
US10/227,089 US20030038344A1 (en) | 2001-08-24 | 2002-08-23 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
Related Child Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/834,224 Division US20040201095A1 (en) | 2001-08-24 | 2004-04-29 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
Publications (1)
Publication Number | Publication Date |
---|---|
US20030038344A1 true US20030038344A1 (en) | 2003-02-27 |
Family
ID=23222469
Family Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/227,089 Abandoned US20030038344A1 (en) | 2001-08-24 | 2002-08-23 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
US10/834,224 Abandoned US20040201095A1 (en) | 2001-08-24 | 2004-04-29 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
Family Applications After (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US10/834,224 Abandoned US20040201095A1 (en) | 2001-08-24 | 2004-04-29 | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods |
Country Status (6)
Country | Link |
---|---|
US (2) | US20030038344A1 (en) |
EP (1) | EP1419526A2 (en) |
JP (1) | JP2005501413A (en) |
KR (1) | KR20040060919A (en) |
AU (1) | AU2002323388A1 (en) |
WO (1) | WO2003019651A2 (en) |
Cited By (36)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030067074A1 (en) * | 2001-10-10 | 2003-04-10 | Kinsman Larry D. | Circuit boards containing vias and methods for producing same |
US20040089948A1 (en) * | 2002-11-07 | 2004-05-13 | Yu-Ting Cheng | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
US20050218497A1 (en) * | 2004-03-30 | 2005-10-06 | Nec Electronics Corporation | Through electrode, spacer provided with the through electrode, and method of manufacturing the same |
US20070063316A1 (en) * | 2005-09-22 | 2007-03-22 | International Rectifier Corporation | Flip chip semiconductor device and process of its manufacture |
US20070085117A1 (en) * | 2005-10-11 | 2007-04-19 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20070093066A1 (en) * | 2005-10-24 | 2007-04-26 | Rajashree Baskaran | Stacked wafer or die packaging with enhanced thermal and device performance |
EP1830615A1 (en) * | 2004-11-24 | 2007-09-05 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and method for manufacturing same |
EP1861857A2 (en) * | 2004-12-07 | 2007-12-05 | M-Flex Multi-Fineline Electronix, Inc. | Miniature circuitry and inductive components and methods for manufacturing same |
US20080060693A1 (en) * | 2004-09-30 | 2008-03-13 | Basf Aktiengesellschaft | Thermoelectric Material Contact |
US20090218671A1 (en) * | 2008-03-03 | 2009-09-03 | Kimihito Kuwabara | Semiconductor device and method of fabricating the same |
US20100012934A1 (en) * | 2008-07-17 | 2010-01-21 | Oh-Jin Jung | Semiconductor chip and semiconductor chip stacked package |
WO2010083922A1 (en) * | 2009-01-21 | 2010-07-29 | Austriamicrosystems Ag | Semiconductor component having interlayer connection and method for the production thereof |
US20100193229A1 (en) * | 2009-02-05 | 2010-08-05 | Xilinx, Inc. | Barrier layer to prevent conductive anodic filaments |
WO2011044393A1 (en) * | 2009-10-07 | 2011-04-14 | Tessera North America, Inc. | Wafer-scale emitter package including thermal vias |
EP2315243A1 (en) * | 2009-10-23 | 2011-04-27 | STmicroelectronics SA | Interposer between integrated circuits |
US20110210357A1 (en) * | 2008-06-06 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Optoelectronic Component and Method for the Production Thereof |
US20110227860A1 (en) * | 2010-03-22 | 2011-09-22 | Park Ho Joon | Resistive touch screen |
US20120132460A1 (en) * | 2009-06-17 | 2012-05-31 | Hamamatsu Photonics K.K. | Laminated wiring board |
US8324511B1 (en) * | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US8624996B2 (en) | 2009-12-31 | 2014-01-07 | DigitalOptics Corporation Europe Limited | Auto white balance algorithm using RGB product measure |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US20150257282A1 (en) * | 2014-03-04 | 2015-09-10 | Qualcomm Incorporated | Substrate with conductive vias |
US20160141257A1 (en) * | 2010-03-03 | 2016-05-19 | Georgia Tech Research Corporation | Through-package-via (tpv) structures on inorganic interposer and methods for fabricating same |
US9812629B2 (en) * | 2012-07-13 | 2017-11-07 | Industrial Technology Research Institute | Thermoelectric conversion structure and its use in heat dissipation device |
WO2019234323A1 (en) * | 2018-06-08 | 2019-12-12 | Commissariat a l'énergie atomique et aux énergies alternatives | Photonic chip with buried laser source |
US10764988B2 (en) * | 2018-05-31 | 2020-09-01 | Panasonic Intellectual Property Management Co., Ltd. | Imaging device |
US11164827B2 (en) * | 2016-12-30 | 2021-11-02 | Intel Corporation | Substrate with gradiated dielectric for reducing impedance mismatch |
US11201122B2 (en) | 2018-09-27 | 2021-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating semiconductor device with reduced warpage and better trench filling performance |
US20220299607A1 (en) * | 2021-03-16 | 2022-09-22 | Yuuki OKA | Light source module, distance-measuring apparatus, and mobile object |
US20230099959A1 (en) * | 2020-06-18 | 2023-03-30 | Fudan University | Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof |
US20230397331A1 (en) * | 2022-06-02 | 2023-12-07 | International Business Machines Corporation | Method to manufacture conductive anodic filament-resistant microvias |
Families Citing this family (19)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100584965B1 (en) * | 2003-02-24 | 2006-05-29 | 삼성전기주식회사 | Package Substrate and Manufacturing Method Thereof |
US6943106B1 (en) * | 2004-02-20 | 2005-09-13 | Micron Technology, Inc. | Methods of fabricating interconnects for semiconductor components including plating solder-wetting material and solder filling |
DE102004040505A1 (en) * | 2004-08-20 | 2006-03-02 | Infineon Technologies Ag | Semiconductor circuit arrangement and method for its production |
US7279407B2 (en) | 2004-09-02 | 2007-10-09 | Micron Technology, Inc. | Selective nickel plating of aluminum, copper, and tungsten structures |
US7892972B2 (en) * | 2006-02-03 | 2011-02-22 | Micron Technology, Inc. | Methods for fabricating and filling conductive vias and conductive vias so formed |
US7560371B2 (en) | 2006-08-29 | 2009-07-14 | Micron Technology, Inc. | Methods for selectively filling apertures in a substrate to form conductive vias with a liquid using a vacuum |
KR100896883B1 (en) * | 2007-08-16 | 2009-05-14 | 주식회사 동부하이텍 | Semiconductor chip, manufacturing method thereof and laminated package having same |
WO2009111874A1 (en) * | 2008-03-11 | 2009-09-17 | The Royal Institution For The Advancement Of Learning/ Mcgiil University | Low-temperature wafer level processing for mems devices |
KR101002680B1 (en) | 2008-10-21 | 2010-12-21 | 삼성전기주식회사 | Semiconductor package and manufacturing method thereof |
US8304863B2 (en) | 2010-02-09 | 2012-11-06 | International Business Machines Corporation | Electromigration immune through-substrate vias |
JP5209075B2 (en) | 2010-05-21 | 2013-06-12 | 有限会社 ナプラ | Electronic device and manufacturing method thereof |
TW201200853A (en) * | 2010-06-18 | 2012-01-01 | Ind Tech Res Inst | Measuring apparatus |
WO2012061304A1 (en) * | 2010-11-02 | 2012-05-10 | Georgia Tech Research Corporation | Ultra-thin interposer assemblies with through vias |
US9704793B2 (en) | 2011-01-04 | 2017-07-11 | Napra Co., Ltd. | Substrate for electronic device and electronic device |
KR102295103B1 (en) * | 2015-02-24 | 2021-08-31 | 삼성전기주식회사 | Circuit board and assembly thereof |
CN107934907A (en) * | 2017-12-12 | 2018-04-20 | 成都海威华芯科技有限公司 | A kind of depth Si through-hole structures |
US10629512B2 (en) * | 2018-06-29 | 2020-04-21 | Xilinx, Inc. | Integrated circuit die with in-chip heat sink |
US20230058897A1 (en) * | 2021-08-17 | 2023-02-23 | International Business Machines Corporation | Thermal conduction layer |
WO2024195520A1 (en) * | 2023-03-22 | 2024-09-26 | 味の素株式会社 | Interposer, method for manufacturing same, semiconductor package substrate, and method for manufacturing same |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037822A (en) * | 1997-09-30 | 2000-03-14 | Intel Corporation | Method and apparatus for distributing a clock on the silicon backside of an integrated circuit |
US6180518B1 (en) * | 1999-10-29 | 2001-01-30 | Lucent Technologies Inc. | Method for forming vias in a low dielectric constant material |
US6278181B1 (en) * | 1999-06-28 | 2001-08-21 | Advanced Micro Devices, Inc. | Stacked multi-chip modules using C4 interconnect technology having improved thermal management |
US6469385B1 (en) * | 2001-06-04 | 2002-10-22 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
US20020155700A1 (en) * | 2001-04-24 | 2002-10-24 | Tai-Ju Chen | Method of forming a damascene structure |
US20020158337A1 (en) * | 2000-02-08 | 2002-10-31 | Babich Katherina E. | Multilayer interconnect structure containing air gaps and method for making |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2767223B1 (en) * | 1997-08-06 | 1999-09-17 | Commissariat Energie Atomique | INTERCONNECTION METHOD THROUGH SEMICONDUCTOR MATERIAL, AND DEVICE OBTAINED |
JP3199006B2 (en) * | 1997-11-18 | 2001-08-13 | 日本電気株式会社 | Method of forming interlayer insulating film and insulating film forming apparatus |
US6404061B1 (en) * | 1999-02-26 | 2002-06-11 | Rohm Co., Ltd. | Semiconductor device and semiconductor chip |
US6482733B2 (en) * | 2000-05-15 | 2002-11-19 | Asm Microchemistry Oy | Protective layers prior to alternating layer deposition |
-
2002
- 2002-08-23 AU AU2002323388A patent/AU2002323388A1/en not_active Abandoned
- 2002-08-23 US US10/227,089 patent/US20030038344A1/en not_active Abandoned
- 2002-08-23 WO PCT/US2002/027013 patent/WO2003019651A2/en not_active Application Discontinuation
- 2002-08-23 JP JP2003523001A patent/JP2005501413A/en active Pending
- 2002-08-23 KR KR10-2004-7002596A patent/KR20040060919A/en not_active Withdrawn
- 2002-08-23 EP EP02757368A patent/EP1419526A2/en not_active Withdrawn
-
2004
- 2004-04-29 US US10/834,224 patent/US20040201095A1/en not_active Abandoned
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6037822A (en) * | 1997-09-30 | 2000-03-14 | Intel Corporation | Method and apparatus for distributing a clock on the silicon backside of an integrated circuit |
US6278181B1 (en) * | 1999-06-28 | 2001-08-21 | Advanced Micro Devices, Inc. | Stacked multi-chip modules using C4 interconnect technology having improved thermal management |
US6180518B1 (en) * | 1999-10-29 | 2001-01-30 | Lucent Technologies Inc. | Method for forming vias in a low dielectric constant material |
US20020158337A1 (en) * | 2000-02-08 | 2002-10-31 | Babich Katherina E. | Multilayer interconnect structure containing air gaps and method for making |
US20020155700A1 (en) * | 2001-04-24 | 2002-10-24 | Tai-Ju Chen | Method of forming a damascene structure |
US6469385B1 (en) * | 2001-06-04 | 2002-10-22 | Advanced Micro Devices, Inc. | Integrated circuit with dielectric diffusion barrier layer formed between interconnects and interlayer dielectric layers |
Cited By (89)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20030067074A1 (en) * | 2001-10-10 | 2003-04-10 | Kinsman Larry D. | Circuit boards containing vias and methods for producing same |
US6774486B2 (en) * | 2001-10-10 | 2004-08-10 | Micron Technology, Inc. | Circuit boards containing vias and methods for producing same |
US6797616B2 (en) | 2001-10-10 | 2004-09-28 | Micron Technology, Inc. | Circuit boards containing vias and methods for producing same |
US20040089948A1 (en) * | 2002-11-07 | 2004-05-13 | Yu-Ting Cheng | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
US20090302454A1 (en) * | 2002-11-07 | 2009-12-10 | Cheng Yu-Ting | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
US7880305B2 (en) * | 2002-11-07 | 2011-02-01 | International Business Machines Corporation | Technology for fabrication of packaging interface substrate wafers with fully metallized vias through the substrate wafer |
US7994048B2 (en) | 2004-03-30 | 2011-08-09 | Renesas Electronics Corporation | Method of manufacturing a through electrode |
US20070243706A1 (en) * | 2004-03-30 | 2007-10-18 | Nec Electronics Corporation | Method of manufacturing a through electrode |
US20050218497A1 (en) * | 2004-03-30 | 2005-10-06 | Nec Electronics Corporation | Through electrode, spacer provided with the through electrode, and method of manufacturing the same |
US20080060693A1 (en) * | 2004-09-30 | 2008-03-13 | Basf Aktiengesellschaft | Thermoelectric Material Contact |
US10477702B2 (en) | 2004-11-24 | 2019-11-12 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board |
US10765011B2 (en) | 2004-11-24 | 2020-09-01 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board |
EP1830615A1 (en) * | 2004-11-24 | 2007-09-05 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board and method for manufacturing same |
US9659849B2 (en) | 2004-11-24 | 2017-05-23 | Dai Nippon Printing Co., Ltd. | Method for manufacturing multilayer wiring board |
EP1830615A4 (en) * | 2004-11-24 | 2010-04-28 | Dainippon Printing Co Ltd | Multilayer wiring board and method for manufacturing same |
US20080083558A1 (en) * | 2004-11-24 | 2008-04-10 | Dai Nippon Printing Co., Ltd. | Multilayer Wiring Board And Method For Manufacturing The Same |
US9136214B2 (en) | 2004-11-24 | 2015-09-15 | Dai Nippon Printing Co., Ltd. | Method for manufacturing multilayer wiring board |
US7800002B2 (en) | 2004-11-24 | 2010-09-21 | Dai Nippon Printing Co., Ltd. | Multilayer wiring board |
US20100116782A1 (en) * | 2004-11-24 | 2010-05-13 | Dai Nippon Printing Co., Ltd. | Method for manufacturing multilayer wiring board |
AU2005314077B2 (en) * | 2004-12-07 | 2010-08-05 | Multi-Fineline Electronix, Inc. | Miniature circuitry and inductive components and methods for manufacturing same |
EP1861857A2 (en) * | 2004-12-07 | 2007-12-05 | M-Flex Multi-Fineline Electronix, Inc. | Miniature circuitry and inductive components and methods for manufacturing same |
US7690110B2 (en) | 2004-12-07 | 2010-04-06 | Multi-Fineline Electronix, Inc. | Methods for manufacturing miniature circuitry and inductive components |
US20070294888A1 (en) * | 2004-12-07 | 2007-12-27 | Whittaker Ronald W | Miniature circuitry and inductive components and methods for manufaturing same |
EP1861857A4 (en) * | 2004-12-07 | 2009-09-02 | Multi Fineline Electronix Inc | MINIATURE CIRCUIT AND INDUCTOR COMPONENTS, AND METHODS OF MANUFACTURING THE SAME |
US20070063316A1 (en) * | 2005-09-22 | 2007-03-22 | International Rectifier Corporation | Flip chip semiconductor device and process of its manufacture |
US8154105B2 (en) * | 2005-09-22 | 2012-04-10 | International Rectifier Corporation | Flip chip semiconductor device and process of its manufacture |
US7768085B2 (en) * | 2005-10-11 | 2010-08-03 | Icemos Technology Ltd. | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20070085117A1 (en) * | 2005-10-11 | 2007-04-19 | Icemos Technology Corporation | Photodetector array using isolation diffusions as crosstalk inhibitors between adjacent photodiodes |
US20070093066A1 (en) * | 2005-10-24 | 2007-04-26 | Rajashree Baskaran | Stacked wafer or die packaging with enhanced thermal and device performance |
DE112006002909B4 (en) * | 2005-10-24 | 2014-10-30 | Intel Corporation | Layered wafer or die packaging with improved heat and component performance |
GB2444467A (en) * | 2005-10-24 | 2008-06-04 | Intel Corp | Stackable wafer or die packaging with enhanced thermal and device performance |
WO2007050754A3 (en) * | 2005-10-24 | 2007-06-14 | Intel Corp | Stackable wafer or die packaging with enhanced thermal and device performance |
GB2444467B (en) * | 2005-10-24 | 2010-12-08 | Intel Corp | Stacked wafer or die packaging with enhanced thermal and device performance |
US7723759B2 (en) | 2005-10-24 | 2010-05-25 | Intel Corporation | Stacked wafer or die packaging with enhanced thermal and device performance |
US20090218671A1 (en) * | 2008-03-03 | 2009-09-03 | Kimihito Kuwabara | Semiconductor device and method of fabricating the same |
US20110115085A1 (en) * | 2008-03-03 | 2011-05-19 | Panasonic Corporation | Semiconductor device and method of fabricating the same |
US20180331254A1 (en) * | 2008-06-06 | 2018-11-15 | Osram Opto Semiconductors Gmbh | Optoelectronic Component and Method for the Production Thereof |
US20110210357A1 (en) * | 2008-06-06 | 2011-09-01 | Osram Opto Semiconductors Gmbh | Optoelectronic Component and Method for the Production Thereof |
US11222992B2 (en) * | 2008-06-06 | 2022-01-11 | Osram Oled Gmbh | Optoelectronic component and method for the production thereof |
US10128405B2 (en) * | 2008-06-06 | 2018-11-13 | Osram Opto Semiconductors Gmbh | Optoelectronic component and method for the production thereof |
US20100012934A1 (en) * | 2008-07-17 | 2010-01-21 | Oh-Jin Jung | Semiconductor chip and semiconductor chip stacked package |
WO2010083922A1 (en) * | 2009-01-21 | 2010-07-29 | Austriamicrosystems Ag | Semiconductor component having interlayer connection and method for the production thereof |
US8143532B2 (en) * | 2009-02-05 | 2012-03-27 | Xilinx, Inc. | Barrier layer to prevent conductive anodic filaments |
US20100193229A1 (en) * | 2009-02-05 | 2010-08-05 | Xilinx, Inc. | Barrier layer to prevent conductive anodic filaments |
US20120132460A1 (en) * | 2009-06-17 | 2012-05-31 | Hamamatsu Photonics K.K. | Laminated wiring board |
EP2445004A4 (en) * | 2009-06-17 | 2018-02-14 | Hamamatsu Photonics K.K. | Laminated wiring board |
US8847080B2 (en) * | 2009-06-17 | 2014-09-30 | Hamamatsu Photonics K.K. | Laminated wiring board |
US20120199857A1 (en) * | 2009-10-07 | 2012-08-09 | Digitaloptics Corporation East | Wafer-Scale Emitter Package Including Thermal Vias |
WO2011044393A1 (en) * | 2009-10-07 | 2011-04-14 | Tessera North America, Inc. | Wafer-scale emitter package including thermal vias |
FR2951871A1 (en) * | 2009-10-23 | 2011-04-29 | St Microelectronics Sa | INTERFACE PLATE BETWEEN INTEGRATED CIRCUITS |
EP2315243A1 (en) * | 2009-10-23 | 2011-04-27 | STmicroelectronics SA | Interposer between integrated circuits |
US8624996B2 (en) | 2009-12-31 | 2014-01-07 | DigitalOptics Corporation Europe Limited | Auto white balance algorithm using RGB product measure |
US10672718B2 (en) * | 2010-03-03 | 2020-06-02 | Georgia Tech Research Corporation | Through-package-via (TPV) structures on inorganic interposer and methods for fabricating same |
US20160141257A1 (en) * | 2010-03-03 | 2016-05-19 | Georgia Tech Research Corporation | Through-package-via (tpv) structures on inorganic interposer and methods for fabricating same |
US20110227860A1 (en) * | 2010-03-22 | 2011-09-22 | Park Ho Joon | Resistive touch screen |
US8324511B1 (en) * | 2010-04-06 | 2012-12-04 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US9324614B1 (en) | 2010-04-06 | 2016-04-26 | Amkor Technology, Inc. | Through via nub reveal method and structure |
US8440554B1 (en) | 2010-08-02 | 2013-05-14 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US9159672B1 (en) | 2010-08-02 | 2015-10-13 | Amkor Technology, Inc. | Through via connected backside embedded circuit features structure and method |
US8487445B1 (en) | 2010-10-05 | 2013-07-16 | Amkor Technology, Inc. | Semiconductor device having through electrodes protruding from dielectric layer |
US8900995B1 (en) | 2010-10-05 | 2014-12-02 | Amkor Technology, Inc. | Semiconductor device and manufacturing method thereof |
US8390130B1 (en) | 2011-01-06 | 2013-03-05 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US9082833B1 (en) | 2011-01-06 | 2015-07-14 | Amkor Technology, Inc. | Through via recessed reveal structure and method |
US9431323B1 (en) | 2011-11-29 | 2016-08-30 | Amkor Technology, Inc. | Conductive pad on protruding through electrode |
US8552548B1 (en) | 2011-11-29 | 2013-10-08 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US10410967B1 (en) | 2011-11-29 | 2019-09-10 | Amkor Technology, Inc. | Electronic device comprising a conductive pad on a protruding-through electrode |
US8981572B1 (en) | 2011-11-29 | 2015-03-17 | Amkor Technology, Inc. | Conductive pad on protruding through electrode semiconductor device |
US9947623B1 (en) | 2011-11-29 | 2018-04-17 | Amkor Technology, Inc. | Semiconductor device comprising a conductive pad on a protruding-through electrode |
US11043458B2 (en) | 2011-11-29 | 2021-06-22 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing an electronic device comprising a conductive pad on a protruding-through electrode |
US9129943B1 (en) | 2012-03-29 | 2015-09-08 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US10014240B1 (en) | 2012-03-29 | 2018-07-03 | Amkor Technology, Inc. | Embedded component package and fabrication method |
US9048298B1 (en) | 2012-03-29 | 2015-06-02 | Amkor Technology, Inc. | Backside warpage control structure and fabrication method |
US9812629B2 (en) * | 2012-07-13 | 2017-11-07 | Industrial Technology Research Institute | Thermoelectric conversion structure and its use in heat dissipation device |
US20150257282A1 (en) * | 2014-03-04 | 2015-09-10 | Qualcomm Incorporated | Substrate with conductive vias |
US9596768B2 (en) * | 2014-03-04 | 2017-03-14 | Qualcomm Incorporated | Substrate with conductive vias |
US11837458B2 (en) | 2016-12-30 | 2023-12-05 | Intel Corporation | Substrate with gradiated dielectric for reducing impedance mismatch |
US11164827B2 (en) * | 2016-12-30 | 2021-11-02 | Intel Corporation | Substrate with gradiated dielectric for reducing impedance mismatch |
US10764988B2 (en) * | 2018-05-31 | 2020-09-01 | Panasonic Intellectual Property Management Co., Ltd. | Imaging device |
CN110581436A (en) * | 2018-06-08 | 2019-12-17 | 原子能和替代能源委员会 | Photonic chip through which the channel passes |
US11114818B2 (en) * | 2018-06-08 | 2021-09-07 | Commissariat A L'energie Atomique Et Aux Energies Alternatives | Photonic chip passed through by a via |
WO2019234323A1 (en) * | 2018-06-08 | 2019-12-12 | Commissariat a l'énergie atomique et aux énergies alternatives | Photonic chip with buried laser source |
CN112219288A (en) * | 2018-06-08 | 2021-01-12 | 原子能和替代能源委员会 | Photonic chip with buried laser source |
US12021347B2 (en) | 2018-06-08 | 2024-06-25 | Commissariat a l'énergie atomique et aux énergies alternatives | Photonic chip with buried laser source |
US11201122B2 (en) | 2018-09-27 | 2021-12-14 | Taiwan Semiconductor Manufacturing Co., Ltd. | Method of fabricating semiconductor device with reduced warpage and better trench filling performance |
US11887912B2 (en) * | 2020-06-18 | 2024-01-30 | Fudan University | Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof |
US20230099959A1 (en) * | 2020-06-18 | 2023-03-30 | Fudan University | Through silicon via structure for three-dimensional integrated circuit packaging and manufacturing method thereof |
US20220299607A1 (en) * | 2021-03-16 | 2022-09-22 | Yuuki OKA | Light source module, distance-measuring apparatus, and mobile object |
US11968780B2 (en) * | 2022-06-02 | 2024-04-23 | International Business Machines Corporation | Method to manufacture conductive anodic filament-resistant microvias |
US20230397331A1 (en) * | 2022-06-02 | 2023-12-07 | International Business Machines Corporation | Method to manufacture conductive anodic filament-resistant microvias |
Also Published As
Publication number | Publication date |
---|---|
EP1419526A2 (en) | 2004-05-19 |
JP2005501413A (en) | 2005-01-13 |
US20040201095A1 (en) | 2004-10-14 |
KR20040060919A (en) | 2004-07-06 |
WO2003019651A2 (en) | 2003-03-06 |
WO2003019651A3 (en) | 2003-05-22 |
AU2002323388A1 (en) | 2003-03-10 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US20030038344A1 (en) | Through-via vertical interconnects, through-via heat sinks and associated fabrication methods | |
US9881904B2 (en) | Multi-layer semiconductor devices fabricated using a combination of substrate and via structures and fabrication techniques | |
US8592932B2 (en) | Apparatus and methods for constructing semiconductor chip packages with silicon space transformer carriers | |
US7410884B2 (en) | 3D integrated circuits using thick metal for backside connections and offset bumps | |
US8129811B2 (en) | Techniques for three-dimensional circuit integration | |
US8367472B2 (en) | Method of fabricating a 3-D device | |
TWI429046B (en) | Semiconductor device and method for forming the same | |
US8426921B2 (en) | Three-dimensional integrated circuits and techniques for fabrication thereof | |
US8395269B2 (en) | Method of stacking semiconductor chips including forming an interconnect member and a through electrode | |
TWI399827B (en) | Method of forming stacked dies | |
TW201935583A (en) | Method of forming via for semiconductor device connection | |
US20030215984A1 (en) | Chip and wafer integration process using vertical connections | |
US8772919B2 (en) | Image sensor package with trench insulator and fabrication method thereof | |
CN104425452A (en) | Electronic component package and manufacturing method thereof | |
CN113764392A (en) | Photonic packaging and manufacturing method | |
EP4510176A1 (en) | Method for assembling eic to pic to build an optical engine | |
TW202406034A (en) | Integrated circuit packages and methods of forming the same | |
CN118969635A (en) | Method for manufacturing three-dimensional semiconductor device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AS | Assignment |
Owner name: MCNC, NORTH CAROLINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:PALMER, WILLIAM DEVEREUX;BONAFEDE, SALVATORE;TEMPLE, DOROTA;AND OTHERS;REEL/FRAME:013239/0415 Effective date: 20020822 |
|
STCB | Information on status: application discontinuation |
Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION |
|
AS | Assignment |
Owner name: MCNC RESEARCH AND DEVELOPMENT INSTITUTE, NORTH CAR Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MCNC;REEL/FRAME:016323/0779 Effective date: 20030101 Owner name: RESEARCH TRIANGLE INSTITUTE, NORTH CAROLINA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:MCNC RESEARCH AND DEVELOPMENT INSTITUTE;REEL/FRAME:016323/0730 Effective date: 20050208 |