US20020185673A1

US20020185673A1 - Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof

Info

Publication number: US20020185673A1
Application number: US09/846,181
Authority: US
Inventors: Ching-Hsiang Hsu; Ching-Sung Yang
Original assignee: eMemory Technology Inc
Current assignee: eMemory Technology Inc
Priority date: 2001-05-02
Filing date: 2001-05-02
Publication date: 2002-12-12
Also published as: US6677198B2; US20020182805A1

Abstract

The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which structure comprises an N-substrate, a deep P-well formed on the substrate, and an N-well formed on the deep P-well. A deep p-type region and a shallow p-type region are ion-implanted in the N-well. The deep p-type region is connected to the shallow p-type region. An n-type region is ion-implanted in the deep p-type region to be electrically shorted with the deep p-type region and be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. The present invention can apply the same voltage to the deep P-well and the N-well on the N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.

Description

FIELD OF THE INVENTION

The present invention relates to a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof. The present invention can apply the same voltage to a deep P-well and an N-well on an N-substrate by adding in a triple well architecture so that the leakage current capably generated can be reduced to minimum, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.

BACKGROUND OF THE INVENTION

Flash memories have been widely used in electronic products such as portable computers or communication apparatuses because of their non-volatile functions of electrically writing and erasing. The channel Fowler-Nordheim effect is generally exploited to operate the flash memory cell structure. Because the array structure thereof becomes denser and denser, the operation of each memory cell begins to influence one another. Therefore, the array density of the memory cell structure designed by using this effect has a certain limit. FIG. 1 is a cross-sectional view of the structure of a prior art channel write/erase flash memory cell. As shown in the figure, an N-

well

12 is formed on a p-type substrate 10. An n-type region 15 is ion-implanted into the N-well 12 to be used as a drain. A p-type region 16 is also implanted into the N-well 12. Another p-type region 17 is ion-implanted below the n-type region 15. Because the implanted depth of the p-type region 17 is much larger than that of the p-type region 16, it can be used as a P-well. The p-type region 17 is connected to the p-type region 16. Moreover, an n-type region 18 is also ion-implanted at anther end of the p-type region 16 to be used as a source. A stacked gate G is disposed above the p-type region 16.

The operation of the above prior art will not be further described. According to this prior art, the source of the flash memory cell needs not to be at the opposite side of the drain thereof, i.e., it is a separate source. Each drain corresponds to a well. Therefore, when the density increases, the drawback of penetrating the source and the drain will not arise. Therefore, the integration can be increased.

However, when performing the operation of erasing, if a lower end voltage is to be used to reduce the burden of a charge pump circuit, a positive voltage originally applied to a word line and a source line grounding voltage will be respectively changed to a small positive voltage applied to the word line and a negative voltage applied to the source line. The negative voltage of the source line applied to the N-

well

12 will generate a forward bias across a p-n junction between the N-well 12 and the grounded p-type substrate 10, thereby indirectly resulting in a leakage current I_Lso as to fail the action of erasing.

SUMMARY OF THE INVENTION

The primary object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, wherein a deep P-well and an N-well are formed on an N-substrate to form a triple well architecture to let the same voltage be applied to the deep P-well and the N-well on the N-substrate so that the two voltages can be balanced, thereby avoiding forward conduction of the p-n junction and thus reducing the leakage current.

The secondary object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof. The present invention can apply the same voltage to a deep P-well and an N-well on an N-substrate by adding in a triple well architecture, thereby effectively reducing end voltages when performing the operation of erasing, simplifying the design complexity of a charge pump circuit required by the whole structure, and enhancing the operating efficiency.

Another object of the present invention is to provide a structure of a low-voltage channel write/erase flash memory cell and a fabricating method thereof, which can reduce the program disturb generated when performing the operation of programming.

To accomplish the above objects, the present invention provides a structure of a low-voltage channel write/erase flash memory cell, which comprises mainly an N-substrate, a deep P-well formed on the substrate, an N-well formed on the deep P-well, and a stacked gate disposed above the N-well. A deep p-type region and a shallow p-type region are ion-implanted at predetermined positions in the N-well. An n-type region is ion-implanted in the deep p-type region to be used as a drain. Another n-type region is also ion-implanted at one side of the shallow p-type region to be used as a source. Because the present invention is operated at low voltages, the same voltage can be applied to the deep P-well and the N-well on the N-substrate to let the leakage current possibly generated be reduced to minimum.

The present invention also provides a fabricating method of the structure of a low-voltage channel write/erase flash memory cell. The proposed fabricating method comprises mainly the following steps: ion-implanting a deep P-well in an N-substrate; ion-implanting an N-well in the deep P-well; ion-implanting a shallow p-type region on the surface of the N-well; growing a tunnel oxide on the N-well and depositing a poly-Si layer; etching the tunnel oxide and the poly-Si layer; depositing an oxide-nitride-oxide (ONO) film on the etched tunnel oxide and the etched poly-Si layer; depositing a poly-Si layer on the ONO film; etching all the grown layers and the deposited layers on the N-well to form a rectangular stacked layer (two sides of the rectangular stacked layer being the exposed N-well); ion-implanting a deep p-type region in the N-well and disposed at one side of the rectangular stacked layer; and ion-implanting a plurality of n-type regions in the N-well and disposed at two sides of the rectangular stacked layer.

The various objects and advantages of the present invention will be more readily understood from the following detailed description when read in conjunction with the appended drawings, in which:

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross-sectional view of the structure of a prior art channel write/erase flash memory cell; [0011]
FIGS. 2A to [0012] 2L are cross-sectional views showing the process flow of a flash memory cell according to a preferred embodiment of the present invention; and
FIG. 3 is a cross-sectional view showing the operation of erasing of a flash memory cell according to the preferred embodiment of the present invention.[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 2A to [0014] 2L are cross-sectional views showing the process flow of a flash memory cell according to a preferred embodiment of the present invention. The fabricating method of the present invention comprises mainly the following steps:
Step A: A semiconductor N-[0015] substrate 20 is provided; a plurality of field oxides (FOX) 21 are formed at specific regions in the substrate 20 using photolithography and oxidation techniques; a deep P-well 22 is ion-implanted in the substrate 20 between the field oxides 22, as shown in FIG. 2A;
Step B: An N-[0016] well 24 is formed in the deep P-well 22 of the substrate 20 using ion-implantation technique, as shown in FIG. 2B;
Step C: A shallow p-[0017] type region 26 is formed on the surface of the N-well 24 using ion-implantation technique; a tunnel oxide 31 is grown on the surface of the N-well; a first poly-Si layer 32 is then deposited and stacked on the tunnel oxide 31, as shown in FIG. 2C;
Step D: The patterns of the [0018] tunnel oxide 31 and the first poly-Si layer 32 are defined using photolithography and etching techniques, as shown in FIG. 2D;
Step E: An [0019] ONO film 33 is deposited on the etched tunnel oxide 31 and the etched first poly-Si layer 32; The ONO film 33 is then etched, as shown in FIG. 2E;
Step F: A second poly-[0020] Si layer 35 is deposited and stacked on the surface of the ONO film 33, as shown in FIG. 2F;
Step G: The second poly-[0021] Si layer 35 on the N-well 24, the ONO film 33, and the first poly-Si layer 32 are etched using anisotropic dry etching technique until the tunnel oxide 31 is exposed, thereby forming a rectangular stacked layer 30; only part of the tunnel oxide 31 straddling between two field oxides 21 is reserved; a thicker tunneling oxide is formed at the edge of the rectangular stacked layer 30 by means of oxidation to form a smiling effect oxide 312, as shown in FIG. 2G;
Step H: A deep p-[0022] type region 27 is formed in the N-well 24 at the left side of the rectangular stacked layer 30, and a shallow p-type region 26 is formed in the N-well 24 below the rectangular stacked layer 30 using ion-implantation technique; the implanted depth of the deep p-type region 27 is larger than that of the shallow p-type region 26, as shown in FIG. 2H;
Step I: Two n-[0023] type regions 25 and 28 are formed in the N-well 24 at two sides of the rectangular stacked layer 30 using ion-implantation technique; the n-type region 25 at the left side of the rectangular stacked layer 30 is implanted in the deep p-type region 27, as shown in FIG. 2I;
Step J: A third poly-[0024] Si layer 37 is deposited to cover the rectangular stacked layer 30 and the exposed tunnel oxide 31 at two sides thereof, as shown in FIG. 2J;
Step K: The insulating [0025] layer 37 at the left side of the rectangular stacked layer 30 is etched to form a contact hole 38 so as to expose the part with the deep p-type region 27 and the n-type region 25 implanted therein; the deep p-type region 27 and the n-type region 25 are electrically shorted via a metal 29, as shown in FIG. 2K; and
Step L: Connection of metals is performed; i.e., a [0026] metal contact 39 is connected to the deep p-type region 27 and the n-type region 25 via the etched contact hole 38 of the insulating layer 37, as shown in FIG. 2L.
FIG. 3 is a cross-sectional view showing the operation of erasing of a flash memory cell according to the preferred embodiment of the present invention, wherein a deep P-well [0027] 22 is formed on an N-substrate 20, and an N-well 24 is formed on the P-well 22. A deep p-type region 27 and a shallow p-type region 26 are ion-implanted in the N-well 24. The deep p-type region 27 is connected to one end of the shallow p-type region 26. An n-type region 25 is further ion-implanted in the deep p-type region to electrically short with the deep p-type region 27 and be used as a drain. Another n-type region 28 is also implanted at one side of the shallow p-type region 26 to be used a source. Furthermore, the implanted depth of the deep p-type region 27 is larger than that of the shallow p-type region, i.e., the deep p-type region can also be used as a P-well. A tunnel oxide 31 is disposed above the N-well 24 to form a smiling effect junction with a stacked control gate G by oxidation. Thereby, program disturb generated when performing the operation of programming can be reduced through the structure change of the tunnel oxide 31. Additionally, the stacked control gate G comprises a control gate and a float gate.
Because the present invention is operated at low voltages, the same voltage can be applied to the deep P-well [0028] 22 and the N-well 24 on the N-substrate 20, such as a source line voltage V_SLand a deep P-well voltage V_{deep P-well}, to let the leakage current possibly generated be reduced to minimum. As shown in Table 1, when performing the operation of erasing, the source line voltage V_SLis set to −8V, the deep P-well voltage V_{deep P-well}is set to −8V, and a word line voltage V_WLis set to 10V. Thereby, the source line voltage V_SLand the deep P-well voltage V_{deep P-well}will balance each other so that forward bias will not be formed across a p-n junction between the deep P-well 22 and the N-substrate 20, hence reducing the leakage current.

TABLE 1

Bit line voltage Word line voltage Source Deep P-

V_BL V_WL line well

Not Not voltage voltage

Selected selected Selected selected V_SL V_deep-P-well

Program 6 V 0 V −10 V floating floating 0 V

Erase floating floating 10 V floating −8 V −8 V

Read 0 V floating 4 V floating 1 V 0 V
Although the present invention has been described with reference to the preferred embodiment thereof, it will be understood that the invention is not limited to the details thereof. Various substitutions and modifications have been suggested in the foregoing description, and other will occur to those of ordinary skill in the art. P-type semiconductors and n-type semiconductors can interchange each other in the structure of the present invention. For instance, the triple well structure of N-well/deep P-well/N-substrate can be replaced with a triple well structure of P-well/deep N-well/P-substrate. Therefore, all such substitutions and modifications are intended to be embraced within the scope of the invention as defined in the appended claims. [0029]

Claims

I claim:

1. A fabricating method of a low-voltage channel write/erase flash memory cell, comprising mainly the steps of:

a. ion-implanting a deep P-well in an N-substrate;

b. ion-implanting an N-well in said deep P-well;

c. ion-implanting a shallow p-type region on the surface of said N-well;

d. growing a tunnel oxide on said shallow p-type region and depositing a poly-Si layer;

e. etching said tunnel oxide and said poly-Si layer;

f. etching out an ONO film on said etched tunnel oxide and said etched poly-Si layer;

g. depositing a poly-Si layer on said ONO film;

h. etching all grown layers and deposited layers on said tunnel oxide to form a rectangular stacked layer with exposed regions of said tunnel oxide region at two sides thereof;

i. performing oxidation to form a smiling effect oxide between said rectangular stacked layer and the surface of said N-well;

j. ion-implanting a deep p-type region at one side of said rectangular stacked layer and in said N-well; and

k. ion-implanting a plurality of n-type regions in said N-well and at two sides of said rectangular stacked layer.

2. The fabricating method of a flash memory cell as claimed in claim 1, wherein said deep p-type region in said Step j is connected to one side of said shallow p-type region, and the implanted depth of said deep p-type region is larger than that of said shallow p-type region.

3. The fabricating method of a flash memory cell as claimed in claim 1, wherein one of said n-type regions in said Step k is disposed in said deep p-type region.

4. The fabricating method of a flash memory cell as claimed in claim 1 further comprising the following steps:

l. depositing a poly-Si layer to cover said rectangular stacked layer and two sides thereof;

m. etching said poly-Si layer disposed at one side of said rectangular stacked layer to form a contact hole so as to expose said N-well having said deep p-type region and said n-type region thereon; and

n. providing a metal contact in said etched contact hole of said poly-Si layer to join said N-well having said deep p-type region and said n-type region thereon.

5. The fabricating method of a flash memory cell as claimed in claim 1, wherein said p-type semiconductors and said n-type semiconductors in each step can interchange each other, e.g., an npn structure can be replaced with a pnp structure.

6. A structure of a low-voltage channel write/erase flash memory cell, comprising mainly:

an N-substrate;

a deep P-well formed on said substrate;

an N-well formed on said deep P-well, a deep p-type region and a shallow p-type region being ion-implanted at predetermined positions in said N-well; and

a stacked gate disposed above said N-well.

7. The structure of a flash memory cell as claimed in claim 6, wherein an oxide is further disposed between said N-well and said stacked gate.

8. The structure of a flash memory cell as claimed in claim 7, wherein a smiling effect pattern is etched out between said stacked gate and said oxide.

9. The structure of a flash memory cell as claimed in claim 6, wherein an n-type region is further ion-implanted in said deep p-type region in said N-well to be used as a drain.

10. The structure of a flash memory cell as claimed in claim 6, wherein the implanted depth of said deep p-type region in said N-well is larger than that of said shallow p-type region in said N-well.

11. The structure of a flash memory cell as claimed in claim 6, wherein said deep p-type region in said N-well is connected to one end of said shallow p-type region.

12. The structure of a flash memory cell as claimed in claim 6, wherein an n-type region is further disposed at the other side of said shallow p-type region in said N-well to be used as a source.

13. The structure of a flash memory cell as claimed in claim 6, wherein said n-type region implanted in said deep p-type region is connected to said deep p-type region via an electrical short circuit.

14. The structure of a flash memory cell as claimed in claim 13, wherein said electrical short circuit is formed by using a metal contact to penetrate a junction of said n-type region in said deep p-type region and said deep p-type region.

15. The structure of a flash memory cell as claimed in claim 13, wherein said electrical short circuit is formed by using a metal contact to connect said exposed n-type region in said deep p-type region with said deep p-type region.

16. The structure of a flash memory cell as claimed in claim 6, wherein said n-type semiconductors and said p-type semiconductors can interchange each other, e.g., an npn structure can be replaced with a pnp structure.