+

US20020160185A1 - Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same - Google Patents

Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same Download PDF

Info

Publication number
US20020160185A1
US20020160185A1 US10/138,485 US13848502A US2002160185A1 US 20020160185 A1 US20020160185 A1 US 20020160185A1 US 13848502 A US13848502 A US 13848502A US 2002160185 A1 US2002160185 A1 US 2002160185A1
Authority
US
United States
Prior art keywords
circuit tape
adhesive
adhesive layer
semiconductor devices
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
US10/138,485
Inventor
Akira Nagai
Shuji Eguchi
Masahiko Ogino
Masanori Segawa
Toshiak Ishii
Nobutake Tsuyuno
Hiroyoshi Kokaku
Rie Hattori
Makoto Morishima
Ichiro Anjoh
Kunihiro Tsubosaki
Chuichi Miyazaki
Makoto Kitano
Mamoru Mita
Norio Okabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Renesas Technology Corp
Original Assignee
Individual
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Individual filed Critical Individual
Priority to US10/138,485 priority Critical patent/US20020160185A1/en
Publication of US20020160185A1 publication Critical patent/US20020160185A1/en
Assigned to RENESAS TECHNOLOGY CORPORATION reassignment RENESAS TECHNOLOGY CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HITACHI, LTD.
Priority to US10/724,092 priority patent/US7202570B2/en
Abandoned legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H01L23/4951—Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/04042—Bonding areas specifically adapted for wire connectors, e.g. wirebond pads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0555—Shape
    • H01L2224/05552—Shape in top view
    • H01L2224/05553—Shape in top view being rectangular
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061—Disposition
    • H01L2224/0612—Layout
    • H01L2224/0613—Square or rectangular array
    • H01L2224/06134—Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06136—Covering only the central area of the surface to be connected, i.e. central arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/4824—Connecting between the body and an opposite side of the item with respect to the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01014—Silicon [Si]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01045—Rhodium [Rh]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01087—Francium [Fr]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/102—Material of the semiconductor or solid state bodies
    • H01L2924/1025—Semiconducting materials
    • H01L2924/1026—Compound semiconductors
    • H01L2924/1032—III-V
    • H01L2924/10329—Gallium arsenide [GaAs]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/12—Passive devices, e.g. 2 terminal devices
    • H01L2924/1204—Optical Diode
    • H01L2924/12042—LASER
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T156/00—Adhesive bonding and miscellaneous chemical manufacture
    • Y10T156/10—Methods of surface bonding and/or assembly therefor
    • Y10T156/1052—Methods of surface bonding and/or assembly therefor with cutting, punching, tearing or severing
    • Y10T156/1062—Prior to assembly
    • Y10T156/107—Punching and bonding pressure application by punch
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/249921—Web or sheet containing structurally defined element or component
    • Y10T428/249953—Composite having voids in a component [e.g., porous, cellular, etc.]
    • Y10T428/249955—Void-containing component partially impregnated with adjacent component
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00—Stock material or miscellaneous articles
    • Y10T428/28—Web or sheet containing structurally defined element or component and having an adhesive outermost layer
    • Y10T428/2848—Three or more layers

Definitions

  • the present invention relates to a circuit tape, a semiconductor device, and a method of manufacturing the same, which are superior in electrical characteristics, mounting reliability, and assembling easiness, and are responsive to the requirements for high density mounting, multipins mounting, and fast transmittance.
  • the grid array structure is a structure of a semiconductor element, in which the connecting terminals are provided in a grid array over the entire mounting surface of the semiconductor element by using a multilayer carrier substrate.
  • the grid array structure includes a ball grid array structure (BGA), which has a shortened connecting terminal length in order to make fast signal transmission possible.
  • BGA ball grid array structure
  • the ball type structure of the connecting terminal increases the width of its conductor; therefore, the ball structure is also effective in decreasing inductance.
  • organic materials haying a relatively low dielectric constant have been investigated for use in the multilayer carrier substrate.
  • the organic materials have generally a larger thermal expansion coefficient than the semiconductor element, and so thermal stress generated by the difference in thermal expansion becomes a problem from the point of view of connection reliability, and so on. Recently, a structure which does not use a carrier substrate has been proposed for the BGA package.
  • a new semiconductor element package structure has been disclosed (U.S. Pat. No. 5,148,265), in which the connection reliability is improved by using an elastomer material having a low modulus of elasticity for reducing the thermal stress generated by the difference in thermal expansion between the semiconductor element and the mounting substrate.
  • the proposed package structure uses a circuit tape composed of a polyimide and the like, instead of a carrier substrate, for electrically connecting the semiconductor element and the mounting substrate. Therefore, the electrical connections between the semiconductor element and the circuit tape are effected by a wire bonding method or a bonding connection with leads, and the circuit tape and the mounting substrate are electrically connected by soldering ball terminals.
  • a silicone material is generally used since this is a material having a low modulus of elasticity and a superior heat resistance.
  • the steps of printing an uncured liquid resin on the circuit tape using masks, and subsequently, curing the printed resin are generally used.
  • the above method has problems, such as a difficulty in maintaining the flatness of the buffer layer obtained by the printing, and the complexity of the printing process, which requires a long time for the printing, is disadvantageous. Accordingly, the above method is not suitable for a mass-production process, and so the problems which undesirably affect the assembling yield and reliability of mounting caused by the difficulty in maintaining the flatness of the buffer layer are yet to be solved.
  • One of the objects of the present invention is to provide a method of obtaining a stress buffer layer which is superior in flatness by using a film material as the elastomer material for reducing the thermal stress in the semiconductor devices, thereby obtaining semiconductor devices which are superior in mass productivity.
  • the present invention provides the following measures.
  • the measures can be achieved by providing a semiconductor device comprising a circuit tape having a pattern layer connected electrically to a semiconductor element, an external terminal provided on the circuit tape for electrically connecting the circuit tape to a mounting substrate, and film material for causing the circuit tape to adhere to the semiconductor element while maintaining an insulation condition between the circuit tape and the semiconductor element, wherein the film material for effecting the adhering has a physical property such that the modulus of elasticity of the film material in the temperature range of a solder reflow condition for mounting (200-250° C.) is at least 1 MPa.
  • the above film material for effecting the adhering is passed through a process for forming an external terminal, such as a solder ball and the like, for connecting the mounting substrate and the circuit tape, or a solder reflow process for mounting the semiconductor element of the present invention onto a mounting substrate in the manufacturing process of the semiconductor devices
  • the reflow temperature is generally a high temperature in the range of 200-250° C. Therefore, if the semiconductor device contains moisture, the moisture evaporates during the heat treatment, and the film material swells due to the vapor pressure of the moisture. When the swelling exceeds a threshold value, a foaming phenomenon is generated, and defects, such as void formation, delamination, and the like, are generated.
  • the film material to be used is required to have as low a moisture absorption rate as possible and a high modulus of elasticity in the range of the reflow temperature.
  • various film materials have been studied, and it was found that the adhesive materials having a modulus of elasticity in the temperature range of a reflow process of at least 1 MPa had superior reflow characteristics.
  • FIG. 1 Several examples of the temperature dependence of the modulus of elasticity of the material are shown in FIG. 1.
  • the amount of swelling depends on the ratio of the vapor pressure and the modulus of elasticity, and the higher the modulus of elasticity is, the less will be the amount of swelling.
  • the foaming phenomenon is generated when the amount of swelling exceeds the break elongation, one of the mechanical properties of the material.
  • the modulus of elasticity correlates with the mechanical strength of the adhesive film material, and generally, the higher the modulus of elasticity is, the greater will be the tendency to increase the break stress and break elongation.
  • the adhesive film material may be either a thermosetting resin or a thermoplastic resin.
  • the adhesive layer is sometimes composed of either sticky adhesive agents or sticky-cohesive adhesive agents, in addition to the adhesive agents made of the above material.
  • the thermoplastic resin preferably has a glass transition temperature, i.e. a changing point of modulus of elasticity, which is higher then the temperature range (200-250° C.) of the reflow process.
  • the thermosetting resin is required to have a chemical or physical crosslinking structure to a certain degree at a temperature in the rubber region, which is higher than the glass transition temperature.
  • the modulus of elasticity in the rubber region is generally proportional to the crosslinking density, and the crosslinking density must be increased in order to increase the modulus of elasticity.
  • the film material is desirably composed of a resin having a low modulus of elasticity which is at the utmost 4000 MPa at room temperature, in order to operate as a stress buffer layer.
  • the coefficient of moisture absorption at 85° C./85% RH for 168 hours is desirably, at the utmost, 3% in view of the reflow characteristics.
  • the film material materials having a low modulus of elasticity, except for a silicone material, can be used.
  • the structure of the film material is not restricted to a homogeneous structure composed of an adhesive agent component, but also, for instance, a three layer structure having adhesive layers at both surfaces of a supporter, respectively, or a structure in which the adhesive agent is impregnated into a porous supporter, can be used.
  • shapes of the film various shapes manufactured by stamping, a mesh-like shape, and the like can be used. The mesh-like shape is effective in improving the anti-reflow property at the moisture absorbing time, because the adhesion area can be decreased.
  • the supporter and the adhesive layer can be composed of a combination of at least two kinds of the above adhesive agents, the sticky adhesive agents, the sticky-cohesive adhesive agents, and the like.
  • the adhesive layer is located at each of both of the surfaces of the supporter, and each adhesive layer can be formed of a different kind of material from the other.
  • a combination is usable in which a thermosetting resin having a high fluidity is used in order to flatten or eliminate the unevenness of the pattern layer of the circuit tape side, and a thermoplastic resin, which can be adhered in a short time at a high temperature, is used at the opposite flat portion for adhering to the semiconductor element.
  • FIG. 2 A set of schematic illustrations indicating a flow of a general fabrication process for the manufacture of semiconductor devices, according to the present invention, is shown in FIG. 2.
  • the process can be divided into three representative sections.
  • the first one including STEPS 1 - 5 (FIG. 2 a ), is a method for fabricating a semiconductor element comprising (1) the step 1 of applying an adhesive film to the tape having a pattern layer, (2) the step 2 of adhering the tape having a pattern layer to the semiconductor element by means of the adhesive film while maintaining an insulating condition therebetween, (3) the step 3 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (4) the step 4 of sealing the electrically connected portion with an insulating agent, and (5) the step 5 of forming an external terminal on the tape for connection to the mounting substrate.
  • the above method is effective in improving the processability, because the circuit tape and the film material can be handled in the manner of a reel to reel process, as will be explained later.
  • the second one including STEPS 6 - 10 , (FIG. 2 b ), is a method for fabricating a semiconductor element comprising (1) the step 6 of applying an adhesive film to the semiconductor element, (2) the step 7 of adhering the tape having a pattern layer to the semiconductor element by means of the adhesive film while maintaining an insulating condition therebetween, (3) the step 8 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (4) the step 9 of sealing the electrically connected portion with an insulating agent, and (5) the step 10 of forming an external terminal on the tape for connection to the mounting substrate.
  • the above method is effective in improving the production yield of the semiconductor element itself.
  • the stress buffer layer can be formed on the semiconductor element at the wafer stage condition.
  • the third one is a method of fabricating a semiconductor clement comprising (1) the step 11 of setting the tape having the pattern layer in registration and adhering the tape to the semiconductor element using the adhesive film simultaneously with maintaining an insulating condition therebetween, (2) the step 12 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (3) the step 13 of sealing the electrically connected portion with an insulating agent, and (4) the step 14 of forming an external terminal on the tape for connection to the mounting substrate.
  • the above method is effective in shortening the manufacturing time, because the number of steps in the process can be decreased.
  • the adhesive film material of the present invention is provided between the tape material having the pattern layer and the semiconductor element by adopting a certain method, and the tape material and the semiconductor element are bonded together simultaneously or sequentially under conditions of designated temperature, pressure, and time. Subsequently, the pattern layer on the tape is electrically connected to the connecting pad of the semiconductor element.
  • a connecting method using a connecting lead previously formed on the circuit tape as a circuit for connection with the semiconductor element any one of a single point bonding method, a gang bonding method, and the like can be used.
  • the connecting portion is encapsulated with an insulating material, and finally the external terminals, which are electrically connected with the mounting substrate, are formed on the circuit tape.
  • an external terminal a solder ball is generally used, and most of the solder ball is formed by plating.
  • Metals which may be used for the plating are gold, nickel, copper, solder, and the like.
  • a method comprising the steps of transferring the tape, whereon the pattern is formed, by a long reel apparatus, stamping out the adhesive film into a designated shape, and adhering the adhesive film of the designated shape onto the circuit tape, as shown in FIG. 3, is effective for mass production.
  • the adhesive film is made of a thermosetting resin
  • the adhesive film can be made to adhere to the circuit tape while in an uncured A stage or a half-cured B stage.
  • the resin is then further cured to a condition of a final-cured C stage during the step of adhering the obtained circuit tape, to which the adhesive film is attached, to the semiconductor element. Otherwise, if the adhesive agent reaches the condition of the final cured C stage during the time that the adhesive film is adhered to the circuit tape, sometimes, an adhesive layer is newly formed on the cured film portion.
  • an application method, a film adhering method, and the like are generally used.
  • the adhesive component is desirably not sticky at room temperature, but if sticky, a mold releasing paper and the like is used.
  • FIG. 4 shows an example of the composition of a circuit tape to which an adhesive film is attached.
  • the circuit tape can be adhered to the semiconductor element. If a thermosetting resin is used for the adhesive layer at the circuit tape side and a thermoplastic resin is used for the adhesive layer at the side adhered to the semiconductor, the circuit tape having the adhesive ability shown in FIG. 4 can be provided readily.
  • the adhesive layer is composed of a thermoplastic, sticky, or cohesive material
  • the conditions for the two steps to adhere to the circuit tape and to the semiconductor element can be set as quite the same with respect to each other.
  • the curing reaction does not need to be controlled at the intermediate stages, and so a manufacturing process superior in workability can be provided.
  • the adhesive layer is composed of a sticky or cohesive material
  • the material is advantageous from the point of view of avoiding warpage of the semiconductor element, because the material can be adhered at room temperature.
  • the adhesive film is initially combined with the circuit tape, the semiconductor element is easily registered at the time of adhering to the circuit tape. Accordingly, the jigs of the adhering apparatus can be simplified, and the method becomes advantageous for mass production.
  • the unevenness of the pattern circuit on the circuit tape is sometimes eliminated by filling spaces with the adhesive layer of the film.
  • the suitability of the adhesive layer for the filling can be confirmed at the step of combining the circuit tape and the semiconductor element. Therefore, an unsuitable adhesive layer can be eliminated before joining the circuit tape to the semiconductor element, a loss of the semiconductor can be avoided, and an advantageous increase in the production yield can be attained.
  • thermosetting resin and a thermoplastic resin for the adhesive component of the film materials are as follows: epoxy resin, polyimide resin, polyamide resin, cyanate resin, isocyanate resin, fluorine-containing resin, silicon-containing resin, urethane resin, acrylate resin, styrene resin, maleimide resin, phenolic resin, unsaturated polyester resin, diallyl phthalate resin, cyanamide resin, polybutadiene resin, polyamideimide resin, polyether resin, polysulfone resin, polyester resin, polyolefine resin, polystyrene resin, polyvinyl chloride, transpolyisoprene resin, polyacetal resin, polycarbonate resin, polyphenylene ether resin, polyphenylene sulfide resin, polyacrylate resin, polyether imide resin, polyether sulfone resin, polyether ketone resin, liquid crystalline polyester resin, polyallylether nitrile resin, polybenzoimidazole resin, various kinds
  • thermosetting resin and a thermoplastic resin involve materials having an adhesiveness resulting from melting or softening of the material by heating.
  • the sticky or cohesive materials are materials having an adhesiveness produced by pressurizing.
  • the sticky and cohesive materials are as follows: various rubber groups, such as the silicone group, the butadiene group and the isoprene group, acrylate groups, polyvinyl ether groups, and the like.
  • the cohesive material includes a room temperature curing type, a type cured by heat, ultraviolet ray irradiation, electron beam irradiation, and the like, a type cured by concurrent use of an accelerator, and the like.
  • the room temperature curing type includes a moisture-reactive type which reacts in the presence of moisture in the atmosphere, a photo-reactive type which contains a photo-initiator, and an anti-oxygen material which contains peroxide, and the like.
  • the thermosetting resin generally includes a crosslinking agent, such as thiurum groups, phenol groups, isocyanate groups, and the like, and adhesive components are crosslinked three-dimensionally to form the adhesive layer at a designated temperature.
  • the material of the type cured by ultraviolet ray irradiation, or electron beam irradiation contains various photo-initiators.
  • the material of the type cured by concurrent use of an accelerator includes a solution containing a reaction accelerator and a crosslinking agent, which are applied onto the surface of the sticky layer, wherein the adhesive layer is finally formed by mixing the above two agents with a contact pressure and reacting the two agents sequentially.
  • thermosetting resin For the cohesive agent of the present invention, a thermosetting resin is relatively preferable
  • a thermosetting resin a semiconductor device, which is superior in mass productivity and reliability, can be provided by the method comprising the steps of registering the circuit tape and the semiconductor element at room temperature, bringing the wiring tape and the semiconductor element into contact to form a set, and elevating the temperature of a plurality of such sets to a designated degree simultaneously in a container, such as a constant temperature bath, for producing a curing reaction to ensure the adhesive strength.
  • the modulus of elasticity of the adhesive film material is preferably high at a high temperature region in view of the reflow characteristics, but as low as possible at room temperature.
  • the semiconductor element and the mounting substrate generally have different thermal expansion coefficients from each other, and a thermal stress is generated, when the mounting is performed, at the external terminal, which is composed of a solder ball and the like. Then, the reliability of the connection becomes remarkably important.
  • the modulus of elasticity of the adhesive film existing between the semiconductor element and the mounting substrate is low, the region of the adhesive layer becomes a stress buffer layer, and this is advantageous from the point of view of the connection reliability.
  • the modulus of elasticity at room temperature is desirably, at the utmost, 4000 MPa. More preferably, the modulus of elasticity in the entire range of the heat cycling test ( ⁇ 55° C.-150° C.) is, at the utmost, 2000 MPa.
  • silicone group materials are used as a material which has a high modulus of elasticity at a high temperature and a relatively low elastic modulus in a range of a low temperature including room temperature.
  • a film material comprising a silicone group material is one of the significantly important materials of the present invention.
  • film materials other than the silicone group material having the above characteristics, are advantageous in comparison with the silicone group material. That is, because of the weak cohesive energy of silicon, cyclic low molecular weight silicone group compounds are gradually decomposed thermally during a long heat treatment, such as during storing at a high temperature (for instance, at least 150° C.), and this sometimes becomes a cause of contamination to the environment.
  • a high temperature for instance, at least 150° C.
  • composition of the film material of the present invention is not only a homogeneous structure composed of the adhesive agent components, but also may be a three layer structure, such as a supporter having adhesive agent layers at both surfaces for instance, and a structure in which the adhesive agent is impregnated into a porous supporter.
  • a supporter of the film material films or a porous material made of polyimide, epoxy, polyethylene terephthalate, cellurose, acetate, fluorine-containing polymer, and the like can be used.
  • the various shapes obtainable by stamping out, a mesh-like shape, and the like can be used.
  • the mesh-like shape is effective in improving the anti-reflow properly at the moisture absorbing time, because the adhesion area can be decreased.
  • the three layer structure can be controlled to an arbitrary thickness and as to the kind of the adhesive layer provided at both the surfaces of the supporter, and the fluidity of the adhesive layer at the time of adhesion can be readily controlled. Furthermore, the presence of an insulating layer is ensured by the supporter located between the adhesive layers.
  • the value of vapor pressure of the adhesive material by moisture absorption at the time of reflow can be maintained at a low value by using the material, of which the film material has a coefficient of moisture absorption at 85° C./85% RH of, at the utmost, 3%, and so preferable reflow characteristics can be obtained.
  • the tape having a pattern layer is generally composed of a flexible circuit substrate. That is, a polyimide group material serving as the insulating layer, an epoxy group material, a polyimide group material, a phenolic group material, a polyamide group material, and the like are used as the adhesive layer with the conductor. Generally, copper is used as the conductor. As the wiring circuit, the copper is sometimes coated with nickel, gold plating, and the like. As the flexible circuit substrate, a material, which does not use the adhesive layer with the conductor, but uses a copper layer formed directly onto the polyimide insulating layer, is sometimes used.
  • the tape having a pattern layer is sometimes composed of a multilayer wiring structure.
  • a voltage layer, a ground layer, and so on in addition to the signal layer can be formed in the circuit tape, and so a semiconductor device which is superior in electric characteristics can be provided.
  • the one is a peripheral pad arrangement as shown in FIG. 5.
  • there are different types of structure for the arrangement of the external terminal of the semiconductor device as shown in FIGS. 6 - 1 , 6 - 2 , 6 - 3 . That is, the case wherein the external terminals are located under the semiconductor element (Fan In type, FIG. 6 1 ), the case wherein the external terminals are located outside the semiconductor element (Fan Out type, FIG. 6- 2 ), and the case wherein the external terminals are located at both under and outside the semiconductor element (Fan In/Out type, FIG. 6- 3 ) can be used.
  • FIG. 7 Another example of the pad arrangement is the central arrangement shown in FIG. 7.
  • the semiconductor device is composed of the structure shown in FIG. 8.
  • the semiconductor element is a device wherein IC, LSI, and the like, such as memories, logic devices, gate arrays, customs, power transistors, and the like, are formed on a wafer comprising semiconductor materials such as Si, GaAs, and the like, and the device has terminals for connecting to a lead, bump, and the like.
  • the semiconductor device comprising a tape having a pattern layer is used as an interconnection between the semiconductor element and the mounting substrate, which is superior in anti-reflow characteristics and connection reliability, may be provided by using a film material having a modulus of elasticity of at least 1 MPa in the reflow temperature region (200-250° C.), which is a high temperature region, as the adhesive material while maintaining the insulation between the circuit tape and the semiconductor element.
  • a film material having a modulus of elasticity of at least 1 MPa in the reflow temperature region (200-250° C.), which is a high temperature region, as the adhesive material while maintaining the insulation between the circuit tape and the semiconductor element.
  • FIG. 1 is a graph indicating temperature dependency of the modulus of elasticity of materials
  • FIGS. 2 a , 2 b , and 2 c are schematic illustrations indicating the manufacturing process of the semiconductor device of the present invention, wherein FIG. 2 a shows a method wherein the film is adhered previously to the circuit tape, FIG. 2 b shows a method wherein the film is adhered previously to the semiconductor element, and FIG. 2 c shows a method wherein the circuit tape and the semiconductor element are adhered together simultaneously via the film;
  • FIG. 3 is a schematic diagram indicating the continuous process for adhering the film using a long reel
  • FIG. 4 is a schematic diagram showing a cross section indicating the composition of a circuit tape having a film with an adhesive agent layer
  • FIG. 5 is a schematic diagram of a semiconductor element having peripheral pads
  • FIGS. 6 - 1 , 6 - 2 , 6 - 3 are schematic cross sections showing the structure of semiconductor devices using the semiconductor elements having the peripheral pads;
  • FIG. 7 is a schematic diagram showing a semiconductor element having pads located at the center of the element.
  • FIG. 8 is a schematic cross section showing the structure of a semiconductor device using a semiconductor element having pads located at the center of the element.
  • An epoxy group adhesive film (made by Hitachi Chemical Co., Ltd., AS 3000, 50 ⁇ m thick) was registered, placed, and adhered between a semiconductor element and circuit tape at 170° C. for one minute with a pressure of 50 kgf/cm 2 , and was then post-cured at 180° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd., RC021C). Finally, the semiconductor device shown in FIG. 6- 1 was obtained by fixing the solder balls, which were connecting terminals with the mounting substrate, onto the circuit tape.
  • the obtained semiconductor device was set in an infrared reflow apparatus with a maximum temperature of 245° C., and it was confirmed whether the semiconductor device exhibited defects, such as delamination and voids by foaming the adhesive layer. Furthermore, the connection reliability between the lead of the semiconductor device and the solder bump was confirmed.
  • a woven glass-epoxy copper clad laminate FR-4 (made by Hitachi Chemical Co., Ltd., MCI-E-67) was used as the mounting substrate. The reliability was evaluated by performing a thermal cycling test ( ⁇ 55° C. ⁇ ⁇ 150° C., 1000 times).
  • a film material having a three layer structure was obtained by applying an adhesive agent (made by Hitachi Chemical Co. Ltd., DF335), composed of a die bonding film material, onto both surfaces of a polyimide film (made by Ube Kosan Co., Ltd., SGA, 50 ⁇ m thick) to a thickness of 50 ⁇ m.
  • the obtained film material was registered and adhered to circuit tape at 170° C. for five seconds with a pressure of 30 kgf/cm 2 . Under the above conditions, the unadhered adhesive layer exhibited a sufficient adhesive force to adhere to the semiconductor element.
  • the circuit tape attached with the film material was adhered to the semiconductor element at 200° C.
  • a low elastic adhesive film composed of an epoxy resin and acrylic rubber (made by Hitachi Chemical Co. Ltd., trial product, 150 ⁇ m thick) was registered, placed, and adhered between the semiconductor element and the circuit tape at 180° C. for 30 seconds with a pressure of 100 kgf/cm 2 , and was then post-cured at 180° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by wire bonding.
  • the connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd., TSJ 3150)
  • the semiconductor device shown in FIG. 6- 3 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • a film material having a three layer structure was obtained by adhering a low elastic adhesive film composed of epoxy resin and acrylic rubber (made by Hitachi Chemical Co. Ltd., trial product, 50 ⁇ m thick) to both surfaces of a woven glass-epoxy resin laminate (obtained by eliminating a copper cladding by etching from both surfaces of MCL-E-679 made by Hitachi Chemical Co., Ltd.).
  • the film material was registered, placed, and adhered between the semiconductor element and the circuit tape at 200° C. for 20 seconds with a pressure of 80 kgf/cm 2 , and was then post-cured at 180° C. for 60 minutes in a constant temperature bath.
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding.
  • the connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd., TSJ 3153).
  • the semiconductor device shown in FIG. 8 was obtained by filing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • a LOC (Lead on chip) Film (made by Hitachi Chemical Co. Ltd., HM122U, 100 ⁇ m thick) having a three layer structure was registered and adhered to the circuit tape at 300° C. for 2 seconds with pressure of 150 kgf/cm 2 .
  • the film was stamped out into a designated shape using the long scale apparatus shown in FIG. 3, and the stamped film was adhered to the circuit tape continuously. Because the adhesive layer of the film was made of a thermoplastic resin, the unadhered portion of the adhesive layer still had a sufficient adhering force to the semiconductor element.
  • the circuit tape with the film material was adhered to the semiconductor element at 300° C. for 10 minutes with a pressure of 100 kgf/cm 2 . Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding.
  • the connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co., Ltd. Chip coat 8107).
  • the semiconductor device shown in FIG. 6- 1 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • thermoplastic polyimide film made by Mitsui Toatsu Chemicals, Inc., Regulus PI-UAY, 100 ⁇ m thick
  • the film had a sufficient adhesive force to adhere to the circuit tape.
  • the semiconductor element with the film material was adhered to the circuit tape at 250° C. for 10 minutes with a pressure of 20 kgf/cm 2 . Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by wire bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co., Ltd. Chip coat 8107). Finally, the semiconductor device shown in FIG. 6- 2 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • a film material composed of a three layer structure having two different kinds of adhesive layers was obtained by applying a fluorine-containing polyimide (a reactant of hexafluorobisphenol AF and bis(4-aminophenoxyphenyl) hexafluoropropane, glass transition temperature 260° C.) onto one surface of a polyimide film (made by Ube Kosan Co. Ltd., SGA, 50 ⁇ m thick) to a thickness of 50 ⁇ m, and a polyetheretherketone (a reactant of dihydroxy-naphthalene and difluorobenzophenone, glass transition temperature 154° C.) onto the other surface of the polyimide film to a thickness of 50 ⁇ m.
  • a fluorine-containing polyimide a reactant of hexafluorobisphenol AF and bis(4-aminophenoxyphenyl) hexafluoropropane, glass transition temperature 260° C.
  • a polyimide film made by U
  • the obtained film material was registered and adhered to the circuit tape using the adhesive layer having a lower glass transition temperature.
  • the adhesion condition was at 200° C. for one minute with a pressure of 30 kgf/cm 2 .
  • the adhesive layer of the film was composed of a thermoplastic resin, the adhesive layer had a sufficient adhering force to adhere to the semiconductor element.
  • the circuit tape with the film material was adhered to the semiconductor element at 300° C. for ten seconds with a pressure of 80 kgf/cm 2 .
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding.
  • the connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co. Ltd., Chip coat 8107).
  • the semiconductor device shown in FIG. 6- 3 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • a silicone adhesive agent (made by Shinetsu Chemical Co. Ltd., KE1820) was applied onto one surface of a silicone film (made by Toray Dow Corning Silicone Co. Ltd., JCR6126, 150 ⁇ m thick, press-fabrication) to a thickness of 20 ⁇ m. Then, the silicone film was registered and adhered to the circuit tape. The adhesion condition was at 150° C. for one minute with a pressure of 30 kgf/cm 2 . Furthermore, in order to adhere to the semiconductor element, the silicone adhesive agent (made by Shinetsu Chemical Co. Ltd., KE1820) was applied onto the other surface of the silicone film to a thickness of 20 ⁇ m, and the circuit tape attached with the film material was adhered to the semiconductor element.
  • the adhesion condition was at 200° C. for 30 seconds with a pressure of 20 kgf/cm 2 .
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding.
  • the connecting portion was encapsulated with a silicone encapsulant (made by Toray Dow Corning Silicone Co. Ltd., DA 6501).
  • the semiconductor device shown in FIG. 8 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • Porous polytetrafluoroethylene made by Japan Gore-tex Inc., 190 ⁇ m thick), both surfaces of which were applied with BT resin (Bismaleimide-Triazine resin), was registered and adhered to the circuit tape.
  • the adhesion condition was at 150° C. for one minute with a pressure of 30 kgf/cm 2 . Because the adhesive layer of the film was in a B stage condition (half-cured condition), the adhesive layer had a sufficient adhering force to adhere to semiconductor element.
  • the adhesion of the circuit tape with the film material to the semiconductor element was conducted at 200° C. for 2 minutes with a pressure of 70 kgf/cm 2 .
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding.
  • the connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd. RO21C).
  • the semiconductor device shown in FIG. 6- 1 was obtained by fixing the solder balls, which were connecting terminals with the mounting substrate, onto the circuit tape.
  • a sticky tape having a three layer structure (made by Teraoka Seisakusyo, Ltd., Tape No. 760, 145 ⁇ m thick, silicone adhesive agent was applied onto both surfaces of Kapton film (commercial name by Du Pont)) was registered and adhered to the circuit tape at room temperature for 5 seconds with a pressure of 50 kgf/cm 2 .
  • Kapton film commercial name by Du Pont
  • the film was stamped out into a designated shape using the long scale apparatus shown in FIG. 3, and the stamped film was adhered to the circuit tape continuously. Because the adhesive layer of the film was made of a sticky resin, the unadhered portion of the adhesive layer still had a sufficient adhering force to adhere to the semiconductor element.
  • the circuit tape with the film material was adhered to the semiconductor element at room temperature for 10 seconds with a pressure of 5 kgf/cm 2 . Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding.
  • the connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co. Ltd. TSJ 3150). Finally, the semiconductor device shown in FIG. 6- 2 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • a cohesive tape having a three layer structure (150 ⁇ m thick, butadiene adhesive agent was applied onto both surfaces of unwoven aramide cloth (100 ⁇ m thick)) was registered and adhered between semiconductor and circuit tape at room temperature for 5 seconds with a pressure of 50 kgf/cm 2 . Under the above condition, some correction of the registration was possible, because the adhesive layer was still in a cohesive condition. Then, the adhesive layer of the film was cured at 180° C. for 60 minutes in a constant temperature bath to form a connecting state having a three dimensional crosslinking structure, because the adhesive layer was made of a cohesive resin.
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding.
  • the connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd. TSJ 3150).
  • the semiconductor device shown in FIG. 6- 3 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • a polyamic acid was prepared by reacting an equivalent of benzophenone tetracarboxylic acid dianhydride (made by Wako Pure Chemicals) and bis(4(2-aminophenoxyphenyl)ether) (synthetic chemical) at 5° C. in dimethylacetamide. Then, the reactant was heated at 250° C. to obtain polyimide.
  • the obtained polyimide 100 g was mixed with 4,4′-glycidyl-3,3′, 5,5′-tetramethylbiphenylether (made by Yuka Shell) 19.5 g phenol novolac (made by Meiwa Kasei) 10.6 g, and triphenyliphosphate (made by Wako Pure Chemicals) 0.2 g as a catalyst in dimethylacetamide to obtain a varnish containing a non-volatile component of 20% by weight. A film 100 ⁇ m thick was prepared with the obtained varnish.
  • the prepared film was registered and adhered to the circuit tape.
  • the adhesion condition was at 170° C. for ten seconds with a pressure of 30 kgf/cm 2 .
  • the unadhered portion of the adhesive layer had a sufficient adhering force to adhere with semiconductor element.
  • the adhesion of the circuit tape with the film material to the semiconductor element was conducted at 200° C. for one minute with a pressure of 30 kgf/cm 2 .
  • a post-curing was performed at 200° C. for 60 minutes in a constant temperature bath. Then, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding.
  • the connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd. RC021C).
  • an epoxy encapsulant made by Hitachi Chemical Co., Ltd. RC021C.
  • a film having a three layer structure was prepared by applying the varnish obtained in the embodiment 12 onto the one surface of polyimide film (made by Ube Kosan Co. Ltd., SGA, 50 ⁇ m thick) to a thickness of 20 ⁇ m (thermosetting resin component), and the fluorine-containing polyimide, i.e. the varnish prepared in the embodiment 7, (the reactant of hexafluorobisphenol AF and bis(4-aminophenoxyphenyl) hexafluoropropane, with a glass transition temperature of 260° C.) was applied onto the other surface of the polyimide film to a thickness of 10 ⁇ m (thermoplastic resin component).
  • the film was registered and adhered to the circuit tape at the surface where the thermosetting resin component was applied.
  • the adhesion condition was at 170° C. for 10 seconds with a pressure of 30 kgf/cm 2 .
  • a post-curing was performed at 200° C. for 60 minutes in a constant temperature bath.
  • the semiconductor element was adhered to the surface where the thermoplastic resin component was applied.
  • the adhesion condition was at 350° C. for 2 seconds with a pressure of 80 kgf/cm 2 .
  • connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding.
  • the connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo chip coat 8107).
  • the semiconductor device shown in FIG. 6- 2 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • An elastomer of 150 ⁇ m thickness was formed by registering silicone resin (made by Toray Dow Corning Silicone Co. Ltd., JCR 6126) with the circuit tape and printing using metal masks. After the formation, post-curing was performed at 150° C. for 60 minutes in a constant temperature bath. Then, the flatness of the elastomer was determined using a laser film thickness measuring apparatus. A silicone adhesive agent (made by Sinetsu Chemical Co. Ltd., KE 1820) was applied onto the surface of the elastomer a thickness of 20 ⁇ m as an adhesive layer for causing the semiconductor element to adhere to the circuit tape having the elastomer, and the circuit tape was registered and adhered to the semiconductor element.
  • silicone resin made by Toray Dow Corning Silicone Co. Ltd., JCR 6126
  • post-curing was performed at 150° C. for 60 minutes in a constant temperature bath. Then, the flatness of the elastomer was determined using a laser film thickness measuring apparatus.
  • a silicone adhesive agent
  • the adhesion was carried out at 150° C. for one minute with a pressure of 30 kgf/cm 2 . Then, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone, TSJ 3150). Finally, the semiconductor device shown in FIG. 6- 1 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • a film having a three layer structure was prepared by applying a thermoplastic resin (polyamide 12, m.p. 175° C.) having a melting point equal to or lower than 200° C. onto both surfaces of a polyimide film (made by Ube Kosan Co.
  • a thermoplastic resin polyamide 12, m.p. 175° C.
  • a melting point equal to or lower than 200° C.
  • a film having a three layer structure was prepared by applying an epoxy resin (made by Hitachi Chemical Co., Ltd., RO21C) having a high modulus of elasticity at room temperature onto both surfaces of a polyimide film (made by Ube Kosan Co. Ltd., SGA) as adhesive layers (20 ⁇ m thick).
  • the film having the three layer structure was used to prepare a semiconductor device by the same method as the embodiment 1, and the reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the embodiment 1.
  • Reflow test condition Pretreatment: 85° C./85% RH, 48 hours, Water absorption 240° C. ⁇ 3 times, Infrared oven.
  • a semiconductor device wherein tape material having a circuit layer and a semiconductor element are electrically connected, an external terminal for effecting electrical connection with the mounting substrate is provided on the circuit tape, and a film material is used as the material for bonding the circuit tape and the semiconductor element in an insulating manner, resulting in a semiconductor device which is superior in anti-reflow property due to the use of the film material for the adhesion, of which the modulus of elasticity in the reflow temperature range is at least 1 MPa.
  • a manufacturing method is also provided which is superior in mass productivity by using a film material at a portion for buffering thermal stress generated by a difference in thermal expansion of the semiconductor element and the mounting substrate.
  • the film material is superior in flatness, and a high and low difference within 5 ⁇ m can be ensured for a thickness of 150 ⁇ m, and so a manufacturing method which is superior in workability can be provided.
  • the connection reliability of both the lead portion which electrically connects the circuit tape and the semiconductor element, and the bump which electrically connects the semiconductor device and the mounting substrate can be satisfied simultaneously in a temperature cycling test.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Adhesive Tapes (AREA)
  • Adhesives Or Adhesive Processes (AREA)

Abstract

A semiconductor device having a superior connection reliability is obtained by providing a buffer body for absorbing the difference of thermal expansion between the mounting substrate and the semiconductor element in a semiconductor package structure, even if an organic material is used for the mounting substrate. A film material is used as the body for buffering the thermal stress generated by the difference in thermal expansion between the mounting substrate and the semiconductor element. The film material has modulus of elasticity of at least 1 MPa in the reflow temperature range (200-250° C.).

Description

  • This application is a Continuation application of application Ser. No. 09/493,208, filed Jan. 28, 2000, which is a Divisional application of application Ser. No. 08/857,674, filed May 16, 1997.[0001]
    • BACKGROUND OF THE INVENTION
  • The present invention relates to a circuit tape, a semiconductor device, and a method of manufacturing the same, which are superior in electrical characteristics, mounting reliability, and assembling easiness, and are responsive to the requirements for high density mounting, multipins mounting, and fast transmittance. [0002]
  • Currently, in the continuing effort to improve electronic devices to provide high performance, the demand for high integration and high density mounting of semiconductor elements has become strong. Therefore, semiconductor elements have been improved to achieve high integration and high performance, such as in LSI, VLSI, and ULSI devices, and there has been increase in the capacity, the number of pins, the speed, and power consumption thereof. In responding to such advances, the package structure of the semiconductor device for multipins has been changed from a structure, in which connecting terminals are provided at two sides of the semiconductor element, to an advanced structure, in which the connecting terminals are provided at all four sides of the semiconductor element. Furthermore, in order to respond to increasing the number of pins, a grid array structure has come to be used in practice. The grid array structure is a structure of a semiconductor element, in which the connecting terminals are provided in a grid array over the entire mounting surface of the semiconductor element by using a multilayer carrier substrate. The grid array structure includes a ball grid array structure (BGA), which has a shortened connecting terminal length in order to make fast signal transmission possible. The ball type structure of the connecting terminal increases the width of its conductor; therefore, the ball structure is also effective in decreasing inductance. Currently, in order to respond to the requirement for fast signal transmission, organic materials haying a relatively low dielectric constant have been investigated for use in the multilayer carrier substrate. However, the organic materials have generally a larger thermal expansion coefficient than the semiconductor element, and so thermal stress generated by the difference in thermal expansion becomes a problem from the point of view of connection reliability, and so on. Recently, a structure which does not use a carrier substrate has been proposed for the BGA package. [0003]
  • More particularly, a new semiconductor element package structure has been disclosed (U.S. Pat. No. 5,148,265), in which the connection reliability is improved by using an elastomer material having a low modulus of elasticity for reducing the thermal stress generated by the difference in thermal expansion between the semiconductor element and the mounting substrate. The proposed package structure uses a circuit tape composed of a polyimide and the like, instead of a carrier substrate, for electrically connecting the semiconductor element and the mounting substrate. Therefore, the electrical connections between the semiconductor element and the circuit tape are effected by a wire bonding method or a bonding connection with leads, and the circuit tape and the mounting substrate are electrically connected by soldering ball terminals. As the elastomer material of the prior art, a silicone material is generally used since this is a material having a low modulus of elasticity and a superior heat resistance. As a general method for forming a stress buffer layer with a silicone material, the steps of printing an uncured liquid resin on the circuit tape using masks, and subsequently, curing the printed resin, are generally used. However, the above method has problems, such as a difficulty in maintaining the flatness of the buffer layer obtained by the printing, and the complexity of the printing process, which requires a long time for the printing, is disadvantageous. Accordingly, the above method is not suitable for a mass-production process, and so the problems which undesirably affect the assembling yield and reliability of mounting caused by the difficulty in maintaining the flatness of the buffer layer are yet to be solved. [0004]
    • SUMMARY OF THE INVENTION
  • One of the objects of the present invention is to provide a method of obtaining a stress buffer layer which is superior in flatness by using a film material as the elastomer material for reducing the thermal stress in the semiconductor devices, thereby obtaining semiconductor devices which are superior in mass productivity. [0005]
  • In order to realize the above object, the present invention provides the following measures. [0006]
  • The measures can be achieved by providing a semiconductor device comprising a circuit tape having a pattern layer connected electrically to a semiconductor element, an external terminal provided on the circuit tape for electrically connecting the circuit tape to a mounting substrate, and film material for causing the circuit tape to adhere to the semiconductor element while maintaining an insulation condition between the circuit tape and the semiconductor element, wherein the film material for effecting the adhering has a physical property such that the modulus of elasticity of the film material in the temperature range of a solder reflow condition for mounting (200-250° C.) is at least 1 MPa. [0007]
  • The above film material for effecting the adhering is passed through a process for forming an external terminal, such as a solder ball and the like, for connecting the mounting substrate and the circuit tape, or a solder reflow process for mounting the semiconductor element of the present invention onto a mounting substrate in the manufacturing process of the semiconductor devices The reflow temperature is generally a high temperature in the range of 200-250° C. Therefore, if the semiconductor device contains moisture, the moisture evaporates during the heat treatment, and the film material swells due to the vapor pressure of the moisture. When the swelling exceeds a threshold value, a foaming phenomenon is generated, and defects, such as void formation, delamination, and the like, are generated. Therefore, the film material to be used is required to have as low a moisture absorption rate as possible and a high modulus of elasticity in the range of the reflow temperature. In accordance with the present invention, various film materials have been studied, and it was found that the adhesive materials having a modulus of elasticity in the temperature range of a reflow process of at least 1 MPa had superior reflow characteristics. Several examples of the temperature dependence of the modulus of elasticity of the material are shown in FIG. 1. [0008]
  • Furthermore, it was found that when materials, of which the modulus of elasticity in the temperature range of the mounting reflow condition was maintained at least at 1 MPa, were used, a preferable result in the anti-reflow characteristics could be obtained. The amount of swelling depends on the ratio of the vapor pressure and the modulus of elasticity, and the higher the modulus of elasticity is, the less will be the amount of swelling. The foaming phenomenon is generated when the amount of swelling exceeds the break elongation, one of the mechanical properties of the material. Furthermore, the modulus of elasticity correlates with the mechanical strength of the adhesive film material, and generally, the higher the modulus of elasticity is, the greater will be the tendency to increase the break stress and break elongation. Therefore, by using a material having a high modulus of elasticity in the range of the reflow temperature, the reflow characteristics can be improved as to both the swelling amount and the mechanical characteristics. In the above case, the adhesive film material may be either a thermosetting resin or a thermoplastic resin. [0009]
  • The adhesive layer is sometimes composed of either sticky adhesive agents or sticky-cohesive adhesive agents, in addition to the adhesive agents made of the above material. In order to maintain the modulus of elasticity at least at 1 MPa in the temperature range of the reflow process, the thermoplastic resin preferably has a glass transition temperature, i.e. a changing point of modulus of elasticity, which is higher then the temperature range (200-250° C.) of the reflow process. The thermosetting resin is required to have a chemical or physical crosslinking structure to a certain degree at a temperature in the rubber region, which is higher than the glass transition temperature. That is, the modulus of elasticity in the rubber region is generally proportional to the crosslinking density, and the crosslinking density must be increased in order to increase the modulus of elasticity. The film material is desirably composed of a resin having a low modulus of elasticity which is at the utmost 4000 MPa at room temperature, in order to operate as a stress buffer layer. [0010]
  • As one of characteristics of a film material, the coefficient of moisture absorption at 85° C./85% RH for 168 hours is desirably, at the utmost, 3% in view of the reflow characteristics. As the film material, materials having a low modulus of elasticity, except for a silicone material, can be used. The structure of the film material is not restricted to a homogeneous structure composed of an adhesive agent component, but also, for instance, a three layer structure having adhesive layers at both surfaces of a supporter, respectively, or a structure in which the adhesive agent is impregnated into a porous supporter, can be used. As shapes of the film, various shapes manufactured by stamping, a mesh-like shape, and the like can be used. The mesh-like shape is effective in improving the anti-reflow property at the moisture absorbing time, because the adhesion area can be decreased. [0011]
  • In the case of a multilayer structure represented by a three layer structure, the supporter and the adhesive layer can be composed of a combination of at least two kinds of the above adhesive agents, the sticky adhesive agents, the sticky-cohesive adhesive agents, and the like. The adhesive layer is located at each of both of the surfaces of the supporter, and each adhesive layer can be formed of a different kind of material from the other. For instance, a combination is usable in which a thermosetting resin having a high fluidity is used in order to flatten or eliminate the unevenness of the pattern layer of the circuit tape side, and a thermoplastic resin, which can be adhered in a short time at a high temperature, is used at the opposite flat portion for adhering to the semiconductor element. [0012]
  • A set of schematic illustrations indicating a flow of a general fabrication process for the manufacture of semiconductor devices, according to the present invention, is shown in FIG. 2. [0013]
  • The process can be divided into three representative sections. The first one, including STEPS [0014] 1-5 (FIG. 2a), is a method for fabricating a semiconductor element comprising (1) the step 1 of applying an adhesive film to the tape having a pattern layer, (2) the step 2 of adhering the tape having a pattern layer to the semiconductor element by means of the adhesive film while maintaining an insulating condition therebetween, (3) the step 3 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (4) the step 4 of sealing the electrically connected portion with an insulating agent, and (5) the step 5 of forming an external terminal on the tape for connection to the mounting substrate.
  • The above method is effective in improving the processability, because the circuit tape and the film material can be handled in the manner of a reel to reel process, as will be explained later. [0015]
  • The second one, including STEPS [0016] 6-10, (FIG. 2b), is a method for fabricating a semiconductor element comprising (1) the step 6 of applying an adhesive film to the semiconductor element, (2) the step 7 of adhering the tape having a pattern layer to the semiconductor element by means of the adhesive film while maintaining an insulating condition therebetween, (3) the step 8 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (4) the step 9 of sealing the electrically connected portion with an insulating agent, and (5) the step 10 of forming an external terminal on the tape for connection to the mounting substrate.
  • The above method is effective in improving the production yield of the semiconductor element itself. In accordance with the method, the stress buffer layer can be formed on the semiconductor element at the wafer stage condition. [0017]
  • The third one, including STEPS [0018] 11-14, (FIG. 2c), is a method of fabricating a semiconductor clement comprising (1) the step 11 of setting the tape having the pattern layer in registration and adhering the tape to the semiconductor element using the adhesive film simultaneously with maintaining an insulating condition therebetween, (2) the step 12 of electrically connecting the pattern layer formed on the tape and the pad on the semiconductor element, (3) the step 13 of sealing the electrically connected portion with an insulating agent, and (4) the step 14 of forming an external terminal on the tape for connection to the mounting substrate.
  • The above method is effective in shortening the manufacturing time, because the number of steps in the process can be decreased. [0019]
  • These methods essentially comprise the following steps. The adhesive film material of the present invention is provided between the tape material having the pattern layer and the semiconductor element by adopting a certain method, and the tape material and the semiconductor element are bonded together simultaneously or sequentially under conditions of designated temperature, pressure, and time. Subsequently, the pattern layer on the tape is electrically connected to the connecting pad of the semiconductor element. As examples of a connecting method using a connecting lead previously formed on the circuit tape as a circuit for connection with the semiconductor element, any one of a single point bonding method, a gang bonding method, and the like can be used. [0020]
  • As another example of a method for connection, a method in which the pattern layer and the semiconductor element are connected with wire bonding can be adopted. [0021]
  • Then, the connecting portion is encapsulated with an insulating material, and finally the external terminals, which are electrically connected with the mounting substrate, are formed on the circuit tape. As an external terminal, a solder ball is generally used, and most of the solder ball is formed by plating. Metals which may be used for the plating are gold, nickel, copper, solder, and the like. [0022]
  • In order to improve the mass productivity in the manufacturing process, the process for integrating the adhesive film material with the circuit tape previously as shown in FIG. 2[0023] a is important.
  • As a general method for the above process, a method comprising the steps of transferring the tape, whereon the pattern is formed, by a long reel apparatus, stamping out the adhesive film into a designated shape, and adhering the adhesive film of the designated shape onto the circuit tape, as shown in FIG. 3, is effective for mass production. When the adhesive film is made of a thermosetting resin, the adhesive film can be made to adhere to the circuit tape while in an uncured A stage or a half-cured B stage. The resin is then further cured to a condition of a final-cured C stage during the step of adhering the obtained circuit tape, to which the adhesive film is attached, to the semiconductor element. Otherwise, if the adhesive agent reaches the condition of the final cured C stage during the time that the adhesive film is adhered to the circuit tape, sometimes, an adhesive layer is newly formed on the cured film portion. [0024]
  • As a method for forming the adhesive layer, an application method, a film adhering method, and the like are generally used. The adhesive component is desirably not sticky at room temperature, but if sticky, a mold releasing paper and the like is used. [0025]
  • FIG. 4 shows an example of the composition of a circuit tape to which an adhesive film is attached. The circuit tape can be adhered to the semiconductor element. If a thermosetting resin is used for the adhesive layer at the circuit tape side and a thermoplastic resin is used for the adhesive layer at the side adhered to the semiconductor, the circuit tape having the adhesive ability shown in FIG. 4 can be provided readily. [0026]
  • When the adhesive layer is composed of a thermoplastic, sticky, or cohesive material, the conditions for the two steps to adhere to the circuit tape and to the semiconductor element can be set as quite the same with respect to each other. As opposed to the case of a thermosetting resin, the curing reaction does not need to be controlled at the intermediate stages, and so a manufacturing process superior in workability can be provided. [0027]
  • When the adhesive layer is composed of a sticky or cohesive material, the material is advantageous from the point of view of avoiding warpage of the semiconductor element, because the material can be adhered at room temperature. When the adhesive film is initially combined with the circuit tape, the semiconductor element is easily registered at the time of adhering to the circuit tape. Accordingly, the jigs of the adhering apparatus can be simplified, and the method becomes advantageous for mass production. [0028]
  • With the semiconductor device relating to the present invention, the unevenness of the pattern circuit on the circuit tape is sometimes eliminated by filling spaces with the adhesive layer of the film. In this case, the suitability of the adhesive layer for the filling can be confirmed at the step of combining the circuit tape and the semiconductor element. Therefore, an unsuitable adhesive layer can be eliminated before joining the circuit tape to the semiconductor element, a loss of the semiconductor can be avoided, and an advantageous increase in the production yield can be attained. [0029]
  • Typical examples of a thermosetting resin and a thermoplastic resin for the adhesive component of the film materials are as follows: epoxy resin, polyimide resin, polyamide resin, cyanate resin, isocyanate resin, fluorine-containing resin, silicon-containing resin, urethane resin, acrylate resin, styrene resin, maleimide resin, phenolic resin, unsaturated polyester resin, diallyl phthalate resin, cyanamide resin, polybutadiene resin, polyamideimide resin, polyether resin, polysulfone resin, polyester resin, polyolefine resin, polystyrene resin, polyvinyl chloride, transpolyisoprene resin, polyacetal resin, polycarbonate resin, polyphenylene ether resin, polyphenylene sulfide resin, polyacrylate resin, polyether imide resin, polyether sulfone resin, polyether ketone resin, liquid crystalline polyester resin, polyallylether nitrile resin, polybenzoimidazole resin, various kinds of polymer blend, and polymer alloys, and the like. [0030]
  • The above examples of a thermosetting resin and a thermoplastic resin involve materials having an adhesiveness resulting from melting or softening of the material by heating. On the contrary, the sticky or cohesive materials are materials having an adhesiveness produced by pressurizing. [0031]
  • Typical examples of the sticky and cohesive materials are as follows: various rubber groups, such as the silicone group, the butadiene group and the isoprene group, acrylate groups, polyvinyl ether groups, and the like. The cohesive material includes a room temperature curing type, a type cured by heat, ultraviolet ray irradiation, electron beam irradiation, and the like, a type cured by concurrent use of an accelerator, and the like. The room temperature curing type includes a moisture-reactive type which reacts in the presence of moisture in the atmosphere, a photo-reactive type which contains a photo-initiator, and an anti-oxygen material which contains peroxide, and the like. The thermosetting resin generally includes a crosslinking agent, such as thiurum groups, phenol groups, isocyanate groups, and the like, and adhesive components are crosslinked three-dimensionally to form the adhesive layer at a designated temperature. [0032]
  • The material of the type cured by ultraviolet ray irradiation, or electron beam irradiation, contains various photo-initiators. The material of the type cured by concurrent use of an accelerator includes a solution containing a reaction accelerator and a crosslinking agent, which are applied onto the surface of the sticky layer, wherein the adhesive layer is finally formed by mixing the above two agents with a contact pressure and reacting the two agents sequentially. For the cohesive agent of the present invention, a thermosetting resin is relatively preferable Using a thermosetting resin, a semiconductor device, which is superior in mass productivity and reliability, can be provided by the method comprising the steps of registering the circuit tape and the semiconductor element at room temperature, bringing the wiring tape and the semiconductor element into contact to form a set, and elevating the temperature of a plurality of such sets to a designated degree simultaneously in a container, such as a constant temperature bath, for producing a curing reaction to ensure the adhesive strength. [0033]
  • The modulus of elasticity of the adhesive film material is preferably high at a high temperature region in view of the reflow characteristics, but as low as possible at room temperature. In this regard, the semiconductor element and the mounting substrate generally have different thermal expansion coefficients from each other, and a thermal stress is generated, when the mounting is performed, at the external terminal, which is composed of a solder ball and the like. Then, the reliability of the connection becomes remarkably important. [0034]
  • If the modulus of elasticity of the adhesive film existing between the semiconductor element and the mounting substrate is low, the region of the adhesive layer becomes a stress buffer layer, and this is advantageous from the point of view of the connection reliability. The modulus of elasticity at room temperature is desirably, at the utmost, 4000 MPa. More preferably, the modulus of elasticity in the entire range of the heat cycling test (−55° C.-150° C.) is, at the utmost, 2000 MPa. As a material which has a high modulus of elasticity at a high temperature and a relatively low elastic modulus in a range of a low temperature including room temperature, sometimes silicone group materials are used. A film material comprising a silicone group material is one of the significantly important materials of the present invention. [0035]
  • However, film materials, other than the silicone group material having the above characteristics, are advantageous in comparison with the silicone group material. That is, because of the weak cohesive energy of silicon, cyclic low molecular weight silicone group compounds are gradually decomposed thermally during a long heat treatment, such as during storing at a high temperature (for instance, at least 150° C.), and this sometimes becomes a cause of contamination to the environment. [0036]
  • The composition of the film material of the present invention is not only a homogeneous structure composed of the adhesive agent components, but also may be a three layer structure, such as a supporter having adhesive agent layers at both surfaces for instance, and a structure in which the adhesive agent is impregnated into a porous supporter. As the supporter of the film material, films or a porous material made of polyimide, epoxy, polyethylene terephthalate, cellurose, acetate, fluorine-containing polymer, and the like can be used. [0037]
  • As the shape of the film, the various shapes obtainable by stamping out, a mesh-like shape, and the like can be used. The mesh-like shape is effective in improving the anti-reflow properly at the moisture absorbing time, because the adhesion area can be decreased. The three layer structure can be controlled to an arbitrary thickness and as to the kind of the adhesive layer provided at both the surfaces of the supporter, and the fluidity of the adhesive layer at the time of adhesion can be readily controlled. Furthermore, the presence of an insulating layer is ensured by the supporter located between the adhesive layers. [0038]
  • The value of vapor pressure of the adhesive material by moisture absorption at the time of reflow can be maintained at a low value by using the material, of which the film material has a coefficient of moisture absorption at 85° C./85% RH of, at the utmost, 3%, and so preferable reflow characteristics can be obtained. [0039]
  • The tape having a pattern layer is generally composed of a flexible circuit substrate. That is, a polyimide group material serving as the insulating layer, an epoxy group material, a polyimide group material, a phenolic group material, a polyamide group material, and the like are used as the adhesive layer with the conductor. Generally, copper is used as the conductor. As the wiring circuit, the copper is sometimes coated with nickel, gold plating, and the like. As the flexible circuit substrate, a material, which does not use the adhesive layer with the conductor, but uses a copper layer formed directly onto the polyimide insulating layer, is sometimes used. [0040]
  • The tape having a pattern layer is sometimes composed of a multilayer wiring structure. In this case, a voltage layer, a ground layer, and so on in addition to the signal layer can be formed in the circuit tape, and so a semiconductor device which is superior in electric characteristics can be provided. [0041]
  • Two typical arrangements of the pad terminal on the semiconductor element for electrically connecting the tape material having the pattern layer with the semiconductor element are as follows. [0042]
  • The one is a peripheral pad arrangement as shown in FIG. 5. In this case, there are different types of structure for the arrangement of the external terminal of the semiconductor device, as shown in FIGS. [0043] 6-1, 6-2, 6-3. That is, the case wherein the external terminals are located under the semiconductor element (Fan In type, FIG. 6 1), the case wherein the external terminals are located outside the semiconductor element (Fan Out type, FIG. 6-2), and the case wherein the external terminals are located at both under and outside the semiconductor element (Fan In/Out type, FIG. 6-3) can be used.
  • Another example of the pad arrangement is the central arrangement shown in FIG. 7. In this case, the semiconductor device is composed of the structure shown in FIG. 8. [0044]
  • In accordance with the present invention, the semiconductor element is a device wherein IC, LSI, and the like, such as memories, logic devices, gate arrays, customs, power transistors, and the like, are formed on a wafer comprising semiconductor materials such as Si, GaAs, and the like, and the device has terminals for connecting to a lead, bump, and the like. [0045]
  • In accordance with the present invention, the semiconductor device comprising a tape having a pattern layer is used as an interconnection between the semiconductor element and the mounting substrate, which is superior in anti-reflow characteristics and connection reliability, may be provided by using a film material having a modulus of elasticity of at least 1 MPa in the reflow temperature region (200-250° C.), which is a high temperature region, as the adhesive material while maintaining the insulation between the circuit tape and the semiconductor element. By using such a film material, a manufacturing method which is superior in mass productivity to the conventional printing methods can be provided[0046]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • These and other objects, features and advantages of the present invention will be understood more clearly from the following detailed description with reference to the accompanying drawings, wherein: [0047]
  • FIG. 1 is a graph indicating temperature dependency of the modulus of elasticity of materials; [0048]
  • FIGS. 2[0049] a, 2 b, and 2 c are schematic illustrations indicating the manufacturing process of the semiconductor device of the present invention, wherein FIG. 2a shows a method wherein the film is adhered previously to the circuit tape, FIG. 2b shows a method wherein the film is adhered previously to the semiconductor element, and FIG. 2c shows a method wherein the circuit tape and the semiconductor element are adhered together simultaneously via the film;
  • FIG. 3 is a schematic diagram indicating the continuous process for adhering the film using a long reel; [0050]
  • FIG. 4 is a schematic diagram showing a cross section indicating the composition of a circuit tape having a film with an adhesive agent layer; [0051]
  • FIG. 5 is a schematic diagram of a semiconductor element having peripheral pads; [0052]
  • FIGS. [0053] 6-1, 6-2, 6-3 are schematic cross sections showing the structure of semiconductor devices using the semiconductor elements having the peripheral pads;
  • FIG. 7 is a schematic diagram showing a semiconductor element having pads located at the center of the element; and [0054]
  • FIG. 8 is a schematic cross section showing the structure of a semiconductor device using a semiconductor element having pads located at the center of the element.[0055]
    • DESCRIPTION OF THE PREFERRED EMBODIMENTS EMBODIMENT 1
  • An epoxy group adhesive film (made by Hitachi Chemical Co., Ltd., AS 3000, 50 μm thick) was registered, placed, and adhered between a semiconductor element and circuit tape at 170° C. for one minute with a pressure of 50 kgf/cm[0056] 2, and was then post-cured at 180° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd., RC021C). Finally, the semiconductor device shown in FIG. 6-1 was obtained by fixing the solder balls, which were connecting terminals with the mounting substrate, onto the circuit tape.
  • After absorbing moisture in a constant temperature bath at 85° C./85% RH for 168 hours, the obtained semiconductor device was set in an infrared reflow apparatus with a maximum temperature of 245° C., and it was confirmed whether the semiconductor device exhibited defects, such as delamination and voids by foaming the adhesive layer. Furthermore, the connection reliability between the lead of the semiconductor device and the solder bump was confirmed. In this case, a woven glass-epoxy copper clad laminate FR-4 (made by Hitachi Chemical Co., Ltd., MCI-E-67) was used as the mounting substrate. The reliability was evaluated by performing a thermal cycling test (−55° C.← →150° C., 1000 times). [0057]
    • EMBODIMENT 2
  • A film material having a three layer structure was obtained by applying an adhesive agent (made by Hitachi Chemical Co. Ltd., DF335), composed of a die bonding film material, onto both surfaces of a polyimide film (made by Ube Kosan Co., Ltd., SGA, 50 μm thick) to a thickness of 50 μm. The obtained film material was registered and adhered to circuit tape at 170° C. for five seconds with a pressure of 30 kgf/cm[0058] 2. Under the above conditions, the unadhered adhesive layer exhibited a sufficient adhesive force to adhere to the semiconductor element. The circuit tape attached with the film material was adhered to the semiconductor element at 200° C. for one minute with a pressure of 30 kgf/cm2, and was then post-cured at 200° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd., RC021C). Finally, the semiconductor device shown in FIG. 6-2 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0059] embodiment 1.
    • EMBODIMENT 3
  • A low elastic adhesive film composed of an epoxy resin and acrylic rubber (made by Hitachi Chemical Co. Ltd., trial product, 150 μm thick) was registered, placed, and adhered between the semiconductor element and the circuit tape at 180° C. for 30 seconds with a pressure of 100 kgf/cm[0060] 2 , and was then post-cured at 180° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by wire bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd., TSJ 3150) Finally, the semiconductor device shown in FIG. 6-3 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0061] embodiment 1.
    • EMBODIMENT 4
  • A film material having a three layer structure was obtained by adhering a low elastic adhesive film composed of epoxy resin and acrylic rubber (made by Hitachi Chemical Co. Ltd., trial product, 50 μm thick) to both surfaces of a woven glass-epoxy resin laminate (obtained by eliminating a copper cladding by etching from both surfaces of MCL-E-679 made by Hitachi Chemical Co., Ltd.). The film material was registered, placed, and adhered between the semiconductor element and the circuit tape at 200° C. for 20 seconds with a pressure of 80 kgf/cm[0062] 2, and was then post-cured at 180° C. for 60 minutes in a constant temperature bath. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd., TSJ 3153). Finally, the semiconductor device shown in FIG. 8 was obtained by filing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0063] embodiment 1.
    • EMBODIMENT 5
  • A LOC (Lead on chip) Film (made by Hitachi Chemical Co. Ltd., HM122U, 100 μm thick) having a three layer structure was registered and adhered to the circuit tape at 300° C. for 2 seconds with pressure of 150 kgf/cm[0064] 2. In the adhering process, the film was stamped out into a designated shape using the long scale apparatus shown in FIG. 3, and the stamped film was adhered to the circuit tape continuously. Because the adhesive layer of the film was made of a thermoplastic resin, the unadhered portion of the adhesive layer still had a sufficient adhering force to the semiconductor element.
  • The circuit tape with the film material was adhered to the semiconductor element at 300° C. for 10 minutes with a pressure of 100 kgf/cm[0065] 2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co., Ltd. Chip coat 8107). Finally, the semiconductor device shown in FIG. 6-1 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0066] embodiment 1.
    • EMBODIMENT 6
  • A thermoplastic polyimide film (made by Mitsui Toatsu Chemicals, Inc., Regulus PI-UAY, 100 μm thick) was registered and adhered to the semiconductor element at 250° C. for 2 seconds with a pressure of 30 kgf/cm[0067] 2. The film had a sufficient adhesive force to adhere to the circuit tape.
  • The semiconductor element with the film material was adhered to the circuit tape at 250° C. for 10 minutes with a pressure of 20 kgf/cm[0068] 2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by wire bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co., Ltd. Chip coat 8107). Finally, the semiconductor device shown in FIG. 6-2 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0069] embodiment 1.
    • EMBODIMENT 7
  • A film material composed of a three layer structure having two different kinds of adhesive layers was obtained by applying a fluorine-containing polyimide (a reactant of hexafluorobisphenol AF and bis(4-aminophenoxyphenyl) hexafluoropropane, glass transition temperature 260° C.) onto one surface of a polyimide film (made by Ube Kosan Co. Ltd., SGA, 50 μm thick) to a thickness of 50 μm, and a polyetheretherketone (a reactant of dihydroxy-naphthalene and difluorobenzophenone, glass transition temperature 154° C.) onto the other surface of the polyimide film to a thickness of 50 μm. [0070]
  • The obtained film material was registered and adhered to the circuit tape using the adhesive layer having a lower glass transition temperature. The adhesion condition was at 200° C. for one minute with a pressure of 30 kgf/cm[0071] 2. Because the adhesive layer of the film was composed of a thermoplastic resin, the adhesive layer had a sufficient adhering force to adhere to the semiconductor element. The circuit tape with the film material was adhered to the semiconductor element at 300° C. for ten seconds with a pressure of 80 kgf/cm2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo Co. Ltd., Chip coat 8107). Finally, the semiconductor device shown in FIG. 6-3 was obtained by fixing the solder balls, which served as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0072] embodiment 1.
    • EMBODIMENT 8
  • A silicone adhesive agent (made by Shinetsu Chemical Co. Ltd., KE1820) was applied onto one surface of a silicone film (made by Toray Dow Corning Silicone Co. Ltd., JCR6126, 150 μm thick, press-fabrication) to a thickness of 20 μm. Then, the silicone film was registered and adhered to the circuit tape. The adhesion condition was at 150° C. for one minute with a pressure of 30 kgf/cm[0073] 2. Furthermore, in order to adhere to the semiconductor element, the silicone adhesive agent (made by Shinetsu Chemical Co. Ltd., KE1820) was applied onto the other surface of the silicone film to a thickness of 20 μm, and the circuit tape attached with the film material was adhered to the semiconductor element. The adhesion condition was at 200° C. for 30 seconds with a pressure of 20 kgf/cm2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toray Dow Corning Silicone Co. Ltd., DA 6501). Finally, the semiconductor device shown in FIG. 8 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0074] embodiment 1.
    • EMBODIMENT 9
  • Porous polytetrafluoroethylene (made by Japan Gore-tex Inc., 190 μm thick), both surfaces of which were applied with BT resin (Bismaleimide-Triazine resin), was registered and adhered to the circuit tape. The adhesion condition was at 150° C. for one minute with a pressure of 30 kgf/cm[0075] 2. Because the adhesive layer of the film was in a B stage condition (half-cured condition), the adhesive layer had a sufficient adhering force to adhere to semiconductor element. The adhesion of the circuit tape with the film material to the semiconductor element was conducted at 200° C. for 2 minutes with a pressure of 70 kgf/cm2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd. RO21C). Finally, the semiconductor device shown in FIG. 6-1 was obtained by fixing the solder balls, which were connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0076] embodiment 1.
    • EMBODIMENT 10
  • A sticky tape having a three layer structure (made by Teraoka Seisakusyo, Ltd., Tape No. 760, 145 μm thick, silicone adhesive agent was applied onto both surfaces of Kapton film (commercial name by Du Pont)) was registered and adhered to the circuit tape at room temperature for 5 seconds with a pressure of 50 kgf/cm[0077] 2. In the adhering process, the film was stamped out into a designated shape using the long scale apparatus shown in FIG. 3, and the stamped film was adhered to the circuit tape continuously. Because the adhesive layer of the film was made of a sticky resin, the unadhered portion of the adhesive layer still had a sufficient adhering force to adhere to the semiconductor element.
  • The circuit tape with the film material was adhered to the semiconductor element at room temperature for 10 seconds with a pressure of 5 kgf/cm[0078] 2. Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co. Ltd. TSJ 3150). Finally, the semiconductor device shown in FIG. 6-2 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0079] embodiment 1.
    • EMBODIMENT 11
  • A cohesive tape having a three layer structure (150 μm thick, butadiene adhesive agent was applied onto both surfaces of unwoven aramide cloth (100 μm thick)) was registered and adhered between semiconductor and circuit tape at room temperature for 5 seconds with a pressure of 50 kgf/cm[0080] 2. Under the above condition, some correction of the registration was possible, because the adhesive layer was still in a cohesive condition. Then, the adhesive layer of the film was cured at 180° C. for 60 minutes in a constant temperature bath to form a connecting state having a three dimensional crosslinking structure, because the adhesive layer was made of a cohesive resin.
  • Subsequently, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by single point bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone Co., Ltd. TSJ 3150). Finally, the semiconductor device shown in FIG. 6-[0081] 3 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0082] embodiment 1.
    • EMBODIMENT 12
  • A polyamic acid was prepared by reacting an equivalent of benzophenone tetracarboxylic acid dianhydride (made by Wako Pure Chemicals) and bis(4(2-aminophenoxyphenyl)ether) (synthetic chemical) at 5° C. in dimethylacetamide. Then, the reactant was heated at 250° C. to obtain polyimide. The obtained polyimide 100 g was mixed with 4,4′-glycidyl-3,3′, 5,5′-tetramethylbiphenylether (made by Yuka Shell) 19.5 g phenol novolac (made by Meiwa Kasei) 10.6 g, and triphenyliphosphate (made by Wako Pure Chemicals) 0.2 g as a catalyst in dimethylacetamide to obtain a varnish containing a non-volatile component of 20% by weight. A [0083] film 100 μm thick was prepared with the obtained varnish.
  • The prepared film was registered and adhered to the circuit tape. The adhesion condition was at 170° C. for ten seconds with a pressure of 30 kgf/cm[0084] 2. Under the above conditions, the unadhered portion of the adhesive layer had a sufficient adhering force to adhere with semiconductor element. The adhesion of the circuit tape with the film material to the semiconductor element was conducted at 200° C. for one minute with a pressure of 30 kgf/cm2. Subsequently, a post-curing was performed at 200° C. for 60 minutes in a constant temperature bath. Then, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hitachi Chemical Co., Ltd. RC021C). Finally, the semiconductor device shown in FIG. 6-2 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0085] embodiment 1.
    • EMBODIMENT 13
  • A film having a three layer structure was prepared by applying the varnish obtained in the [0086] embodiment 12 onto the one surface of polyimide film (made by Ube Kosan Co. Ltd., SGA, 50 μm thick) to a thickness of 20 μm (thermosetting resin component), and the fluorine-containing polyimide, i.e. the varnish prepared in the embodiment 7, (the reactant of hexafluorobisphenol AF and bis(4-aminophenoxyphenyl) hexafluoropropane, with a glass transition temperature of 260° C.) was applied onto the other surface of the polyimide film to a thickness of 10 μm (thermoplastic resin component). The film was registered and adhered to the circuit tape at the surface where the thermosetting resin component was applied. The adhesion condition was at 170° C. for 10 seconds with a pressure of 30 kgf/cm2. Then, a post-curing was performed at 200° C. for 60 minutes in a constant temperature bath. Subsequently, the semiconductor element was adhered to the surface where the thermoplastic resin component was applied. The adhesion condition was at 350° C. for 2 seconds with a pressure of 80 kgf/cm2. Then, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with an epoxy encapsulant (made by Hokuriku Toryo chip coat 8107). Finally, the semiconductor device shown in FIG. 6-2 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0087] embodiment 1.
    • COMPARATIVE EXAMPLE 1
  • An elastomer of 150 μm thickness was formed by registering silicone resin (made by Toray Dow Corning Silicone Co. Ltd., JCR 6126) with the circuit tape and printing using metal masks. After the formation, post-curing was performed at 150° C. for 60 minutes in a constant temperature bath. Then, the flatness of the elastomer was determined using a laser film thickness measuring apparatus. A silicone adhesive agent (made by Sinetsu Chemical Co. Ltd., KE 1820) was applied onto the surface of the elastomer a thickness of 20 μm as an adhesive layer for causing the semiconductor element to adhere to the circuit tape having the elastomer, and the circuit tape was registered and adhered to the semiconductor element. The adhesion was carried out at 150° C. for one minute with a pressure of 30 kgf/cm[0088] 2. Then, connecting leads on the circuit tape were electrically connected to pads of the semiconductor element by gang bonding. The connecting portion was encapsulated with a silicone encapsulant (made by Toshiba Silicone, TSJ 3150). Finally, the semiconductor device shown in FIG. 6-1 was obtained by fixing the solder balls, which serve as connecting terminals with the mounting substrate, onto the circuit tape.
  • The reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the [0089] embodiment 1.
    • COMPARATIVE EXAMPLE 2
  • A film having a three layer structure was prepared by applying a thermoplastic resin ([0090] polyamide 12, m.p. 175° C.) having a melting point equal to or lower than 200° C. onto both surfaces of a polyimide film (made by Ube Kosan Co.
  • Ltd., SGA, 50 μm thick) as adhesive layers (30 μm thick). The film having the three layer structure was used to prepare a semiconductor device using the same method as the [0091] embodiment 1, and the reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the embodiment 1.
    • COMPARATIVE EXAMPLE 3
  • A film having a three layer structure was prepared by applying an epoxy resin (made by Hitachi Chemical Co., Ltd., RO21C) having a high modulus of elasticity at room temperature onto both surfaces of a polyimide film (made by Ube Kosan Co. Ltd., SGA) as adhesive layers (20 μm thick). The film having the three layer structure was used to prepare a semiconductor device by the same method as the [0092] embodiment 1, and the reflow characteristics and connection reliability of the lead and the solder bump of the obtained semiconductor device were confirmed by the same method as the embodiment 1.
    TABLE 1
    Elastic modulus
    (MPa)
    Adhesive Thermal cycling
    layers test(1000 cycles)
    Adhesive (average Lead open Bump open
    film of 200˜ Reflow failure failure
    (25° C.) 250° C.) test (%) (%)
    Emb.* 1 788 4.3 No void 0 0
    Emb. 2 5000 1.5 No void 0 0
    Emb. 3 960 3.6 No void 0 0
    Emb. 4 4190 3.6 No void 0 0
    Emb. 5 3750 13 No void 0 0
    Emb. 6 3500 100 No void 0 0
    Emb. 7 3500 2000, 15 No void 0 0
    Emb 8 10 2.5 No void 0 0
    Emb. 9 2000 100 No void 0 0
    Emb. 10 20 2.5 No void 0 0
    Emb. 11 30 3.5 No void 0 0
    Emb. 12 850 8.5 No void 0 0
    Emb. 13 3300 2000, 8.5 No void 0 0
    Com.1 10 2.5 No void 10 0
    Com. 2 1400 ˜0 Void 5 0
    Com. 3 11000 1100 No void 80 100
  • Flatness of the elastomer: High and low difference of comparative example 1 was 50 μm to thickness of 150 μm, and all other samples within 5μm. [0093]
  • Reflow test condition: Pretreatment: 85° C./85% RH, 48 hours, Water absorption 240° C.×3 times, Infrared oven. [0094]
  • In accordance with the present invention, a semiconductor device is provided, wherein tape material having a circuit layer and a semiconductor element are electrically connected, an external terminal for effecting electrical connection with the mounting substrate is provided on the circuit tape, and a film material is used as the material for bonding the circuit tape and the semiconductor element in an insulating manner, resulting in a semiconductor device which is superior in anti-reflow property due to the use of the film material for the adhesion, of which the modulus of elasticity in the reflow temperature range is at least 1 MPa. A manufacturing method is also provided which is superior in mass productivity by using a film material at a portion for buffering thermal stress generated by a difference in thermal expansion of the semiconductor element and the mounting substrate. [0095]
  • The film material is superior in flatness, and a high and low difference within 5 μm can be ensured for a thickness of 150 μm, and so a manufacturing method which is superior in workability can be provided. In accordance with the stress buffering effect of the film material, the connection reliability of both the lead portion which electrically connects the circuit tape and the semiconductor element, and the bump which electrically connects the semiconductor device and the mounting substrate can be satisfied simultaneously in a temperature cycling test. [0096]

Claims (24)

What is claimed is:
1. A circuit tape with an adhesive layer, for semiconductor devices, comprising:
a circuit tape having a base material made of a dielectric film, whereon a circuit is formed; and
an adhesive layer for connecting said circuit tape to a semiconductor element such that the circuit tape is insulated from the semiconductor element, wherein
an elastic modulus of said adhesive layer, in a range of mounting reflow temperature for mounting the semiconductor element onto a mounting substrate, is more than 1 MPa.
2. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein the elastic modulus of said adhesive layer, in the range of 200□-250□C, is more than 1 MPa.
3. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein said adhesive layer is composed of an adhesive film.
4. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 3, wherein said adhesive film includes a three-layer structure having a porous support layer and two adhesive layers which are respectively applied onto both sides of said porous support layer.
5. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 3, wherein said adhesive film includes a structure wherein an adhesive agent is impregnated into a porous support.
6. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 3, wherein an elastic modulus of said adhesive film at room temperature is equal to or less than 4000 MPa.
7. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein an elastic modulus of the adhesive layer at room temperature is lower than the elastic modulus of said adhesive layer in a temperature range of 200□-250□C.
8. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1 , wherein the adhesive layer has a layer of a thermoplastic resin, and the thermoplastic resin has a glass transition temperature greater than 250□C.
9. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein material of the adhesive layer has a coefficient of moisture absorption at 85□C/85% RH for 168 hours of, at most, 3%.
10. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein the adhesive layer includes a thermosetting resin closest to the circuit tape and a thermoplastic resin to be closest to the semiconductor element.
11. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 1, wherein the circuit tape has an uneven surface with space between portions of the circuit, and the adhesive layer fills in the spaces.
12. A circuit tape with an adhesive layer, for semiconductor devices, comprising:
an elongated circuit tape having a base material made of dielectric film, whereon circuits are formed; and
at least one adhesive film each adhered continuously to said circuit tape, each adhesive film having a size less than that of the elongated circuit tape.
13. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 12, wherein an elastic modulus of said adhesive film, in a range of mounting reflow temperature for mounting a semiconductor element onto a mounting substrate, is more than 1 MPa.
14. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 13, wherein an elastic modulus of said adhesive film, in the range of 200□-250□C, is more than 1 MPa.
15. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 12, wherein said adhesive film includes a three-layer structure having a support layer and two adhesive layers which are respectively applied onto both sides of said support layer.
16. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 12, wherein said adhesive film includes a structure wherein an adhesive agent is impregnated into a porous support.
17. A circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 13, wherein an elastic modulus of said adhesive film, at room temperature, is equal to or les s than 4000 MPa.
18. A method of manufacturing a circuit tape with an adhesive layer, for semiconductor devices, comprising the steps of:
transferring an elongated circuit tape, whereon a circuit is formed, from a first reel to a second reel;
punching out adhesive film of a size smaller than that of the elongated circuit tape; and
adhering continuously the punched-out adhesive film to said circuit tape, as the circuit tape is transferred from the first reel to the second reel, concurrently with the punching.
19. A method of manufacturing circuit tape with an adhesive layer, for semiconductor devices, as claimed in claim 18, wherein said punched-out adhesive film is punched out from an elongated adhesive film transferred from a first reel to a second reel.
20. Adhesive film for semiconductor devices, which is for adhering a semiconductor element to circuit tape, having an elastic modulus, in a range of mounting reflow temperature for mounting the semiconductor element onto a mounting substrate, of more than 1 MPa.
21. Adhesive film for semiconductor devices as claimed in claim 20, wherein said mounting reflow temperature is in a range of 200□C-250□C, said elastic modulus of the adhesive film, in the range of 200□C-250□C, being more than 1 MPa.
22. Adhesive film for semiconductor devices as claimed in claim 20, wherein said elastic modulus at room temperature is equal to or less than 4000 MPa.
23. Adhesive film for semiconductor devices as claimed in claim 20, wherein said adhesive film includes a three-layer structure having a support layer and two adhesive agent layers which are applied respectively onto both sides of said support layer.
24. Adhesive film for semiconductor devices as claimed in claim 20, wherein said adhesive film has a structure wherein an adhesive agent is impregnated into a porous support.
US10/138,485 1996-05-30 2002-05-06 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same Abandoned US20020160185A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US10/138,485 US20020160185A1 (en) 1996-05-30 2002-05-06 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US10/724,092 US7202570B2 (en) 1996-05-30 2003-12-01 Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
JP8-136159 1996-05-30
JP13615996A JP3195236B2 (en) 1996-05-30 1996-05-30 Wiring tape having adhesive film, semiconductor device and manufacturing method
US08/857,674 US6114753A (en) 1996-05-30 1997-05-16 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US49320800A 2000-01-28 2000-01-28
US10/138,485 US20020160185A1 (en) 1996-05-30 2002-05-06 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
US49320800A Continuation 1996-05-30 2000-01-28

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US10/724,092 Continuation US7202570B2 (en) 1996-05-30 2003-12-01 Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

Publications (1)

Publication Number Publication Date
US20020160185A1 true US20020160185A1 (en) 2002-10-31

Family

ID=15168704

Family Applications (3)

Application Number Title Priority Date Filing Date
US08/857,674 Expired - Lifetime US6114753A (en) 1996-05-30 1997-05-16 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US10/138,485 Abandoned US20020160185A1 (en) 1996-05-30 2002-05-06 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
US10/724,092 Expired - Fee Related US7202570B2 (en) 1996-05-30 2003-12-01 Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

Family Applications Before (1)

Application Number Title Priority Date Filing Date
US08/857,674 Expired - Lifetime US6114753A (en) 1996-05-30 1997-05-16 Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same

Family Applications After (1)

Application Number Title Priority Date Filing Date
US10/724,092 Expired - Fee Related US7202570B2 (en) 1996-05-30 2003-12-01 Circuit tape having adhesive film semiconductor device and a method for manufacturing the same

Country Status (4)

Country Link
US (3) US6114753A (en)
JP (1) JP3195236B2 (en)
KR (1) KR100610629B1 (en)
TW (1) TW345724B (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060228562A1 (en) * 2005-03-25 2006-10-12 Ken Ukawa Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulating
US20070218586A1 (en) * 2006-03-16 2007-09-20 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US20070299215A1 (en) * 2006-06-22 2007-12-27 General Electric Company Polysiloxane/Polyimide Copolymers and Blends Thereof
US20080236864A1 (en) * 2007-03-28 2008-10-02 General Electric Company Cross linked polysiloxane/polyimide copolymers, methods of making, blends thereof, and articles derived therefrom
US7518237B2 (en) * 2005-02-08 2009-04-14 Micron Technology, Inc. Microfeature systems including adhered microfeature workpieces and support members
US7615871B2 (en) 2002-04-04 2009-11-10 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members

Families Citing this family (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3195236B2 (en) 1996-05-30 2001-08-06 株式会社日立製作所 Wiring tape having adhesive film, semiconductor device and manufacturing method
JP3652488B2 (en) * 1997-12-18 2005-05-25 Ｔｄｋ株式会社 Manufacturing method of resin package
KR100266138B1 (en) * 1998-06-24 2000-09-15 윤종용 Method for manufacturing chip scale package
KR20000015583A (en) * 1998-08-31 2000-03-15 김규현 Circuit film and elastomer tape adhesion apparatus for fabricating a semiconductor package
JP3661444B2 (en) * 1998-10-28 2005-06-15 株式会社ルネサステクノロジ Semiconductor device, semiconductor wafer, semiconductor module, and semiconductor device manufacturing method
JP4534100B2 (en) * 1998-11-10 2010-09-01 日立化成工業株式会社 Double-sided adhesive film for electronic parts, organic substrate for semiconductor mounting, and semiconductor device
US6541872B1 (en) 1999-01-11 2003-04-01 Micron Technology, Inc. Multi-layered adhesive for attaching a semiconductor die to a substrate
US6306680B1 (en) * 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
TW556329B (en) 1999-02-26 2003-10-01 Hitachi Ltd Wiring board, its production method, semiconductor device and its production method
JP3344372B2 (en) 1999-06-29 2002-11-11 日本電気株式会社 Method for manufacturing semiconductor device
TW478089B (en) 1999-10-29 2002-03-01 Hitachi Ltd Semiconductor device and the manufacturing method thereof
US6770547B1 (en) 1999-10-29 2004-08-03 Renesas Technology Corporation Method for producing a semiconductor device
TW498468B (en) 1999-10-29 2002-08-11 Hitachi Ltd Semiconductor device
JP2001131501A (en) * 1999-11-04 2001-05-15 Hitachi Chem Co Ltd Three-layer adhesive film, semiconductor chip-carrying substrate and semiconductor device
JP2001152107A (en) * 1999-11-25 2001-06-05 Hitachi Chem Co Ltd Laminated adhesive film, substrate for mounting semiconductor chip and semiconductor device
EP1139415B1 (en) * 2000-03-30 2009-02-25 Nitto Denko Corporation Water-permeable adhesive tape for semiconductor processing
US6696765B2 (en) 2001-11-19 2004-02-24 Hitachi, Ltd. Multi-chip module
US6730595B2 (en) * 2000-12-12 2004-05-04 Mitsui Chemicals, Inc. Protecting method for semiconductor wafer and surface protecting adhesive film for semiconductor wafer used in said method
JP4701339B2 (en) * 2001-02-22 2011-06-15 日東電工株式会社 Method for producing breathable adhesive sheet
JP3840921B2 (en) * 2001-06-13 2006-11-01 株式会社デンソー Printed circuit board and manufacturing method thereof
JP2003003134A (en) * 2001-06-20 2003-01-08 Japan Gore Tex Inc IC chip bonding sheet and IC package
DE10133361C2 (en) * 2001-07-10 2003-05-28 Infineon Technologies Ag Process for the production of packaging for semiconductor chips
CN100339948C (en) * 2002-03-28 2007-09-26 三井化学株式会社 Adhesive film for protection of semiconductor wafer surface and method of protecting semiconductor wafer with the adhesive film
US7323772B2 (en) * 2002-08-28 2008-01-29 Micron Technology, Inc. Ball grid array structures and tape-based method of manufacturing same
KR101177250B1 (en) 2003-06-06 2012-08-24 히다치 가세고교 가부시끼가이샤 Adhesive sheet, dicing tape integrated type, adhesive sheet, and semiconductor device producing method
JP4397653B2 (en) * 2003-08-26 2010-01-13 日東電工株式会社 Adhesive sheet for semiconductor device manufacturing
JP4370513B2 (en) * 2004-02-27 2009-11-25 エルピーダメモリ株式会社 Semiconductor device
JPWO2005112091A1 (en) * 2004-05-18 2008-03-27 日立化成工業株式会社 Adhesive sheet, semiconductor device using the same, and manufacturing method thereof
US7697400B2 (en) * 2005-02-21 2010-04-13 Panasonic Corporation Optical pickup and optical disc device
KR100593814B1 (en) * 2005-12-06 2006-06-28 에이스 인더스트리 주식회사 Adhesive Tape for Semiconductor Die Bonding
TW200802771A (en) * 2006-06-08 2008-01-01 Chipmos Technologies Inc BGA package with leads on chip
JP5028968B2 (en) * 2006-11-17 2012-09-19 日立電線株式会社 Semiconductor device, stacked semiconductor device, and interposer substrate
US20080237855A1 (en) * 2007-03-28 2008-10-02 Powertech Technology Inc. Ball grid array package and its substrate
US20090001599A1 (en) * 2007-06-28 2009-01-01 Spansion Llc Die attachment, die stacking, and wire embedding using film
KR20090111091A (en) * 2008-04-21 2009-10-26 (주)모디스텍 Conductive Film Structure and Patterning Method
US20120113361A1 (en) * 2010-11-10 2012-05-10 Tpk Touch Solutions Inc. Optical Level Composite Pressure-Sensitive Adhesive and an Apparatus Therewith
JP6002672B2 (en) * 2010-11-15 2016-10-05 アプライド マテリアルズ インコーポレイテッドＡｐｐｌｉｅｄ Ｍａｔｅｒｉａｌｓ，Ｉｎｃｏｒｐｏｒａｔｅｄ Adhesive material used to join chamber components
DE102014115099B4 (en) 2014-10-16 2021-05-06 Infineon Technologies Ag Electronic module with an electrically insulating structure with material with a low modulus of elasticity and a method of manufacturing an electronic module

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5507910A (en) * 1993-04-28 1996-04-16 Apic Yamada Corporation Lead frame taping machine

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5882217U (en) 1981-11-27 1983-06-03 ヤマウチ株式会社 Cushioning material for molding presses
JPH01175747A (en) 1987-12-29 1989-07-12 Canon Inc Apparatus and method for cutting conductive adhesive film
JP2834841B2 (en) 1990-04-20 1998-12-14 沖電気工業株式会社 High heat resistant resin encapsulated semiconductor device
WO1992000558A2 (en) 1990-06-29 1992-01-09 Analog Devices, Inc. Apparatus for generating multiple phase clock signals and phase detector and recovery apparatus therefor
US5148265A (en) 1990-09-24 1992-09-15 Ist Associates, Inc. Semiconductor chip assemblies with fan-in leads
US5219640A (en) 1991-02-08 1993-06-15 Rogers Corporation Flexible circuit having flexing section of reduced stiffness, and method of manufacture thereof
US5440756A (en) * 1992-09-28 1995-08-08 Larson; Bruce E. Apparatus and method for real-time extraction and display of musical chord sequences from an audio signal
JPH06256733A (en) 1992-10-01 1994-09-13 Toray Ind Inc Heat-resistant adhesive material
US5406124A (en) * 1992-12-04 1995-04-11 Mitsui Toatsu Chemicals, Inc. Insulating adhesive tape, and lead frame and semiconductor device employing the tape
JP2645969B2 (en) 1993-02-10 1997-08-25 株式会社巴川製紙所 Adhesive tape for semiconductor
JP3385711B2 (en) 1993-04-13 2003-03-10 東レ株式会社 Heat resistant adhesive material
JP3386567B2 (en) 1993-04-28 2003-03-17 アピックヤマダ株式会社 Taping device
US5521323A (en) * 1993-05-21 1996-05-28 Coda Music Technologies, Inc. Real-time performance score matching
TW258829B (en) * 1994-01-28 1995-10-01 Ibm
JPH0831868A (en) 1994-07-21 1996-02-02 Hitachi Cable Ltd BGA type semiconductor device
JP2616565B2 (en) 1994-09-12 1997-06-04 日本電気株式会社 Electronic component assembly
JP2595909B2 (en) * 1994-09-14 1997-04-02 日本電気株式会社 Semiconductor device
JPH08111473A (en) 1994-10-07 1996-04-30 Hitachi Ltd Ball grid array type package and mounting structure using the same
US5620928A (en) * 1995-05-11 1997-04-15 National Semiconductor Corporation Ultra thin ball grid array using a flex tape or printed wiring board substrate and method
WO1996037915A1 (en) 1995-05-26 1996-11-28 Sheldahl, Inc. Adherent film with low thermal impedance and high electrical impedance used in an electronic assembly with a heat sink
US5646451A (en) * 1995-06-07 1997-07-08 Lucent Technologies Inc. Multifunctional chip wire bonds
JPH09107046A (en) 1995-10-11 1997-04-22 Hitachi Chem Co Ltd Semiconductor package
JPH09275161A (en) 1996-04-04 1997-10-21 Hitachi Ltd Semiconductor device
JP3195236B2 (en) 1996-05-30 2001-08-06 株式会社日立製作所 Wiring tape having adhesive film, semiconductor device and manufacturing method
JPH1098072A (en) * 1996-09-20 1998-04-14 Hitachi Ltd Semiconductor device and manufacturing method thereof
US5952597A (en) * 1996-10-25 1999-09-14 Timewarp Technologies, Ltd. Method and apparatus for real-time correlation of a performance to a musical score
US5900312A (en) 1996-11-08 1999-05-04 W. L. Gore & Associates, Inc. Integrated circuit chip package assembly
US5990545A (en) 1996-12-02 1999-11-23 3M Innovative Properties Company Chip scale ball grid array for integrated circuit package
US5866949A (en) * 1996-12-02 1999-02-02 Minnesota Mining And Manufacturing Company Chip scale ball grid array for integrated circuit packaging
US6166314A (en) * 1997-06-19 2000-12-26 Time Warp Technologies, Ltd. Method and apparatus for real-time correlation of a performance to a musical score
US5800758A (en) * 1997-09-16 1998-09-01 Kimberly-Clark Worldwide, Inc. Process for making microporous films with improved properties
US5913259A (en) * 1997-09-23 1999-06-15 Carnegie Mellon University System and method for stochastic score following
US6057502A (en) * 1999-03-30 2000-05-02 Yamaha Corporation Apparatus and method for recognizing musical chords
JP4389330B2 (en) * 2000-03-22 2009-12-24 ヤマハ株式会社 Performance position detection method and score display device

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5507910A (en) * 1993-04-28 1996-04-16 Apic Yamada Corporation Lead frame taping machine

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7615871B2 (en) 2002-04-04 2009-11-10 Micron Technology, Inc. Method and apparatus for attaching microelectronic substrates and support members
US7518237B2 (en) * 2005-02-08 2009-04-14 Micron Technology, Inc. Microfeature systems including adhered microfeature workpieces and support members
US8278751B2 (en) 2005-02-08 2012-10-02 Micron Technology, Inc. Methods of adhering microfeature workpieces, including a chip, to a support member
US9064973B2 (en) 2005-02-08 2015-06-23 Micron Technology, Inc. Die attached to a support member by a plurality of adhesive members
US20060228562A1 (en) * 2005-03-25 2006-10-12 Ken Ukawa Semiconductor device, resin composition for buffer coating, resin composition for die bonding, and resin composition for encapsulating
US20070218586A1 (en) * 2006-03-16 2007-09-20 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US7736999B2 (en) * 2006-03-16 2010-06-15 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US20100207252A1 (en) * 2006-03-16 2010-08-19 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US8039364B2 (en) * 2006-03-16 2011-10-18 Kabushiki Kaisha Toshiba Manufacturing method of semiconductor device
US20070299215A1 (en) * 2006-06-22 2007-12-27 General Electric Company Polysiloxane/Polyimide Copolymers and Blends Thereof
US8071693B2 (en) 2006-06-22 2011-12-06 Sabic Innovative Plastics Ip B.V. Polysiloxane/polyimide copolymers and blends thereof
US20080236864A1 (en) * 2007-03-28 2008-10-02 General Electric Company Cross linked polysiloxane/polyimide copolymers, methods of making, blends thereof, and articles derived therefrom

Also Published As

Publication number Publication date
KR100610629B1 (en) 2006-10-31
JP3195236B2 (en) 2001-08-06
US6114753A (en) 2000-09-05
TW345724B (en) 1998-11-21
JPH09321084A (en) 1997-12-12
US7202570B2 (en) 2007-04-10
US20040224149A1 (en) 2004-11-11
KR970077572A (en) 1997-12-12

Similar Documents

Publication Publication Date Title
US7202570B2 (en) Circuit tape having adhesive film semiconductor device and a method for manufacturing the same
US6064111A (en) Substrate for holding a chip of semi-conductor package, semi-conductor package, and fabrication process of semi-conductor package
US7038325B2 (en) Wiring tape for semiconductor device including a buffer layer having interconnected foams
US6118183A (en) Semiconductor device, manufacturing method thereof, and insulating substrate for same
JP4665298B2 (en) TAPE WITH ADHESIVE FOR SEMICONDUCTOR DEVICE, COPPER-CLAD LAMINATE USING SAME, SEMICONDUCTOR CONNECTION BOARD AND SEMICONDUCTOR DEVICE
JP2000133683A (en) Semiconductor device, semiconductor wafer, semiconductor module, and method of manufacturing semiconductor device
US6791194B1 (en) Circuit tape having adhesive film, semiconductor device, and a method for manufacturing the same
JP2001230341A (en) Semiconductor device
JP4714406B2 (en) Die bonding material for semiconductor device and semiconductor device using the same
JP2004179647A (en) Wiring board, semiconductor package, and method for producing base insulating film and wiring board
JP3895920B2 (en) Semiconductor device
JP3718083B2 (en) Adhesive film for semiconductor devices
JPH1197578A (en) Semiconductor device and manufacturing method
JP3195315B2 (en) Wiring tape with adhesive layer for semiconductor device and method of manufacturing the same
JP4489742B2 (en) Ball grid array semiconductor device
JP3576870B2 (en) Semiconductor device
JP3915226B2 (en) Chip support substrate for semiconductor package and semiconductor package
JP3616742B2 (en) Chip support substrate for semiconductor package
JP2001267462A (en) Chip supporting substrate for semiconductor package, semiconductor device and method for manufacturing the same
JP4452964B2 (en) Semiconductor mounting substrate manufacturing method and semiconductor package manufacturing method
JP3314142B2 (en) Semiconductor package manufacturing method
JPH0878566A (en) Resin-sealed semiconductor device and manufacturing method
JPH1187562A (en) Semiconductor device and manufacturing method
JP2000277666A (en) Conductive ball reinforcing resin sheet
JP2003092378A (en) Tape with adhesive for semiconductor device and copper- clad laminate using the same, substrate for connecting semiconductor and semiconductor device

Legal Events

Date Code Title Description
AS Assignment

Owner name: RENESAS TECHNOLOGY CORPORATION, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:HITACHI, LTD.;REEL/FRAME:014553/0788

Effective date: 20030912

STCB Information on status: application discontinuation

Free format text: ABANDONED -- FAILURE TO RESPOND TO AN OFFICE ACTION

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载