US20020134911A1 - Method and apparatus for independent readout and reset of pixels within a CMOS image sensor - Google Patents
Method and apparatus for independent readout and reset of pixels within a CMOS image sensor Download PDFInfo
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- US20020134911A1 US20020134911A1 US09/536,581 US53658100A US2002134911A1 US 20020134911 A1 US20020134911 A1 US 20020134911A1 US 53658100 A US53658100 A US 53658100A US 2002134911 A1 US2002134911 A1 US 2002134911A1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/77—Pixel circuitry, e.g. memories, A/D converters, pixel amplifiers, shared circuits or shared components
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/616—Noise processing, e.g. detecting, correcting, reducing or removing noise involving a correlated sampling function, e.g. correlated double sampling [CDS] or triple sampling
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/60—Noise processing, e.g. detecting, correcting, reducing or removing noise
- H04N25/67—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response
- H04N25/671—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction
- H04N25/677—Noise processing, e.g. detecting, correcting, reducing or removing noise applied to fixed-pattern noise, e.g. non-uniformity of response for non-uniformity detection or correction for reducing the column or line fixed pattern noise
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
- H04N25/70—SSIS architectures; Circuits associated therewith
- H04N25/76—Addressed sensors, e.g. MOS or CMOS sensors
- H04N25/78—Readout circuits for addressed sensors, e.g. output amplifiers or A/D converters
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
- H10F39/00—Integrated devices, or assemblies of multiple devices, comprising at least one element covered by group H10F30/00, e.g. radiation detectors comprising photodiode arrays
- H10F39/80—Constructional details of image sensors
- H10F39/802—Geometry or disposition of elements in pixels, e.g. address-lines or gate electrodes
Definitions
- This invention relates generally to controlling the exposure time for elements of a scene. More specifically, it allows one to control the exposure time of any pixel or group of pixels within a scene, independent of readout time (frame-rate), therefore extending the dynamic range to accommodate a given scene.
- This invention allows readout rate (and exposure time) to be optimized to the portion of the scene that is poorly illuminated, achieving good signal level, AND control the exposure time of the portion of the scene that is well illuminated at the same time. This achieves maximization of the intra-scene illumination levels unavailable before now.
- FIG. 1 is prior art CMOS Imager, with fixed readout and reset control.
- FIG. 2 is an active column sensor in accordance with this invention.
- FIG. 3 is an implementation of a pixel in accordance with the invention.
- FIG. 4 is a schematic illustration of a matrix of pixels connected to incorporate a full operational amplifier per pixel forming an active column sensor.
- FIG. 5 is the invention that enables independent readout and reset control.
- FIG. 6 shows additional selection circuitry on the column.
- FIG. 7 shows typical pixel implementation.
- FIG. 8 shows that by adding latches, an entire group or sub-array can be addressed simultaneously.
- FIG. 1 illustrates a typical prior art CMOS imager, utilizing a fixed read out and reset control in which a given row is selected, and its pixels are read out. After the pixels in the selected row are readout, the pixels within that row are reset, and then immediately placed in the exposure state. This mode of operation fixes the exposure time to the readout rate (frame rate).
- FIG. 2 is a schematic diagram of a pixel 12 in accordance with the present invention in which the threshold variations from pixel to pixel of the prior art are eliminated. All pixels 12 in a row or column are read out in parallel and for simplicity only one is shown.
- Pixel 12 which can consist of any photosensitive device 10 , is coupled to a FET 15 to isolate the pixel from the readout circuitry.
- the FET 15 is one FET of a differential input pair of an operational amplifier 30 that includes FET 24 .
- the amplifier circuit 30 is configured as a positive feedback unity gain amplifier.
- a feedback path 32 connects the output of amplifier 30 to input 17 , which in this case is the gate of FET 24 .
- the amplifier 30 can be configured to have gain, a full differential input, or any operational amplifier configuration as the application required.
- the fixed gain of amplifier 30 eliminates the gain variability of the prior art.
- the output of the unity gain amplifier is connected to a Correlated Double Sampler (CDS) that is utilized to eliminate any fixed pattern noise in the video.
- CDS Correlated Double Sampler
- a current source 20 comprising a FET 22 has its source connected to a power source VDD and its drain connected to the sources of differential input FETs 15 and 24 .
- the drains of input FETs 15 and 24 are connected to a current mirror formed from FETs 26 and 28 .
- the gates of FETs 26 and 28 are connected together and to the source 18 of input FET 15 .
- the sources of FETs 26 and 28 are connected to a negative power source, VCC.
- the source 30 of FET 24 is the output of the differential pair and is connected to CDS 34 .
- the input FET 15 could be either an N channel or P channel FET as the application requires.
- the pixel # 80 could be either a photogate or a photodiode.
- FIG. 3 is a detailed schematic of pixel 12 of the active column sensor shown in FIG. 2.
- a photogate 76 is utilized.
- FET 76 controls the selection and reset of sense node # 72 .
- This active column sensor pixel eliminates the separate selection/access FET 58 of prior art. All biasing and controls signals are supplied from the periphery of the pixel array.
- the pixel can be operated in the following manner.
- An N type substrate is used and the substrate is biased the most positive potential, e.g. 5.0 volts.
- the photogate # 70 preferably a layer of polysilicon, is biased to an integrate level (e.g.. 0.0 volts).
- the region 80 under the photogate # 70 is depleted and as light strikes the immediate area, it will collect (integrate) photon generated carriers.
- Photogate 72 is biased to 5.0 volts and will not collect photon-generated carriers during the integration because it is biased to the same potential as the substrate.
- Selecting FET 76 with the reset/Select Control signal biases Photogate 72 .
- FET 76 is a P channel FET that is selected by a negative signal relative to the substrate, for example 0.0 volts.
- the photogate is biased by the reset/select bias that preferably is at 5.0 volts. After a predetermined integration time period the pixel is read.
- Reading the pixel is preferably accomplished in the following manner.
- the reset/select control is changed to 2.5 volts, causing the region beneath photogate # 72 to be depleted, and the background level is read. Setting the reset/select control to 5.0 volts turns off Reset/select FET 76 .
- Photogate 70 has its potential removed, and in this example 5.00 volts. Reading the signal will occur as the collected photon generated charge transfers from the region beneath photogate 70 to the region beneath photogate 72 . The transferred photon generated charge modulates the gate of input FET 15 , according to the amount of collected.
- FPN Fixed Pattern Noise
- FIG. 4 is a schematic diagram of an array of pixels in accordance with this invention.
- a plurality of pixels 90 a , 90 b , and 90 c form a first column of the array, and similar columns 92 a - c and 94 a - c complete the array.
- the pixels are connected with their output FETs in parallel, the combination forming the first one of the differential input pair of operational amplifier 30 .
- amplifiers 30 a , 30 b and 30 c are identical to FIG. 2.
- Each amplifier 30 is connected to CDS 34 a , 34 b , and 34 c respectively.
- CDS 34 a, b, c are connected through column select switches 96 a , 96 b , and 96 c , the common terminals of which are connected to output buffer 98 which can be a source follower, or a more complex signal conditioner as required by the specific application.
- FIG. 5 illustrates a further embodiment of the claimed invention.
- the reset portion of the circuitry is separated from the readout circuitry. It is joined with its own independent row selection method. This allows any given row to be reset and placed into the exposure state while any other row is being readout. The readout and reset functions can now be performed independently.
- FIG. 6 illustrates a further improvement for the invention.
- selection circuitry is placed along both the columns and the rows.
- a type of logic gate commonly known as an “AND” gate is located within the pixel.
- the AND gate is simply two switches connected in series within the pixel. One switch is connected to and triggered by the row selection circuitry, and the other switch is connected to and triggered by the column selection circuitry. Only when both switches are triggered can the pixel be reset or readout. This configuration enables one to readout or reset any given pixel independently.
- FIG. 8 demonstrates that by adding additional circuitry to latch the selected addresses, a group or “sub-array” can be reset and put into the exposure state simultaneously, causing all the pixels comprising that sub-array to have the identical exposure time.
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Abstract
Description
- This application is a Continuation-in-Part of U.S. patent application Ser. No. 09/039,835 filed on Mar. 16, 1998 naming Matthew A. Pace and Jeffrey J. Zarnowski as inventors.
- This invention relates generally to controlling the exposure time for elements of a scene. More specifically, it allows one to control the exposure time of any pixel or group of pixels within a scene, independent of readout time (frame-rate), therefore extending the dynamic range to accommodate a given scene.
- Prior to the current invention, it was not possible to have independent control of the readout and reset functions of a CMOS imager pixel. In prior art imagers, selection circuitry was connected to the rows of a pixel array for selecting a row to be readout or reset. That row was then either readout or reset by control circuitry connected to it. The problem with these prior art imagers was that it was not possible to independently select one row for readout and a second row for reset. Only one selection circuit was connected to each row. Once a row was selected, that row could be readout or reset, but no other row could be reset while the first row was being read. After the pixels in the selected row were readout, the pixels within that row were reset, or placed in the exposure state. This mode of operation fixes the exposure time to the readout rate (frame rate).
- In a scene that contained both well-illuminated and poorly illuminated portions, it was necessary to compromise readout time (frame rate) to achieve sufficient signal in the poorly illuminated portions, while attempting not to over expose the portions that were well illuminated.
- Because of the independent row read nature and random address capability inherent to the active column sensor, this invention is possible.
- This invention allows readout rate (and exposure time) to be optimized to the portion of the scene that is poorly illuminated, achieving good signal level, AND control the exposure time of the portion of the scene that is well illuminated at the same time. This achieves maximization of the intra-scene illumination levels unavailable before now.
- This is accomplished through the addition of a second selection circuit. Now, a row for readout may be selected simultaneously with a row for reset and both readout and reset may occur. The further addition of another selection circuit allows a column of elements to be chosen for additional readout or reset. The additional selection circuit enables one to select individual pixels for readout and reset.
- FIG. 1 is prior art CMOS Imager, with fixed readout and reset control.
- FIG. 2 is an active column sensor in accordance with this invention;
- FIG. 3 is an implementation of a pixel in accordance with the invention;
- FIG. 4 is a schematic illustration of a matrix of pixels connected to incorporate a full operational amplifier per pixel forming an active column sensor.
- FIG. 5 is the invention that enables independent readout and reset control.
- FIG. 6 shows additional selection circuitry on the column.
- FIG. 7 shows typical pixel implementation.
- FIG. 8 shows that by adding latches, an entire group or sub-array can be addressed simultaneously.
- FIG. 1 illustrates a typical prior art CMOS imager, utilizing a fixed read out and reset control in which a given row is selected, and its pixels are read out. After the pixels in the selected row are readout, the pixels within that row are reset, and then immediately placed in the exposure state. This mode of operation fixes the exposure time to the readout rate (frame rate).
- FIG. 2 is a schematic diagram of a
pixel 12 in accordance with the present invention in which the threshold variations from pixel to pixel of the prior art are eliminated. Allpixels 12 in a row or column are read out in parallel and for simplicity only one is shown.Pixel 12, which can consist of anyphotosensitive device 10, is coupled to aFET 15 to isolate the pixel from the readout circuitry. The FET 15 is one FET of a differential input pair of anoperational amplifier 30 that includes FET 24. For simplicity, in FIG. 2 theamplifier circuit 30 is configured as a positive feedback unity gain amplifier. Afeedback path 32 connects the output ofamplifier 30 to input 17, which in this case is the gate ofFET 24. Theamplifier 30 can be configured to have gain, a full differential input, or any operational amplifier configuration as the application required. The fixed gain ofamplifier 30 eliminates the gain variability of the prior art. The output of the unity gain amplifier is connected to a Correlated Double Sampler (CDS) that is utilized to eliminate any fixed pattern noise in the video. - A
current source 20 comprising aFET 22 has its source connected to a power source VDD and its drain connected to the sources ofdifferential input FETs - The drains of
input FETs FETs source 18 ofinput FET 15. The sources of FETs 26 and 28 are connected to a negative power source, VCC. - The
source 30 of FET 24 is the output of the differential pair and is connected toCDS 34. - The
input FET 15 could be either an N channel or P channel FET as the application requires. Thepixel # 80 could be either a photogate or a photodiode. - FIG. 3 is a detailed schematic of
pixel 12 of the active column sensor shown in FIG. 2. In this implementation aphotogate 76 is utilized. FET 76 controls the selection and reset ofsense node # 72. This active column sensor pixel eliminates the separate selection/access FET 58 of prior art. All biasing and controls signals are supplied from the periphery of the pixel array. - The pixel can be operated in the following manner. An N type substrate is used and the substrate is biased the most positive potential, e.g. 5.0 volts. The
photogate # 70, preferably a layer of polysilicon, is biased to an integrate level (e.g.. 0.0 volts). Theregion 80 under thephotogate # 70 is depleted and as light strikes the immediate area, it will collect (integrate) photon generated carriers. Photogate 72 is biased to 5.0 volts and will not collect photon-generated carriers during the integration because it is biased to the same potential as the substrate. SelectingFET 76 with the reset/Select Control signal biases Photogate 72. In this configuration FET 76 is a P channel FET that is selected by a negative signal relative to the substrate, for example 0.0 volts. During integration FET 76 is selected, the photogate is biased by the reset/select bias that preferably is at 5.0 volts. After a predetermined integration time period the pixel is read. - Reading the pixel is preferably accomplished in the following manner. The reset/select control is changed to 2.5 volts, causing the region beneath
photogate # 72 to be depleted, and the background level is read. Setting the reset/select control to 5.0 volts turns off Reset/select FET 76.Photogate 70 has its potential removed, and in this example 5.00 volts. Reading the signal will occur as the collected photon generated charge transfers from the region beneathphotogate 70 to the region beneathphotogate 72. The transferred photon generated charge modulates the gate ofinput FET 15, according to the amount of collected. - Fixed Pattern Noise (FPN) can be eliminated from the video information by utilizing
CDS circuit 34. The first sample applied to the CDS circuit is the background level. The signal information is then applied to the CDS. The difference of the two signals provides for a fixed pattern noise free signal. - FIG. 4 is a schematic diagram of an array of pixels in accordance with this invention. A plurality of
pixels operational amplifier 30. In all other respects,amplifiers amplifier 30 is connected toCDS CDS 34 a, b, c are connected through columnselect switches 96 a, 96 b, and 96 c, the common terminals of which are connected tooutput buffer 98 which can be a source follower, or a more complex signal conditioner as required by the specific application. - FIG. 5 illustrates a further embodiment of the claimed invention. In this embodiment the reset portion of the circuitry is separated from the readout circuitry. It is joined with its own independent row selection method. This allows any given row to be reset and placed into the exposure state while any other row is being readout. The readout and reset functions can now be performed independently.
- FIG. 6 illustrates a further improvement for the invention. In this embodiment, selection circuitry is placed along both the columns and the rows. A type of logic gate commonly known as an “AND” gate is located within the pixel. The AND gate is simply two switches connected in series within the pixel. One switch is connected to and triggered by the row selection circuitry, and the other switch is connected to and triggered by the column selection circuitry. Only when both switches are triggered can the pixel be reset or readout. This configuration enables one to readout or reset any given pixel independently.
- FIG. 8 demonstrates that by adding additional circuitry to latch the selected addresses, a group or “sub-array” can be reset and put into the exposure state simultaneously, causing all the pixels comprising that sub-array to have the identical exposure time.
- While the invention has been described in connection with preferred embodiments, it is not intended to limit the scope of the invention to the particular forms set forth, but on the contrary, it is intended to cover such alternatives, modifications, and equivalents as may be included within the spirit and scope of the invention as defined by the appended claims.
Claims (7)
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US09/536,581 US20020134911A1 (en) | 1998-03-16 | 2000-03-28 | Method and apparatus for independent readout and reset of pixels within a CMOS image sensor |
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US09/039,835 US6084229A (en) | 1998-03-16 | 1998-03-16 | Complimentary metal oxide semiconductor imaging device |
US09/536,581 US20020134911A1 (en) | 1998-03-16 | 2000-03-28 | Method and apparatus for independent readout and reset of pixels within a CMOS image sensor |
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US09/039,835 Continuation-In-Part US6084229A (en) | 1998-03-16 | 1998-03-16 | Complimentary metal oxide semiconductor imaging device |
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US09/039,835 Expired - Lifetime US6084229A (en) | 1998-03-16 | 1998-03-16 | Complimentary metal oxide semiconductor imaging device |
US09/536,581 Abandoned US20020134911A1 (en) | 1998-03-16 | 2000-03-28 | Method and apparatus for independent readout and reset of pixels within a CMOS image sensor |
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EP (1) | EP1062802B1 (en) |
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KR (1) | KR100549385B1 (en) |
CN (1) | CN1200555C (en) |
AT (1) | ATE251829T1 (en) |
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US6084229A (en) | 2000-07-04 |
JP4388696B2 (en) | 2009-12-24 |
DE69911932D1 (en) | 2003-11-13 |
EP1062802A1 (en) | 2000-12-27 |
CN1293863A (en) | 2001-05-02 |
ATE251829T1 (en) | 2003-10-15 |
IL137832A (en) | 2005-08-31 |
WO1999048282A1 (en) | 1999-09-23 |
JP2002507864A (en) | 2002-03-12 |
AU2999899A (en) | 1999-10-11 |
KR20010034571A (en) | 2001-04-25 |
IL137832A0 (en) | 2001-10-31 |
EP1062802B1 (en) | 2003-10-08 |
DE69911932T2 (en) | 2004-08-12 |
KR100549385B1 (en) | 2006-02-08 |
CN1200555C (en) | 2005-05-04 |
CA2323486A1 (en) | 1999-09-23 |
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