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US20020095192A1 - Method of fabricating a flip-chip ball-grid-array package with molded underfill - Google Patents

Method of fabricating a flip-chip ball-grid-array package with molded underfill Download PDF

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Publication number
US20020095192A1
US20020095192A1 US09/760,440 US76044001A US2002095192A1 US 20020095192 A1 US20020095192 A1 US 20020095192A1 US 76044001 A US76044001 A US 76044001A US 2002095192 A1 US2002095192 A1 US 2002095192A1
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substrate
mold
vent hole
flip
chip
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US6451625B1 (en
Inventor
Han-Ping Pu
Tzong-Da Ho
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Siliconware Precision Industries Co Ltd
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Siliconware Precision Industries Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83102—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus using surface energy, e.g. capillary forces
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15151—Shape the die mounting substrate comprising an aperture, e.g. for underfilling, outgassing, window type wire connections
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress

Definitions

  • This invention relates to integrated circuit packaging technology, and more particularly, to a method of fabricating a FCBGA Flip-Chip Ball-Grid-Array) package with molded underfill.
  • BGA Bit Grid Array
  • SMT Surface Mount Technology
  • FCBGA Flip-Chip Ball-Grid-Array
  • FCBGA Flip-Chip Ball-Grid-Array
  • the semiconductor chip is mounted in an upside-down (i.e., clip chip) manner over the substrate and bonded to the same by means of a plurality of solder bumps attached to the I/O pads thereon.
  • FIGS. 1 A- 1 D are simplified schematic diagrams showing only the parts related to the invention; the actual layout on the FCBGA package may be much more complex).
  • FIG. 1A is a schematic sectional diagram showing a semi-finished FCBGA package assembly before molding; and FIG. 1B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 1A.
  • the semi-finished FCBGA package assembly includes: (a) a substrate 110 having a front surface 110 a and a back surface 110 b ; (b) a semiconductor chip 120 mounted in an upside-down (i.e., flip chip) manner by means of a plurality of solder bumps 121 over the front surface 110 a of the substrate 110 ; (c) an array of solder-ball pads 130 formed over the back surface 110 b of the substrate 110 , which are used for subsequent attachment of an array of solder balls (not shown) thereon; and (d) a solder mask 140 which is predefined with a plurality of openings 141 to expose the solder-ball pads 130 .
  • a flip-chip undergap 120 a would be undesirably left between the semiconductor chip 120 and the substrate 110 . If this flip-chip undergap 120 a is not underfilled, it would easily cause the semiconductor chip 120 to suffer from fatigue cracking and electrical failure due to thermal stress when the entire package structure is being subjected to high-temperature conditions.
  • One solution to this problem is to perform a molded-underfill process.
  • vent hole 111 is formed by drilling through the vent hole 111 and the solder mask 140 , so that the part of the vent hole 111 in the solder mask 140 is equal in inside diameter as the part in the substrate 110 .
  • the semi-finished FCBGA package assembly is disposed in a molding tool (not shown), and an encapsulation material, such as epoxy resin, is injected into the molding tool (not shown) to form an encapsulation body 150 to encapsulate the semiconductor chip 120 .
  • an encapsulation material such as epoxy resin
  • the encapsulation material will also infiltrate into the flip-chip undergap 120 a .
  • the air in the flip-chip undergap 120 a can escape to the outside atmosphere, thus allowing the encapsulation material to infiltrate unresistingly into the entire flip-chip undergap 120 a and thereby form a molded underfill layer 122 between the semiconductor chip 120 and the substrate 110 .
  • the invention proposes an improved method for fabricating a FCBGA package with molded underfill
  • the method of the invention comprises the following steps. (1) preparing a substrate having a front surface and a back surface; the substrate being formed with a vent hole at a predefined location; the vent hole having an exit in the back surface of the substrate; (2) forming a plurality of solder-ball pads over the back surface of the substrate; (3) forming a solder mask over the back surface of the substrate; wherein the solder mask is predefined with an array of pad openings to expose the solder-ball pads and a mold-buffering opening aligned to the vent hole; and wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole; (4) mounting a flip chip over the front surface of the substrate; wherein a flip-chip undergap is left between the flip chip and the substrate; and (5) performing a molding process to form an encapsulation body through the injection of a encapsulation material to encapsulate the flip chip; wherein the vent hole allows the air in the
  • FIG. 1A is a schematic sectional diagram showing a semi-finished FCBGA package assembly before molding
  • FIG. 1B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 1A;
  • FIG. 1C is a schematic sectional diagram showing the semi-finished FCBGA package assembly of FIG. 1A after molding
  • FIG. 1D shows a bottom view of the molded FCBGA package assembly of FIG. 1C;
  • FIG. 2A is a schematic sectional diagram showing a semi-finished FCBGA package assembly configured according to the invention before molding
  • FIG. 2B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 2A
  • FIG. 2C is a schematic sectional diagram showing the semi-finished FCBGA package assembly of FIG. 2A after molding
  • FIG. 2D shows a bottom view of the molded FCBGA package assembly of FIG. 2C
  • FIG. 3 shows another embodiment of the invention.
  • FIG. 2A is a schematic sectional diagram showing a semi-finished FCB GA package assembly before molding; and FIG. 2B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 2A.
  • the semi-finished FCBGA package assembly includes: (a) a substrate 210 having a front surface 210 a and a back surface 210 b ; (b) a semiconductor chip 220 mounted in an upside-down (i.e., flip chip) manner by means of a plurality of solder bumps 221 over the front surface 210 a of the substrate 210 ; (c) an array of solder-ball pads 230 formed over the back surface 210 b of the substrate 210 , which are used for subsequent attachment of an array of solder balls (not shown) thereon; and (d) a solder mask 240 which is predefined with a plurality of pad openings 241 to expose the solder-ball pads 230 .
  • a flip-chip undergap 220 a would be undesirably left between the semiconductor chip 220 and the substrate 210 .
  • a vent hole 211 is drilled through the substrate 210 at the central point of the area where the semiconductor chip 220 is mounted.
  • the solder mask 240 is formed with a mold-buffering opening 242 at the exit of the vent hole 211 , and the mold-buffering opening 242 is dimensioned to be sufficiently greater in width than the inside diameter of the vent hole 211 in the substrate 210 , preferably to a height of 50 ⁇ m (micrometer) and a width of from 0.3 mm to 1.0 mm (millimeter).
  • the mold-buffering opening 242 is circularly shaped.
  • FIG. 3 shows another embodiment of the invention, in which the mold-buffering opening (here designated by the reference numeral 243 ) is substantially cross-shaped. Compared to the embodiment of FIG. 2D, the mold-buffering opening 243 has a greater area that can provide an increased level of mold-buffering effect to the encapsulation material.
  • the semi-finished FCBGA package assembly is disposed in a molding tool (not shown), and a encapsulation material, such as epoxy resin, is injected into the molding tool (not shown) to form an encapsulation body 250 to encapsulate the semiconductor chip 220 .
  • a encapsulation material such as epoxy resin
  • the encapsulation material will also infiltrate into the flip-chip undergap 220 a .
  • the air in the flip-chip undergap 220 a can escape to the outside atmosphere, thus allowing the encapsulation material to infiltrate unresistingly into the entire flip-chip undergap 220 a and thereby form a molded underfill layer 222 between the semiconductor chip 220 and the substrate 210 .
  • the invention provides a method for fabricating a FCBGA package with molded underfill, which is characterized by the forming of a mold-buffering opening in the solder mask at the exit of the vent hole in the substrate, wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole, so that during molding process when the encapsulation material flows to the exit of the vent hole, it can be confined within the mold-buffering opening, thereby preventing it from flashing to nearby solder-ball pads.
  • the invention allows the resulted FCBGA package to be assured in the quality of its outer appearance and the bonding between the solder-ball pads and the subsequently attached solder balls thereon.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)

Abstract

A method of fabricating a FCBGA (Flip-Chip Bal-Grid-Array) package with molded underfill is proposed, which is characterized by the forming of a mold-buffering opening in the solder mask at the exit of the vent hole in the substrate, wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole, so that during molding process when the encapsulation material infiltrates to the exit of the vent hole, it can be confined within the mold-buffering opening, thereby preventing it from flashing to nearby solder-ball pads. Since there would substantially exist no mold flash over the exposed surface of the solder mask and the solder-ball pads, the resulted FCBGA package would be assured in the quality of its outer appearance and the bonding between the solder-ball pads and the subsequently attached solder balls thereon.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • This invention relates to integrated circuit packaging technology, and more particularly, to a method of fabricating a FCBGA Flip-Chip Ball-Grid-Array) package with molded underfill. [0002]
  • 2. Description of Related Art [0003]
  • BGA (Ball Grid Array) is an advanced type of integrated circuit packaging technology which is characterized by the use of a substrate whose front side is mounted with a semiconductor chip and whose back side is mounted with a grid array of solder balls. During SMT (Surface Mount Technology) process, the BGA package cart be mechanically bonded and electrically coupled to a printed circuit board (PCB) by means of these solder balls. [0004]
  • FCBGA (Flip-Chip Ball-Grid-Array) is a more advanced type of BGA technology which is characterized by that the semiconductor chip is mounted in an upside-down (i.e., clip chip) manner over the substrate and bonded to the same by means of a plurality of solder bumps attached to the I/O pads thereon. [0005]
  • As the flip chip is readily bonded in position over the substrate, however, an undergap would be undesirably left between the flip chip and the substrate. If this flip-chip undergap is not underfilled, it would easily cause the flip chip to suffer from fatigue cracking and electrical failure due to thermal stress when the entire package structure is being subjected to high-temperature conditions. As a solution to this problem, it is an essential step in flip-chip package fabrication to fill up the flip-chip undergap with an electrically-insulative material into the flip-chip undergap. The underfilled material, when hardened, can serve as a mechanical reinforcement for the flip chip to cope against thermal stress. [0006]
  • Conventionally, there are many methods that can be used to perform the above-mentioned flip-chip underfill process. One method is the molded-underfill process, which can fill the flip-chip undergap incidentally through the molding process to fabricate the required encapsulation body (or called molded compound). One example of the molded-underfill process is depicted in the following with reference to FIGS. [0007] 1A-1D (note that FIGS. 1A-1D are simplified schematic diagrams showing only the parts related to the invention; the actual layout on the FCBGA package may be much more complex).
  • FIG. 1A is a schematic sectional diagram showing a semi-finished FCBGA package assembly before molding; and FIG. 1B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 1A. As shown, the semi-finished FCBGA package assembly includes: (a) a [0008] substrate 110 having a front surface 110 a and a back surface 110 b; (b) a semiconductor chip 120 mounted in an upside-down (i.e., flip chip) manner by means of a plurality of solder bumps 121 over the front surface 110 a of the substrate 110; (c) an array of solder-ball pads 130 formed over the back surface 110 b of the substrate 110, which are used for subsequent attachment of an array of solder balls (not shown) thereon; and (d) a solder mask 140 which is predefined with a plurality of openings 141 to expose the solder-ball pads 130.
  • As the [0009] semiconductor chip 120 is readily mounted in position over the substrate 110, however, a flip-chip undergap 120 a would be undesirably left between the semiconductor chip 120 and the substrate 110. If this flip-chip undergap 120 a is not underfilled, it would easily cause the semiconductor chip 120 to suffer from fatigue cracking and electrical failure due to thermal stress when the entire package structure is being subjected to high-temperature conditions. One solution to this problem is to perform a molded-underfill process.
  • To facilitate the molded-underfill process, it is required to drill a [0010] vent hole 111 through the substrate 110 and the solder mask 140 at the central point of the area where the semiconductor chip 120 is mounted. Conventionally, the vent hole 111 is formed by drilling through the vent hole 111 and the solder mask 140, so that the part of the vent hole 111 in the solder mask 140 is equal in inside diameter as the part in the substrate 110.
  • Referring further to FIG. 1C together with FIG. 1D, during the molding process, the semi-finished FCBGA package assembly is disposed in a molding tool (not shown), and an encapsulation material, such as epoxy resin, is injected into the molding tool (not shown) to form an [0011] encapsulation body 150 to encapsulate the semiconductor chip 120.
  • During the forgoing molding process, the encapsulation material will also infiltrate into the flip-chip undergap [0012] 120 a. Owing to the provision of the vent hole 111, the air in the flip-chip undergap 120 a can escape to the outside atmosphere, thus allowing the encapsulation material to infiltrate unresistingly into the entire flip-chip undergap 120 a and thereby form a molded underfill layer 122 between the semiconductor chip 120 and the substrate 110.
  • One problem to the foregoing molded-underfill process, however, is that the encapsulation material would further infiltrate all the way through the [0013] vent hole 111 to the bottom side of the solder mask 140 (the marching path is indicated by the arrows in FIG. 1C), and thus flash over the exposed surface of the solder mask 140 and possibly over the nearby solder-ball pads 130. Since the encapsulation material is electrically-insulative, the mold flash over the solder-ball pads 130 would degrade the bonding between the solder-ball pads 130 and the subsequently attached solder balls (not shown) thereon.
  • Related patents, include, for example, the U.S. Pat. No. 6,038,136 entitled “CHIP PACKAGE WITH MOLDED UNDERFILL”. This patent discloses a FCBGA package that is underfilled through molded-underfill process. The utilization of this patent, however, still has the above-mentioned problem of mold flash. [0014]
    • SUMMARY OF THE INVENTION
  • It is therefore an objective of this invention to provide a method for fabricating a FCBGA package with molded underfill, which can help to prevent mold flash over exposed surface of the resulted package through the vent hole, so as to assure the quality of the outer appearance of the resulted package. [0015]
  • It is another objective of this invention to provide a method for fabricating a FCBGA package with molded underfill, which can help to prevent mold flash over exposed surface of the resulted package, so as to assure the quality of the bonding between the solder-ball pads and the solder balls attached thereon. [0016]
  • In accordance with the foregoing and other objectives, the invention proposes an improved method for fabricating a FCBGA package with molded underfill [0017]
  • Broadly recited, the method of the invention comprises the following steps. (1) preparing a substrate having a front surface and a back surface; the substrate being formed with a vent hole at a predefined location; the vent hole having an exit in the back surface of the substrate; (2) forming a plurality of solder-ball pads over the back surface of the substrate; (3) forming a solder mask over the back surface of the substrate; wherein the solder mask is predefined with an array of pad openings to expose the solder-ball pads and a mold-buffering opening aligned to the vent hole; and wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole; (4) mounting a flip chip over the front surface of the substrate; wherein a flip-chip undergap is left between the flip chip and the substrate; and (5) performing a molding process to form an encapsulation body through the injection of a encapsulation material to encapsulate the flip chip; wherein the vent hole allows the air in the flip-chip undergap to escape to the outside atmosphere, thereby allowing the encapsulation material to infiltrate unresistingly into the flip-chip undergap and form a molded-underfill layer; and wherein as the encapsulation material flows to the exit of the vent hole, the encapsulation material is contained with the solder mask's mold-buffering opening. [0018]
  • By the invention, there would substantially exist no mold flash over the exposed surface of the solder mask and the solder-ball pads; and therefore, the resulted FCBGA package would be assured in the quality of its outer appearance and the bonding effect between the solder-ball pads and the subsequently attached solder balls thereon.[0019]
    • BRIEF DESCRIPTION OF DRAWINGS
  • The invention can be more fully understood by reading the following detailed description of the preferred embodiments, with reference made to the accompanying drawings, wherein: [0020]
  • FIG. 1A (PRIOR ART) is a schematic sectional diagram showing a semi-finished FCBGA package assembly before molding; [0021]
  • FIG. 1B (PRIOR ART) shows a bottom view of the semi-finished FCBGA package assembly of FIG. 1A; [0022]
  • FIG. 1C (PRIOR ART) is a schematic sectional diagram showing the semi-finished FCBGA package assembly of FIG. 1A after molding; [0023]
  • FIG. 1D (PRIOR ART) shows a bottom view of the molded FCBGA package assembly of FIG. 1C; [0024]
  • FIG. 2A is a schematic sectional diagram showing a semi-finished FCBGA package assembly configured according to the invention before molding; [0025]
  • FIG. 2B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 2A; [0026]
  • FIG. 2C is a schematic sectional diagram showing the semi-finished FCBGA package assembly of FIG. 2A after molding; [0027]
  • FIG. 2D shows a bottom view of the molded FCBGA package assembly of FIG. 2C; [0028]
  • FIG. 3 shows another embodiment of the invention. [0029]
    • DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
  • The method according to the invention for fabricating a FCBGA package with molded underfill is disclosed in full details by way of preferred embodiments in the following with reference to FIGS. [0030] 2A-2D and FIG. 3.
  • FIG. 2A is a schematic sectional diagram showing a semi-finished FCB GA package assembly before molding; and FIG. 2B shows a bottom view of the semi-finished FCBGA package assembly of FIG. 2A. As shown, the semi-finished FCBGA package assembly includes: (a) a [0031] substrate 210 having a front surface 210 a and a back surface 210 b; (b) a semiconductor chip 220 mounted in an upside-down (i.e., flip chip) manner by means of a plurality of solder bumps 221 over the front surface 210 a of the substrate 210; (c) an array of solder-ball pads 230 formed over the back surface 210 b of the substrate 210, which are used for subsequent attachment of an array of solder balls (not shown) thereon; and (d) a solder mask 240 which is predefined with a plurality of pad openings 241 to expose the solder-ball pads 230.
  • As the [0032] semiconductor chip 220 is readily mounted in position over the substrate 210, however, a flip-chip undergap 220 a would be undesirably left between the semiconductor chip 220 and the substrate 210. To facilitate molded underfill to the flip-chip undergap 220 a, a vent hole 211 is drilled through the substrate 210 at the central point of the area where the semiconductor chip 220 is mounted.
  • It is a characteristic feature of the invention that the [0033] solder mask 240 is formed with a mold-buffering opening 242 at the exit of the vent hole 211, and the mold-buffering opening 242 is dimensioned to be sufficiently greater in width than the inside diameter of the vent hole 211 in the substrate 210, preferably to a height of 50 μm (micrometer) and a width of from 0.3 mm to 1.0 mm (millimeter). In the embodiment of FIG. 2D, the mold-buffering opening 242 is circularly shaped.
  • FIG. 3 shows another embodiment of the invention, in which the mold-buffering opening (here designated by the reference numeral [0034] 243) is substantially cross-shaped. Compared to the embodiment of FIG. 2D, the mold-buffering opening 243 has a greater area that can provide an increased level of mold-buffering effect to the encapsulation material.
  • Referring further to FIG. 2C and FIG. 2D, during the molding process, the semi-finished FCBGA package assembly is disposed in a molding tool (not shown), and a encapsulation material, such as epoxy resin, is injected into the molding tool (not shown) to form an [0035] encapsulation body 250 to encapsulate the semiconductor chip 220.
  • During the forgoing molding process, the encapsulation material will also infiltrate into the flip-[0036] chip undergap 220 a. Owing to the provision of the vent hole 211, the air in the flip-chip undergap 220 a can escape to the outside atmosphere, thus allowing the encapsulation material to infiltrate unresistingly into the entire flip-chip undergap 220 a and thereby form a molded underfill layer 222 between the semiconductor chip 220 and the substrate 210.
  • As the encapsulation material further infiltrate all the way through the [0037] vent hole 211 to the mold-buffering opening 242 of the solder mask 240 (the marching path is indicated by the arrows in FIG. 2C), it would be significantly slowed in flow speed and increased in viscosity, and therefore confined within the mold-buffering opening 242 and would hardly flash to the nearby solder-ball pads 230.
  • As the molding process is completed, it can be seen that no mold flash would exist over the exposed surface of the [0038] solder mask 240 and the solder-ball pads 230. Therefore, the resulted FCBGA package would be assured in the quality of its outer appearance and the bonding between the solder-ball pads 230 and the subsequently attached solder balls (not shown) thereon.
  • Conclusion [0039]
  • In conclusion, the invention provides a method for fabricating a FCBGA package with molded underfill, which is characterized by the forming of a mold-buffering opening in the solder mask at the exit of the vent hole in the substrate, wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole, so that during molding process when the encapsulation material flows to the exit of the vent hole, it can be confined within the mold-buffering opening, thereby preventing it from flashing to nearby solder-ball pads. Compared to the prior art, the invention allows the resulted FCBGA package to be assured in the quality of its outer appearance and the bonding between the solder-ball pads and the subsequently attached solder balls thereon. [0040]
  • The invention has been described using exemplary preferred embodiments. However, it is to be understood that the scope of the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements. The scope of the claims, therefore, should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements. [0041]

Claims (9)

What is claimed is:
1. A method for fabricating a FCBGA package, comprising the steps of:
(1) preparing a substrate having a front surface and a back surface; the substrate being formed with a vent hole at a predefined location; the vent hole having an entrance in the front surface and an exit in the back surface of the substrate;
(2) forming a plurality of solder-ball pads over the back surface of the substrate;
(3) forming a solder mask over the back surface of the substrate;
wherein the solder mask is predefined with an array of pad openings to expose the solder-ball pads and a mold-buffering opening aligned to the vent hole;
and wherein the mold-buffering opening is dimensioned to be greater in width than the inside diameter of the vent hole;
(4) mounting a flip chip over the front surface of the substrate; wherein a flip-chip undergap is left between the flip chip and the substrate; and
(5) performing a molding process to form an encapsulation body through the injection of a encapsulation material to encapsulate the flip chip;
wherein the vent hole allows the air in the flip-chip undergap to escape to the outside atmosphere, thereby allowing the encapsulation material to infiltrate unresistingly into the flip-chip undergap and form a molded-underfill layer;
and wherein as the encapsulation material flows to the exit of the vent hole, the encapsulation material is contained with the solder mask's mold-buffering opening.
2. The method of claim 1, wherein the mold-buffering opening is dimensioned to a height of 50 μm and a width of from 0.3 mm to 1.0 mm.
3. The method of claim 1, wherein the mold-buffering opening in the solder mask is circularly-shaped.
4. The method of claim 1, wherein the mold-buffering opening in the solder mask is substantially cross-shaped.
5. The method of claim 1, wherein the encapsulation material is epoxy resin.
6. A method for fabricating a FCBGA package, comprising the steps of:
(1) preparing a substrate having a front surface and a back surface; the substrate being formed with a vent hole at a predefined location; the vent hole having an entrance in the front surface and an exit in the back surface of the substrate;
(2) forming a plurality of solder-ball pads over the back surface of the substrate;
(3) forming a solder mask over the back surface of the substrate;
wherein the solder mask is predefined with an array of pad openings to expose the solder-ball pads and a mold-buffering opening aligned to the vent hole;
and wherein the mold-buffering opening is dimensioned to a height of 50 μm and a width of from 0.3 mm to 1.0 mm greater than the inside diameter of the vent hole;
(4) mounting a flip chip over the front surface of the substrate, wherein a flip-chip undergap is left between the flip chip and the substrate; and
(5) performing a molding process to form an encapsulation body through the injection of a encapsulation material to encapsulate the flip chip;
wherein the vent hole allows the air in the flip-chip undergap to escape to the outside atmosphere, thereby allowing the encapsulation material to infiltrate unresistingly into the flip-chip undergap and form a molded-underfill layer;
and wherein as the encapsulation material flows to the exit of the vent hole, the encapsulation material is contained with the solder mask's mold-buffering opening.
7. The method of claim 6, wherein the mold-buffering opening in the solder mask is circularly-shaped.
8. The method of claim 6, wherein the mold-buffering opening in the solder mask is substantially cross-shaped.
9. The method of claim 6, wherein the encapsulation material is epoxy resin.
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