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US20020076874A1 - Method for epitaxial bipolar bicmos - Google Patents

Method for epitaxial bipolar bicmos Download PDF

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Publication number
US20020076874A1
US20020076874A1 US09/439,067 US43906799A US2002076874A1 US 20020076874 A1 US20020076874 A1 US 20020076874A1 US 43906799 A US43906799 A US 43906799A US 2002076874 A1 US2002076874 A1 US 2002076874A1
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Prior art keywords
layer
forming
protective layer
bipolar
substrate
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US6448124B1 (en
Inventor
Douglas D. Coolbaugh
James S. Dunn
Peter J. Geiss
Peter B. Gray
David L. Harame
Kathryn T. Schonenberg
Stephen A. St. Onge
Seshadri Subbanna
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GlobalFoundries Inc
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Assigned to INTERNATIONAL BUSINESS MACHINES CORPORATION reassignment INTERNATIONAL BUSINESS MACHINES CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: HARAME, DAVID L., COOLBAUGH, DOUGLAS D., DUNN, JAMES S., GEISS, PETER J., GRAY, PETER B., SCHONENBERG, KATHRYN T., ST. ONGE, STPHEN A., SUBBANNA, SESHADRI
Priority to TW089116474A priority patent/TW516204B/en
Priority to IL13813400A priority patent/IL138134A/en
Priority to MYPI20004901A priority patent/MY124964A/en
Priority to GB0027232A priority patent/GB2362508B/en
Priority to KR1020000065750A priority patent/KR100352079B1/en
Priority to JP2000340616A priority patent/JP3516916B2/en
Priority to CNB001309269A priority patent/CN1157780C/en
Publication of US20020076874A1 publication Critical patent/US20020076874A1/en
Publication of US6448124B1 publication Critical patent/US6448124B1/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76224—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using trench refilling with dielectric materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/763—Polycrystalline semiconductor regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

Definitions

  • the present invention relates to a method of fabricating integrated circuits and, in particular to a method of forming field effect transistors (FETs) and bipolar devices on the same substrate. More specifically, the present invention provides an integration scheme that is capable of fabricating a base-after gate BiCMOS (i.e., bipolar device and complementary metal oxide semiconductor (CMOS) device) integrated circuit which solves the problems typically associated with prior art integration schemes.
  • BiCMOS complementary metal oxide semiconductor
  • Base-during gate processes are described, for example, in D. L. Harame, et al. “Si/SiGe Epitaxial-Base Transistors-Part I: Materials Physics and Circuits”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; D. L. Harame, et al., “Si/SiGe Epitaxial-Base Transistors-Part II: Process Integration and Analog Applications”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; and D.
  • the gate polysilicon is formed at the same time as the base epitaxial silicon is grown.
  • An alternative method of fabricating BiCMOS integrated circuits is to employ a base-after gate process.
  • the gate polysilicon is formed before the base epitixial silicon is grown.
  • Such a process is described, for example, in U.S. Pat. No. 5,665,615 to Anmo and U.S. Pat. No. 5,665,616 to Kimura, et al.
  • a first problem is controlling the base outdiffusion during CMOS source/drain (S/D) and lightly doped drain (LDD) anneals.
  • a second problem is how to provide a high quality epitaxial surface for base growth; and a third problem is how to protect the CMOS device during bipolar device formation.
  • One object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which the FETs and bipolar devices are fabricated on the same substrate.
  • Another object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit using an integration scheme in which no thermal limitation is put on the CMOS device during bipolar device formation.
  • a still further object of the present invention is to provide a method in which a high quality surface for epitaxial base growth is provided.
  • a yet further object of the present invention is to provide a method of fabricating a BiCMOS device in which the CMOS devices are protected during bipolar device formation and vice versa.
  • An additional object of the present invention is to provide a method of fabricating a BiCMOS device in which bipolar films are not left on the FET devices.
  • the method of the present invention comprises the steps of:
  • a portion of the second protective layer remains in the structure covering a portion of said bipolar device.
  • a portion of the first protective layer remains over the FET device or portions of the first and second protective layers remain in the structure after fabrication.
  • FIG. 1 is a flow chart illustrating the integration scheme, including the various processing steps that are employed in the present invention.
  • FIGS. 2 A- 2 M are cross-sectional views showing the fabrication of bipolar and NMOS devices on the same substrate using the method of the present invention.
  • FIG. 1 is a flow chart illustrating the basic processing steps of the integration scheme of the present invention. The various steps shown in the flow chart will be described in more detail by referring to FIGS. 2 A- 2 M and the discussion to follow hereinbelow.
  • FIGS. 2 A- 2 M are cross-sections showing the various processing steps that are employed in the present invention in fabricating a BiCMOS structure containing bipolar devices and NMOS devices.
  • NMOS device is shown and illustrated the present invention can be used in fabricating PMOS devices.
  • PMOS device is formed, the same sequence of processing steps as described hereinbelow is employed except for the source/drain regions which are formed after completion of the bipolar devices.
  • the first step of the present invention involves forming a first portion of a bipolar device in first regions of a substrate.
  • This step of the present invention is shown in FIG. 2A (which corresponds to process step 1 of FIG. 1).
  • the structure shown in FIG. 2A comprises a P-substrate 10 , a buried N+ region 12 , an N-epitaxial layer 14 and a patterned masking layer 16 .
  • the N+ region becomes the subcollector region of the bipolar device.
  • the structure shown in FIG. 2A is fabricated using conventional bipolar processing steps that are well known to those skilled in the art. Moreover, conventional materials are used in fabricating the same.
  • the substrate is composed of any semiconducting material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds. Layered substrates comprising the same or different semiconducting material, e.g. Si/SiGe, are also contemplated herein. Of these materials, it is preferred that the substrate be composed of Si. Although a p-doped substrate is shown, n-doped substrates are also contemplated herein.
  • the structure shown in FIG. 2A is fabricated as follows: An oxide film, e.g., SiO 2 , (not shown in the drawings) is formed on the surface of substrate 10 using a conventional deposition process such as chemical vapor deposition (CVD), plasma-enhanced CVD or sputtering, or alternatively the oxide layer is grown thermally.
  • the buried N+ region is formed in the substrate by a conventional ion implantation step.
  • the buried region is activated by employing a conventional anneal (rapid thermal anneal (RTA) or oven anneal) and then the N-epitaxial layer is formed utilizing a conventional epitixial growing process.
  • a layer of masking material, e.g. Si 3 N 4 is formed on the surface of the N-epitaxial layer utilizing a conventional deposition process such as CVD and then it is patterned by conventional lithography and etching (reactive ion etching (RIE)).
  • RIE reactive ion etching
  • FIG. 2A The above processing steps lead to the formation of the structure shown in FIG. 2A.
  • the drawings of the present application include labels which indicate the region wherein the NMOS device is to be fabricated and the region wherein the bipolar device is to be fabricated.
  • the drawings show only one NMOS device region and one bipolar device region, any number of NMOS device regions and bipolar device regions may be formed utilizing the method of the present invention.
  • the patterned masking layer is employed in the present invention to etch deep trench isolation regions 18 for the bipolar devices.
  • the deep trench isolation is shown complete in FIG. 2B (corresponding to step 2 of FIG. 1).
  • the deep trench isolation region is formed by etching a trench in the structure utilizing a conventional dry etching process such as RIE or plasma etching.
  • the deep trench is lined with a conventional deep trench liner material 20 , e.g. an oxide, and then CVD or another like deposition process is used to fill the deep trench with polysilicon or another like dielectric material 22 .
  • a conventional planarization process such as chemical-mechanical polishing (CMP) is used to provide the planar structure shown in FIG. 2B.
  • CMP chemical-mechanical polishing
  • STI shallow trench isolation
  • CMOS devices and the bipolar devices, as well as the collector reach-through for the bipolar devices are formed in the structure shown in FIG. 2B.
  • FIGS. 2 C- 2 F of the present application are illustrated in FIGS. 2 C- 2 F of the present application.
  • a masking layer 24 is formed on the surface of the structure utilizing conventional deposition processes such as CVD. This masking layer may be composed of the same or different material as the previous masking layer.
  • Masking layer 24 is patterned and shallow trenches 26 are then etched through exposed portions of masking layer 24 providing the structure shown in FIG. 2D.
  • the shallow trenches are then subjected to conventional processes well known to those skilled in the art that are capable of providing STI regions 28 , See FIG. 2E.
  • the STI procedure may include: forming a liner in the shallow trench prior STI dielectric fill; and densifying the STI dielectric.
  • a reach-through region (or collector) 30 for subcollector 12 is formed in the bipolar device region utilizing conventional procedures that are capable of forming the same. This includes ion implantation and annealing.
  • the structure that is formed after STI and reach-through formation is shown in FIG. 2F.
  • a first protective layer is formed over a portion of the bipolar device region.
  • first protective layer 32 is formed over N-epitaxial layer 14 (and overlapping the deep trench) upon which the bipolar device will be formed.
  • One type of protective layer employed in the present invention for protecting the bipolar device region comprises a Si 3 N 4 layer.
  • the Si 3 N 4 layer typically has a thickness of from about 10 to about 1000 ⁇ , with a thickness of from about 500 to about 800 ⁇ being highly preferred.
  • the Si 3 N 4 layer may be formed by any conventional deposition process, with a low pressure CVD process being highly preferred. It is noted that the present invention contemplates the use of other protective materials besides the Si 3 N 4 layer mentioned above that are capable of protecting the bipolar device region during CMOS fabrication.
  • the FET devices After protecting a portion of the bipolar device region with a protective layer, the FET devices are completely fabricated, with the exception of PFET source/drain regions which occur after completion of the bipolar device regions; See FIG. 1, step 5 .
  • the FET devices are formed utilizing conventional processing steps that are capable of fabricating transistor devices. Included in the conventional transistor processing steps are: N-well for pFET photolithography, N-well implant, PFET thin oxide tailor implant, P-well for nFET photolithography, P-well implant, n-FET thin oxide tailor implant, dual gate oxide photolithography, dual gate oxide regrowth, FET gate photolithography, FET gate etch, thermal oxide spacer formation, nFET extension photolithography, nFET extension implant (lightly doped drains (LDD)), first spacer formation, pFET extension photolithography, pFET extension (LDD), second spacer deposition, second spacer etch, nFET S/D implant photolithography, nFET S/D anneals.
  • LDD lightly doped drains
  • the FET device includes P-well 36 , S/D regions 38 , S/D extensions 40 , gate region (gate and gate oxide) 44 , spacers 46 .
  • the spacers depicted in the drawings include various layers that are formed on the sidewalls of the gate region as well as a horizontal layer that is formed on the substrate.
  • a second protective layer 50 is formed over the structure shown in FIG. 2H providing the structure shown in FIG. 2I. Specifically, the second protective layer is formed over the FET device and the reach-through region of the bipolar device. Second protective layer 50 may be composed of a single layered material or multiple layers of the same or different materials can be used as second protective layer 50 , e.g. the second protective layer could be composed of an oxide layer and polysilicon layer. For simplicity, reference numeral 50 is used herein to include a single layer protective layer or a multilayered protective layer.
  • any material or materials that are capable of protecting the FET devices during completion of the bipolar devices may be employed in the present invention and any known deposition process may be employed in forming a layer (or multilayers) of the same on the structure.
  • the second protective layer be composed of an oxide which is deposited by a plasma-enhanced CVD process.
  • the thickness of the second protective layer(s) may vary, but typically the thickness of the second protective layer(s) is from about 100 to about 500 ⁇ , with a thickness of from about 150 to about 250 ⁇ being highly preferred.
  • the bipolar devices are then completed, See FIG. 2J, utilizing conventional processing steps that are capable of completing the fabrication of the bipolar devices. These processing steps create additional films that overlay the second protective layer. Specifically, the bipolar devices are completed by growing an epitaxial base and then forming any bipolar emitter device thereon.
  • the bipolar devices contemplated in the present invention can be non-aligned or self-aligned.
  • One preferred process that may be employed in the present invention in forming the bipolar devices includes: etching a bipolar window through second protective layer 50 and first protective layer 32 that overlay a portion of collector region 12 , forming an emitter pedestal SiGe in the bipolar window, extrinsic base formation, second collector implant, define emitter polysilicon and extrinsic base polysilicon. It is again emphasized that the above process description represents one technique that can be employed in the present invention in forming the bipolar devices. Other techniques that are well known in the art in forming bipolar devices can also be employed in the present invention.
  • FIG. 2J comprises the structure of FIG. 2I containing N-layer 52 , P+ polysilicon layer 54 (it is noted that in FIG. 2J reference numeral 54 b represents the P+ polysilicon formed on the bipolar device) and N+ polysilicon layer 56 , wherein layer 52 , 54 , 54 b and 56 form the completed bipolar device. It is noted that during the window etch, substantially all of the first protective layer is removed from the structure. In one embodiment of the present invention, some of the first protective layer remains in the bipolar device region of the structure.
  • step 7 portions of bipolar layer 54 and all of the second protective layer are removed from the structure utilizing a conventional etch process which is highly selective in removing those two layers without attacking the underlying structure. If PFETs are previously formed, then the PFET S/D regions are formed following the above etch step by conventional implantation and activation anneal. These processing steps produce the structure shown in FIG. 2K.
  • step 8 metal polysilicon contacts 58 are formed on the S/D implants and gates as well as the bipolar collector and base regions, See FIG. 2L.
  • the contacts are formed utilizing conventional processing steps well known in the art that are capable of forming the contact regions. Included in these contact formation processing steps include: resistor silicide block mask, Ti deposition and Ti anneal.
  • a passivation layer 60 and dielectric layer 62 are formed over the FET and bipolar devices and metal vias or contact studs 64 are formed through those layers to metal polysilicon contacts 58 .
  • Conventional deposition processes are used in forming the passivation and dielectric layers and the contact openings are formed by conventional lithography and etching. The contact openings are filled utilizing a conventional deposition process and, if needed, a conventional planarization process is employed.
  • Any conventional passivation material such as Si 3 N 4 or a polyimide may be employed in forming layer 60 ; and any conventional dielectric material such as SiO 2 or Si 3 N 4 may be employed in forming layer 62 .
  • any conventional conductive metal such as Ti, W, Cu, Cr and Pt may be employed in the present invention.
  • SiGe bipolar device While the preferred embodiment illustrated above is described for using a SiGe bipolar device, the present invention is not limited to SiGe device, but includes other epitaxial devices.

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Abstract

A method of forming a BiCMOS integrated circuit is provided which comprises the steps of: (a) forming a first portion of a bipolar device in first regions of a substrate; (b) forming a first protective layer over said first regions to protect said first portion of said bipolar devices; (c) forming field effect transistor devices in second regions of said substrate; (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor devices; (e) removing said first protective layer; (f) forming a second portion of said bipolar devices in said first regions of said substrate; and (g) removing said second protective layer.

Description

    FIELD OF THE INVENTION
  • The present invention relates to a method of fabricating integrated circuits and, in particular to a method of forming field effect transistors (FETs) and bipolar devices on the same substrate. More specifically, the present invention provides an integration scheme that is capable of fabricating a base-after gate BiCMOS (i.e., bipolar device and complementary metal oxide semiconductor (CMOS) device) integrated circuit which solves the problems typically associated with prior art integration schemes. [0001]
    • BACKGROUND OF THE INVENTION
  • In the field of semiconductor device manufacturing, it is well known to fabricate BiCMOS integrated circuits using a so-called base-during gate process. Base-during gate processes are described, for example, in D. L. Harame, et al. “Si/SiGe Epitaxial-Base Transistors-Part I: Materials Physics and Circuits”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; D. L. Harame, et al., “Si/SiGe Epitaxial-Base Transistors-Part II: Process Integration and Analog Applications”, IEEE Trans. Elect. Devices, pp. 469-482, March 1995; and D. Ahlgren, et al., “A SiGe HBT BICMOS Technology for Mixed Signal RF Applications”, Proc. of the 1997 BCTM, pp 195-197, 1997. In such base-during gate processes, the gate polysilicon is formed at the same time as the base epitaxial silicon is grown. [0002]
  • An alternative method of fabricating BiCMOS integrated circuits is to employ a base-after gate process. In this process, the gate polysilicon is formed before the base epitixial silicon is grown. Such a process is described, for example, in U.S. Pat. No. 5,665,615 to Anmo and U.S. Pat. No. 5,665,616 to Kimura, et al. [0003]
  • Several problems are evident in using such prior art processes. A first problem is controlling the base outdiffusion during CMOS source/drain (S/D) and lightly doped drain (LDD) anneals. A second problem is how to provide a high quality epitaxial surface for base growth; and a third problem is how to protect the CMOS device during bipolar device formation. When a base-after gate integration scheme is employed, the following two additional manufacturing requirements must be taken into consideration: First, FET spacer structures must not be produced on the bipolar devices; and secondly, bipolar films must not be left on the FET devices after fabricating the same. [0004]
  • In view of the aforementioned drawbacks with prior art integration schemes for BiCMOS fabrication, there is a continued need for developing a new and improved base-after gate integration process wherein all of the above-mentioned problems and requirements have been met. [0005]
    • SUMMARY OF THE INVENTION
  • One object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit in which the FETs and bipolar devices are fabricated on the same substrate. [0006]
  • Another object of the present invention is to provide a method of fabricating a BiCMOS integrated circuit using an integration scheme in which no thermal limitation is put on the CMOS device during bipolar device formation. [0007]
  • A still further object of the present invention is to provide a method in which a high quality surface for epitaxial base growth is provided. [0008]
  • A yet further object of the present invention is to provide a method of fabricating a BiCMOS device in which the CMOS devices are protected during bipolar device formation and vice versa. [0009]
  • An additional object of the present invention is to provide a method of fabricating a BiCMOS device in which bipolar films are not left on the FET devices. [0010]
  • These and other objects and advantages are met by forming portions of bipolar devices on a substrate, protecting the portions with a protective layer while forming FET devices, and protecting the FET devices while forming other portions of the bipolar devices. Specifically, the method of the present invention comprises the steps of: [0011]
  • (a) forming a first portion of a bipolar device in first regions of a substrate; [0012]
  • (b) forming a first protective layer over said first regions to protect said first portion of said bipolar device; [0013]
  • (c) forming a field effect transistor device in second regions of said substrate; [0014]
  • (d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor device; [0015]
  • (e) removing said first protective layer; [0016]
  • (f) forming a second portion of said bipolar device in said first regions of said substrate; and [0017]
  • (g) removing said second protective layer. [0018]
  • In one embodiment of the present invention, a portion of the second protective layer remains in the structure covering a portion of said bipolar device. In other embodiments of the present invention, a portion of the first protective layer remains over the FET device or portions of the first and second protective layers remain in the structure after fabrication. [0019]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a flow chart illustrating the integration scheme, including the various processing steps that are employed in the present invention. [0020]
  • FIGS. [0021] 2A-2M are cross-sectional views showing the fabrication of bipolar and NMOS devices on the same substrate using the method of the present invention.
  • DETAILED DESCRIPTION OF THE INVENTION [0022]
  • The present invention which provides a method of fabricating a BiCMOS integrated circuit using a base-after gate processing scheme will now be described in more detail by referring to the drawings that accompany the present application. It should be noted that in the accompanying drawings like and corresponding elements are referred to by like reference numerals. [0023]
  • Reference is first made to FIG. 1 which is a flow chart illustrating the basic processing steps of the integration scheme of the present invention. The various steps shown in the flow chart will be described in more detail by referring to FIGS. [0024] 2A-2M and the discussion to follow hereinbelow.
  • Insofar as FIGS. [0025] 2A-2M are concerned, those figures are cross-sections showing the various processing steps that are employed in the present invention in fabricating a BiCMOS structure containing bipolar devices and NMOS devices. Although an NMOS device is shown and illustrated the present invention can be used in fabricating PMOS devices. In embodiments wherein a PMOS device is formed, the same sequence of processing steps as described hereinbelow is employed except for the source/drain regions which are formed after completion of the bipolar devices.
  • As stated above, the first step of the present invention involves forming a first portion of a bipolar device in first regions of a substrate. This step of the present invention is shown in FIG. 2A (which corresponds to process [0026] step 1 of FIG. 1). Specifically, the structure shown in FIG. 2A comprises a P-substrate 10, a buried N+ region 12, an N-epitaxial layer 14 and a patterned masking layer 16. The N+ region becomes the subcollector region of the bipolar device.
  • The structure shown in FIG. 2A is fabricated using conventional bipolar processing steps that are well known to those skilled in the art. Moreover, conventional materials are used in fabricating the same. For example, the substrate is composed of any semiconducting material including, but not limited to: Si, Ge, SiGe, GaAs, InAs, InP and all other III/V semiconductor compounds. Layered substrates comprising the same or different semiconducting material, e.g. Si/SiGe, are also contemplated herein. Of these materials, it is preferred that the substrate be composed of Si. Although a p-doped substrate is shown, n-doped substrates are also contemplated herein. [0027]
  • Specifically, the structure shown in FIG. 2A is fabricated as follows: An oxide film, e.g., SiO[0028] 2, (not shown in the drawings) is formed on the surface of substrate 10 using a conventional deposition process such as chemical vapor deposition (CVD), plasma-enhanced CVD or sputtering, or alternatively the oxide layer is grown thermally. The buried N+ region is formed in the substrate by a conventional ion implantation step. The buried region is activated by employing a conventional anneal (rapid thermal anneal (RTA) or oven anneal) and then the N-epitaxial layer is formed utilizing a conventional epitixial growing process. A layer of masking material, e.g. Si3N4, is formed on the surface of the N-epitaxial layer utilizing a conventional deposition process such as CVD and then it is patterned by conventional lithography and etching (reactive ion etching (RIE)).
  • The above processing steps lead to the formation of the structure shown in FIG. 2A. It is noted that the drawings of the present application include labels which indicate the region wherein the NMOS device is to be fabricated and the region wherein the bipolar device is to be fabricated. Although the drawings show only one NMOS device region and one bipolar device region, any number of NMOS device regions and bipolar device regions may be formed utilizing the method of the present invention. Also, it is possible to form BiCMOS structures containing NMOS, PMOS and bipolar devices or BiCMOS structures including PMOS and bipolar devices. [0029]
  • The patterned masking layer is employed in the present invention to etch deep [0030] trench isolation regions 18 for the bipolar devices. The deep trench isolation is shown complete in FIG. 2B (corresponding to step 2 of FIG. 1). Specifically, the deep trench isolation region is formed by etching a trench in the structure utilizing a conventional dry etching process such as RIE or plasma etching. The deep trench is lined with a conventional deep trench liner material 20, e.g. an oxide, and then CVD or another like deposition process is used to fill the deep trench with polysilicon or another like dielectric material 22. A conventional planarization process such as chemical-mechanical polishing (CMP) is used to provide the planar structure shown in FIG. 2B.
  • Next as indicated in [0031] step 3 of FIG. 1, shallow trench isolation (STI) for the CMOS devices and the bipolar devices, as well as the collector reach-through for the bipolar devices are formed in the structure shown in FIG. 2B. These processing steps are illustrated in FIGS. 2C-2F of the present application. Specifically, as is shown in FIG. 2C, a masking layer 24 is formed on the surface of the structure utilizing conventional deposition processes such as CVD. This masking layer may be composed of the same or different material as the previous masking layer. Masking layer 24 is patterned and shallow trenches 26 are then etched through exposed portions of masking layer 24 providing the structure shown in FIG. 2D.
  • The shallow trenches are then subjected to conventional processes well known to those skilled in the art that are capable of providing [0032] STI regions 28, See FIG. 2E. This includes STI dielectric fill and planarization. Optionally, the STI procedure may include: forming a liner in the shallow trench prior STI dielectric fill; and densifying the STI dielectric.
  • After completion of the STI regions, a reach-through region (or collector) [0033] 30 for subcollector 12 is formed in the bipolar device region utilizing conventional procedures that are capable of forming the same. This includes ion implantation and annealing. The structure that is formed after STI and reach-through formation is shown in FIG. 2F.
  • Next, as indicated in FIG. 1, [0034] step 4, a first protective layer is formed over a portion of the bipolar device region. Specifically, as shown in FIG. 2G, first protective layer 32 is formed over N-epitaxial layer 14 (and overlapping the deep trench) upon which the bipolar device will be formed. One type of protective layer employed in the present invention for protecting the bipolar device region comprises a Si3N4 layer. The Si3N4 layer typically has a thickness of from about 10 to about 1000 Å, with a thickness of from about 500 to about 800 Å being highly preferred. The Si3N4 layer may be formed by any conventional deposition process, with a low pressure CVD process being highly preferred. It is noted that the present invention contemplates the use of other protective materials besides the Si3N4 layer mentioned above that are capable of protecting the bipolar device region during CMOS fabrication.
  • After protecting a portion of the bipolar device region with a protective layer, the FET devices are completely fabricated, with the exception of PFET source/drain regions which occur after completion of the bipolar device regions; See FIG. 1, [0035] step 5.
  • The FET devices are formed utilizing conventional processing steps that are capable of fabricating transistor devices. Included in the conventional transistor processing steps are: N-well for pFET photolithography, N-well implant, PFET thin oxide tailor implant, P-well for nFET photolithography, P-well implant, n-FET thin oxide tailor implant, dual gate oxide photolithography, dual gate oxide regrowth, FET gate photolithography, FET gate etch, thermal oxide spacer formation, nFET extension photolithography, nFET extension implant (lightly doped drains (LDD)), first spacer formation, pFET extension photolithography, pFET extension (LDD), second spacer deposition, second spacer etch, nFET S/D implant photolithography, nFET S/D anneals. [0036]
  • These transistor processing steps form the FET device in the structure shown in FIG. 2H. Specifically, the FET device includes P-well [0037] 36, S/D regions 38, S/D extensions 40, gate region (gate and gate oxide) 44, spacers 46. The spacers depicted in the drawings include various layers that are formed on the sidewalls of the gate region as well as a horizontal layer that is formed on the substrate.
  • Next as described in FIG. 1, [0038] step 6, a second protective layer 50 is formed over the structure shown in FIG. 2H providing the structure shown in FIG. 2I. Specifically, the second protective layer is formed over the FET device and the reach-through region of the bipolar device. Second protective layer 50 may be composed of a single layered material or multiple layers of the same or different materials can be used as second protective layer 50, e.g. the second protective layer could be composed of an oxide layer and polysilicon layer. For simplicity, reference numeral 50 is used herein to include a single layer protective layer or a multilayered protective layer.
  • Any material or materials that are capable of protecting the FET devices during completion of the bipolar devices may be employed in the present invention and any known deposition process may be employed in forming a layer (or multilayers) of the same on the structure. It is preferred in the present invention that the second protective layer be composed of an oxide which is deposited by a plasma-enhanced CVD process. The thickness of the second protective layer(s) may vary, but typically the thickness of the second protective layer(s) is from about 100 to about 500 Å, with a thickness of from about 150 to about 250 Å being highly preferred. [0039]
  • After protecting the FET devices of the structure with the second protective layer, the bipolar devices are then completed, See FIG. 2J, utilizing conventional processing steps that are capable of completing the fabrication of the bipolar devices. These processing steps create additional films that overlay the second protective layer. Specifically, the bipolar devices are completed by growing an epitaxial base and then forming any bipolar emitter device thereon. The bipolar devices contemplated in the present invention can be non-aligned or self-aligned. One preferred process that may be employed in the present invention in forming the bipolar devices includes: etching a bipolar window through second [0040] protective layer 50 and first protective layer 32 that overlay a portion of collector region 12, forming an emitter pedestal SiGe in the bipolar window, extrinsic base formation, second collector implant, define emitter polysilicon and extrinsic base polysilicon. It is again emphasized that the above process description represents one technique that can be employed in the present invention in forming the bipolar devices. Other techniques that are well known in the art in forming bipolar devices can also be employed in the present invention.
  • These processing steps result in the structure shown in FIG. 2J. Specifically, FIG. 2J comprises the structure of FIG. 2I containing N-[0041] layer 52, P+ polysilicon layer 54 (it is noted that in FIG. 2J reference numeral 54 b represents the P+ polysilicon formed on the bipolar device) and N+ polysilicon layer 56, wherein layer 52, 54, 54 b and 56 form the completed bipolar device. It is noted that during the window etch, substantially all of the first protective layer is removed from the structure. In one embodiment of the present invention, some of the first protective layer remains in the bipolar device region of the structure.
  • Next as described in FIG. 1, [0042] step 7, portions of bipolar layer 54 and all of the second protective layer are removed from the structure utilizing a conventional etch process which is highly selective in removing those two layers without attacking the underlying structure. If PFETs are previously formed, then the PFET S/D regions are formed following the above etch step by conventional implantation and activation anneal. These processing steps produce the structure shown in FIG. 2K.
  • Although the drawings show removal of substantially all of the second protective layer from the structure, the present invention also contemplates leaving some of the second protective layer over the collector region of the bipolar device. [0043]
  • As described in FIG. 1, [0044] step 8, metal polysilicon contacts 58 are formed on the S/D implants and gates as well as the bipolar collector and base regions, See FIG. 2L. The contacts are formed utilizing conventional processing steps well known in the art that are capable of forming the contact regions. Included in these contact formation processing steps include: resistor silicide block mask, Ti deposition and Ti anneal.
  • Next, as shown in FIG. 1, [0045] step 9, and FIG. 2M, a passivation layer 60 and dielectric layer 62 are formed over the FET and bipolar devices and metal vias or contact studs 64 are formed through those layers to metal polysilicon contacts 58. Conventional deposition processes are used in forming the passivation and dielectric layers and the contact openings are formed by conventional lithography and etching. The contact openings are filled utilizing a conventional deposition process and, if needed, a conventional planarization process is employed.
  • Any conventional passivation material such as Si[0046] 3N4 or a polyimide may be employed in forming layer 60; and any conventional dielectric material such as SiO2 or Si3N4 may be employed in forming layer 62. Insofar as the contact studs are concerned, any conventional conductive metal such as Ti, W, Cu, Cr and Pt may be employed in the present invention.
  • While the preferred embodiment illustrated above is described for using a SiGe bipolar device, the present invention is not limited to SiGe device, but includes other epitaxial devices. [0047]
  • While the present invention has been particularly shown and described with respect to preferred embodiments thereof, it will be understood by those skilled in the art that the foregoing and other changes in form and detail may be made without departing from the spirit and scope of the present invention. It is therefore intended that the present invention not be limited to the exact forms and details described and illustrated, but fall within the scope of the appended claims. [0048]

Claims (25)

Having thus described our invention in detail, what we claim is new, and desire to secure by the letters patent is:
1. A method of forming a BiCMOS integrated circuit comprising the steps of:
(a) forming a first portion of a bipolar device in first regions of a substrate;
(b) forming a first protective layer over said first regions to protect said first portion of said bipolar device;
(c) forming a field effect transistor device in second regions of said substrate;
(d) forming a second protective layer over said second regions of said substrate to protect said field effect transistor device;
(e) removing said first protective layer;
(f) forming a second portion of said bipolar device in said first regions of said substrate; and
(g) removing said second protective layer exposing said field effect transistor device.
2. The method of claim 1 further comprising forming metal polysilicon contacts on portions of said exposed field effect transistor device and on portions of said bipolar device.
3. The method of claim 2 further comprising forming a passivation layer on said exposed field effect transistor device, said bipolar device and said metal polysilicon contacts.
4. The method of claim 3 further comprising forming a dielectric layer on said passivation layer.
5. The method of claim 4 further comprising forming contact studs through said dielectric layer and said passivation layer to said metal polysilicon contacts.
6. The method of claim 1 wherein step (a) includes providing a subcollector region in said substrate and growing epitaxial silicon on said substrate.
7. The method of claim 1 wherein step (b) includes etching trenches in said substrate, lining said trenches with a liner material, filling said trenches with a dielectric material and planarizing.
8. The method of claim 1 wherein said first protective layer comprises a Si3N4 layer.
9. The method of claim 8 wherein said Si3N4 layer is formed by low pressure CVD.
10. The method of claim 8 wherein said Si3N4 layer has a thickness of from about 10 to about 1000 Å.
11. The method of claim 10 wherein said Si3N4 layer has a thickness of from about 500 to about 800 Å.
12. The method of claim 1 wherein step (c) includes forming well implants, source/drain regions, source/drain extensions, gate oxide growth and spacer formation.
13. The method of claim 1 wherein said second protective layer is composed of a multilayer comprises a layer of an oxide and a layer of polysilicon.
14. The method of claim 1 wherein said second protective layer is composed of an oxide.
15. The method of claim 14 wherein said layer of oxide is formed by plasma-enhanced CVD.
16. The method of claim 1 wherein said second protective layer has a thickness of from about 100 to about 500 Å.
17. The method of claim 16 wherein said second protective layer has a thickness of from about 150 about 250 Å.
18. The method of claim 1 wherein step (f) includes growing an epitaxial base in a bipolar window.
19. The method of claim 18 wherein said epitaxial base is SiGe.
20. The method of claim 1 wherein step (g) includes a reactive ion etch process.
21. The method of claim 1 wherein a portion of said first protective layer is not removed.
22. The method of claim 1 wherein a portion of said second protective layer is not removed.
23. The method of claim 1 wherein a portion of said first and said second protective layers are not removed.
24. The method of claim 1 wherein a plurality of bipolar devices and field effect transistor devices are formed.
25. The method of claim 1 wherein said field effect transistor device is a PFET or an nFET.
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TW089116474A TW516204B (en) 1999-11-12 2000-08-15 Method for epitaxial bipolar BiCMOS
IL13813400A IL138134A (en) 1999-11-12 2000-08-28 Methods for epitaxial bipolar bicmos
MYPI20004901A MY124964A (en) 1999-11-12 2000-10-18 Method for epitaxial bipolar bicmos
GB0027232A GB2362508B (en) 1999-11-12 2000-11-07 Semiconductor integrated circuit fabrication
KR1020000065750A KR100352079B1 (en) 1999-11-12 2000-11-07 Method for epitaxial bipolar bicmos
JP2000340616A JP3516916B2 (en) 1999-11-12 2000-11-08 Method for forming BiCMOS
CNB001309269A CN1157780C (en) 1999-11-12 2000-11-08 Methods of fabricating epitaxial bipolar devices and complementary metal oxide semiconductor devices

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Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040132236A1 (en) * 2003-01-08 2004-07-08 International Business Machines Corporation Mos transistor
WO2005074021A1 (en) * 2004-01-31 2005-08-11 X-Fab Semiconductor Foundries Ag Passivation of deep isolating separating trenches with sunk covering layers
US20060060886A1 (en) * 2004-09-21 2006-03-23 International Business Machines Corporation METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY
US20100022056A1 (en) * 2006-08-31 2010-01-28 Nxp, B.V. Method of manufacturing a bipolar transistor
CN105390496A (en) * 2014-09-05 2016-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method therefor, and electronic device
US10698156B2 (en) * 2017-04-27 2020-06-30 The Research Foundation For The State University Of New York Wafer scale bonded active photonics interposer

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2811473B1 (en) * 2000-07-04 2003-09-05 St Microelectronics Sa METHOD FOR PRODUCING DEEP AND SHALLOW INSULATING REGIONS OF AN INTEGRATED CIRCUIT, AND CORRESPONDING INTEGRATED CIRCUIT
US6667226B2 (en) * 2000-12-22 2003-12-23 Texas Instruments Incorporated Method and system for integrating shallow trench and deep trench isolation structures in a semiconductor device
DE10221416A1 (en) * 2002-05-14 2003-11-27 Infineon Technologies Ag Method for producing an integrated circuit and integrated circuit with a bipolar transistor and a heterobipolar transistor
US7521733B2 (en) 2002-05-14 2009-04-21 Infineon Technologies Ag Method for manufacturing an integrated circuit and integrated circuit with a bipolar transistor and a hetero bipolar transistor
US7902630B2 (en) 2002-08-14 2011-03-08 Advanced Analogic Technologies, Inc. Isolated bipolar transistor
US7667268B2 (en) 2002-08-14 2010-02-23 Advanced Analogic Technologies, Inc. Isolated transistor
US8513087B2 (en) 2002-08-14 2013-08-20 Advanced Analogic Technologies, Incorporated Processes for forming isolation structures for integrated circuit devices
US7834421B2 (en) 2002-08-14 2010-11-16 Advanced Analogic Technologies, Inc. Isolated diode
US7812403B2 (en) 2002-08-14 2010-10-12 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuit devices
US8089129B2 (en) 2002-08-14 2012-01-03 Advanced Analogic Technologies, Inc. Isolated CMOS transistors
US7956391B2 (en) 2002-08-14 2011-06-07 Advanced Analogic Technologies, Inc. Isolated junction field-effect transistor
US7825488B2 (en) 2006-05-31 2010-11-02 Advanced Analogic Technologies, Inc. Isolation structures for integrated circuits and modular methods of forming the same
US6943426B2 (en) 2002-08-14 2005-09-13 Advanced Analogic Technologies, Inc. Complementary analog bipolar transistors with trench-constrained isolation diffusion
US7939420B2 (en) 2002-08-14 2011-05-10 Advanced Analogic Technologies, Inc. Processes for forming isolation structures for integrated circuit devices
US6630377B1 (en) * 2002-09-18 2003-10-07 Chartered Semiconductor Manufacturing Ltd. Method for making high-gain vertical bipolar junction transistor structures compatible with CMOS process
KR100486304B1 (en) 2003-02-07 2005-04-29 삼성전자주식회사 Method for manufacturing self-aligned BiCMOS
US6864151B2 (en) * 2003-07-09 2005-03-08 Infineon Technologies Ag Method of forming shallow trench isolation using deep trench isolation
US7329941B2 (en) * 2004-07-20 2008-02-12 International Business Machines Corporation Creating increased mobility in a bipolar device
JP2007129085A (en) * 2005-11-04 2007-05-24 Texas Instr Japan Ltd Semiconductor device and manufacturing method thereof
US20080026545A1 (en) * 2006-07-28 2008-01-31 Paul Cooke Integrated devices on a common compound semiconductor III-V wafer
KR100867977B1 (en) 2006-10-11 2008-11-10 한국과학기술원 Tissue perfusion analysis apparatus using indocyanine green blood concentration dynamics and tissue perfusion analysis method using the same
US7709338B2 (en) * 2006-12-21 2010-05-04 International Business Machines Corporation BiCMOS devices with a self-aligned emitter and methods of fabricating such BiCMOS devices
US8030731B2 (en) 2007-03-28 2011-10-04 Advanced Analogic Technologies, Inc. Isolated rectifier diode
US7737526B2 (en) * 2007-03-28 2010-06-15 Advanced Analogic Technologies, Inc. Isolated trench MOSFET in epi-less semiconductor sustrate
CN101335236B (en) * 2007-12-28 2011-07-06 上海新傲科技股份有限公司 BICMOS circuit buried layer epitaxial method by cylinder epitaxial furnace
CN102820332B (en) * 2011-06-08 2016-04-27 无锡华润上华半导体有限公司 With vertical-type bipolar junction transistor that metal-oxide-semiconductor is integrated and preparation method thereof
CN102723330B (en) * 2012-07-16 2015-12-09 西安电子科技大学 A kind of strain Si BiCMOS integrated device and preparation method
DE202013105006U1 (en) * 2013-11-07 2015-02-10 Wittur Holding Gmbh Elevator with tubular motor and split motor mount
US10243047B2 (en) * 2016-12-08 2019-03-26 Globalfoundries Inc. Active and passive components with deep trench isolation structures
RU174127U1 (en) * 2017-03-17 2017-10-03 Закрытое акционерное общество "ГРУППА КРЕМНИЙ ЭЛ" SILICON PLANAR TRANSISTOR
DE102017216214B4 (en) * 2017-09-13 2019-05-09 Infineon Technologies Ag Method for producing a combined semiconductor device

Family Cites Families (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5340762A (en) 1985-04-01 1994-08-23 Fairchild Semiconductor Corporation Method of making small contactless RAM cell
US4922318A (en) 1985-09-18 1990-05-01 Advanced Micro Devices, Inc. Bipolar and MOS devices fabricated on same integrated circuit substrate
US4752589A (en) * 1985-12-17 1988-06-21 Siemens Aktiengesellschaft Process for the production of bipolar transistors and complementary MOS transistors on a common silicon substrate
US5023193A (en) 1986-07-16 1991-06-11 National Semiconductor Corp. Method for simultaneously fabricating bipolar and complementary field effect transistors using a minimal number of masks
DE68921995T2 (en) * 1988-01-19 1995-12-07 Nat Semiconductor Corp Method of manufacturing a polysilicon emitter and a polysilicon gate by simultaneously etching polysilicon on a thin gate oxide.
JPH0348459A (en) 1989-04-26 1991-03-01 Matsushita Electric Ind Co Ltd Semiconductor device and its manufacturing method
JPH0349234A (en) 1989-07-17 1991-03-04 Fujitsu Ltd Manufacture of semiconductor device
DE69133446T2 (en) * 1990-11-14 2006-02-09 Samsung Semiconductor, Inc., San Jose BiCMOS method with bipolar transistor with low base recombination current
JP2740087B2 (en) 1992-08-15 1998-04-15 株式会社東芝 Method for manufacturing semiconductor integrated circuit device
US5342794A (en) 1992-09-10 1994-08-30 Vlsi Technology, Inc. Method for forming laterally graded deposit-type emitter for bipolar transistor
US5374569A (en) 1992-09-21 1994-12-20 Siliconix Incorporated Method for forming a BiCDMOS
US5557131A (en) 1992-10-19 1996-09-17 At&T Global Information Solutions Company Elevated emitter for double poly BICMOS devices
US5439833A (en) 1994-03-15 1995-08-08 National Semiconductor Corp. Method of making truly complementary and self-aligned bipolar and CMOS transistor structures with minimized base and gate resistances and parasitic capacitance
US5583059A (en) 1994-06-01 1996-12-10 International Business Machines Corporation Fabrication of vertical SiGe base HBT with lateral collector contact on thin SOI
JPH07335773A (en) 1994-06-10 1995-12-22 Hitachi Ltd Method for manufacturing semiconductor integrated circuit device
JP3444002B2 (en) 1995-02-14 2003-09-08 ソニー株式会社 Semiconductor device and manufacturing method thereof
JP3329640B2 (en) 1995-10-10 2002-09-30 株式会社東芝 Method for manufacturing semiconductor device
US5843814A (en) 1996-02-15 1998-12-01 Micron Technology, Inc. Method of forming BiCMOS circuitry
JP3919885B2 (en) * 1997-06-18 2007-05-30 株式会社ルネサステクノロジ Manufacturing method of semiconductor device
US5766990A (en) 1997-08-08 1998-06-16 National Semiconductor Corporation Method of manufacturing a high speed bipolar transistor in a CMOS process

Cited By (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6780694B2 (en) * 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US20040132236A1 (en) * 2003-01-08 2004-07-08 International Business Machines Corporation Mos transistor
US20080315346A1 (en) * 2004-01-31 2008-12-25 Ralf Lerner Passivation of Deep Isolating Separating Trenches with Sunk Covering Layers
WO2005074021A1 (en) * 2004-01-31 2005-08-11 X-Fab Semiconductor Foundries Ag Passivation of deep isolating separating trenches with sunk covering layers
US7625805B2 (en) 2004-01-31 2009-12-01 X-Fab Semiconductor Foundries Ag Passivation of deep isolating separating trenches with sunk covering layers
US20060060886A1 (en) * 2004-09-21 2006-03-23 International Business Machines Corporation METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY
US20070264787A1 (en) * 2004-09-21 2007-11-15 International Business Machines Corporation METHOD TO BUILD SELF-ALIGNED NPN IN ADVANCED BiCMOS TECHNOLOGY
US7265018B2 (en) 2004-09-21 2007-09-04 International Business Machines Corporation Method to build self-aligned NPN in advanced BiCMOS technology
US7776704B2 (en) 2004-09-21 2010-08-17 International Business Machines Corporation Method to build self-aligned NPN in advanced BiCMOS technology
US20100022056A1 (en) * 2006-08-31 2010-01-28 Nxp, B.V. Method of manufacturing a bipolar transistor
US8026146B2 (en) * 2006-08-31 2011-09-27 Nxp B.V. Method of manufacturing a bipolar transistor
CN105390496A (en) * 2014-09-05 2016-03-09 中芯国际集成电路制造(上海)有限公司 Semiconductor device, manufacturing method therefor, and electronic device
US10698156B2 (en) * 2017-04-27 2020-06-30 The Research Foundation For The State University Of New York Wafer scale bonded active photonics interposer
US11435523B2 (en) 2017-04-27 2022-09-06 The Research Foundation For The State University Of New York Wafer scale bonded active photonics interposer
US11841531B2 (en) 2017-04-27 2023-12-12 The Research Foundation For The State University Of New York Wafer scale bonded active photonics interposer

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