US20020070765A1

US20020070765A1 - Data slicer circuit

Info

Publication number: US20020070765A1
Application number: US09/975,576
Authority: US
Inventors: Toshiaki Tsujikawa
Original assignee: Nippon Precision Circuits Inc
Current assignee: Seiko NPC Corp
Priority date: 2000-11-02
Filing date: 2001-10-11
Publication date: 2002-06-13
Anticipated expiration: 2021-10-11
Also published as: JP2002140856A; US6525684B2

Abstract

Automatic slice level control in response to differential input signals is enabled. Analog signals are transferred differentially to remove in-phase noise. Thus, its effects on S/N are alleviated. Ideal desired DSV (e.g., DSV=0) is accomplished. Also, the circuit scale is reduced, and the processing speed is enhanced. Analog differential input signals vinp and Vinn which are obtained by reading a recording medium and are inverted with respect to each other are supplied to input terminals in1 and in2 of a comparator (1) via resistors R1 and R2. A data stream is recorded on the recording medium while giving DSV=0. A charge pump (2) is driven by the digital signal from the comparator (1). A transconductance amplifier produces output currents Itrc1 and Itrc2 that are mutually differential signals and in proportion to the voltage difference between the output voltage Vcp from the charge pump (2) and a reference voltage Vref. The output currents are supplied to the input terminals in1 and in2 of the comparator. As a result, the digital signal delivered from the comparator (1) accomplishes DSV=0. The analog differential input signals are binarized by the comparator (1), whereby the effects of in-phase noise as coming from the power supply are reduced. This enhances the reliability of the digital signal.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a data slicer circuit and, more particularly, to a data slicer circuit for binarizing analog signals, which are obtained by reading a recording medium such as a CD (compact disc) or DVD (digital versatile disc) with a pickup, in accordance with a DSV (digital sum value) and demodulating the data into digital data.

2. Description of the Related Art

Today, data streams are recorded on recording media such as CDs and DVDs while giving DSV (digital sum value)=0. In particular, in a data stream consisting of an array of 1's and 0's, the difference between the number of 1's and the number of 0's is set to 0 in a certain number of bits of data. During readout, an analog signal read out by a pickup system is compared with a slice level and binarized by a comparator and thus the signal is demodulated into a data stream that is a digital signal. The slice level is so controlled that the DSV=0 holds in the data stream produced from the comparator. Thus, accurate readout is accomplished.

A specific conventional data slicer circuit responds to a single input signal as shown in FIG. 6. After binarization, digital signal processing has been used for error detection DSV≠0. An analog signal undergone single end conversion is input from a terminal Input, and is sent to a

comparator

61. Data binarized by the comparator 61 is sent to a pulse width detection circuit 62, where the data is arithmetically processed. An arithmetic processing circuit 63 finds the amount of deviation from duty ratio 50% using the pulse width detected by the pulse width detection circuit 62. The amount of deviation is pulse width-modulated by a pulse width modulation circuit 64. The pulse width-modulated, binarized signal is averaged by a low-pass filter formed by a capacitor C1 and a resistor R1 to produce a pulse width-modulated average signal. A reference signal 65 is also averaged by a low-pass filter formed by a capacitor C2 and a resistor R2. The difference with the pulse width-modulated average signal is calculated by an analog difference calculation circuit 66. The result of the calculation, or difference, produces a slice level signal for the comparator 61. The binarized output from the comparator 61, i.e., a digital signal, responds to satisfy DSV=0. The loop frequency of this circuit is determined by the two resistors R1, R2 and the two capacitors C1, C2.

Normally, in an analog signal processing circuit used for a pickup system for magnetic discs, optical discs, or the like, an equalizer circuit for waveform equalization is built from a differential circuit, for the following reason. Signals to be processed are taken as differential signals and subjected to subtractive operation by a differential circuit to remove noise mainly coming from the power line, i.e., to remove so-called in-phase noise. In the conventional data slicer circuit shown in FIG. 6, however, the output signal from the equalizer circuit needs to be converted into a single signal by analog signal processing because of single input processing. An analog signal that is a single signal created by the equalizer circuit (not shown) for waveform equalization is fed to the terminal Input.

In the conventional structure shown in FIG. 6, a single signal is input, and the slice level is controlled in response to this single signal. It has been impossible to provide automatic slice level control in response to a differential input signal. The single signal processing is subject to in-phase noise. As a result, the slice level varies. Hence, ideal DSV=0 cannot be accomplished. Therefore, there is the problem that the S/N is deteriorated.

Furthermore, in the conventional structure shown in FIG. 6, digital signal processing is performed to control the slice level after binarization. This presents the problem that the circuit scale is increased. Additionally, the processing operation speed is limited by the operating clock.

SUMMARY OF THE INVENTION

Accordingly, it is an object of the present invention to enable automatic slice level control in response to differential input signals, to remove in-phase noise by transferring analog signals differentially to thereby alleviate the effect on S/N, to accomplish ideal and desired DSV (e.g., DSV=0), to reduce the circuit scale, and to improve processing speed.

A data slicer circuit in accordance with the present invention comprises: a comparator having first and second input terminals for receiving, via their respective first and second resistors, first and second analog signals which are mutually differential signals based on data to which a given DSV (digital sum value) is given, the comparator comparing input voltages from the first and second input terminals and producing a two-valued digital output signal; a charge pump driven by the digital out put signal produced from the comparator; and a transconductance amplifier for applying first and second output currents, which are mutually differential signals in proportion to the difference voltage between the output voltage from the charge pump and a reference voltage, to the first and second input terminals, respectively, of the comparator. The digital signal is so controlled that the given DSV is attained.

Preferably, the output voltage from the charge pump is fed to the transconductance amplifier via a low-pass filter.

The above-described charge pump preferably comprises plural first current sources for charging capacitors and plural second current sources for discharging the capacitors. When the capacitors are charged and discharged, the first and second current sources are selectively used to switch the loop frequency of a loop formed by the comparator, the charge pump, and transconductance amplifier.

The aforementioned charge pump preferably can perform charging and discharging operations using plural capacitors selectively. The loop frequency of a loop formed by the comparator, the charge pump, and the transconductance amplifier is switched.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing the configuration of a data slicer circuit in accordance with a first embodiment of the present invention; [0014]
FIG. 2 is a block diagram showing the details of the charge pump of FIG. 1; [0015]
FIG. 3 is a block diagram showing the configuration of a data slicer circuit in accordance with a second embodiment of the invention; [0016]
FIG. 4 is a block diagram showing the configuration of a charge pump in a data slicer circuit in accordance with a third embodiment of the invention; [0017]
FIG. 5 is a block diagram showing another configuration of a charge pump in the data slicer circuit in accordance with the third embodiment of the invention; and [0018]
FIG. 6 is a block diagram showing the configuration of the related art data slicer circuit.[0019]

DESCRIPTION OF THE PREFERRED EMBODIMENTS

A data slicer circuit in accordance with the present invention is next described in detail in connection with a first embodiment illustrated in FIG. 1. A [0020] comparator 1 consists of a differential amplifier and has input terminals in1 and in2 to which mutually inverted analog signals vinp and Vinn are applied via resistors R1 and R2. The analog differential input signals Vinp and Vinn are analog differential signals obtained by reading an optical disc on which data is recorded by giving DSV (digital sum value)=0 with a pickup system (not shown). For example, it is obtained by subjecting the output current from a photodiode in an optical pickup to current-to-voltage conversion, creating a differential signal by a fully differential amplifier or the like, and then correcting peak shift or the like accompanying RF reading by an equalizer for waveform equalization. The resistors R1 and R2 act to shift the DC voltage levels of the analog differential input signals vinp and Vinn using the output currents Itrc1 and Itrc2 from a transconductance amplifier (described later). Let Vcomp1 and Vcomp2 be input voltages to the comparator 1. Let Vinp(DC) and Vinn(DC) be the DC voltage levels of the analog differential input signals Vinp and Vinn. Thus, we have $\begin{matrix} (\begin{matrix} Vcomp1 = Vinp (DC) + R1 \cdot Intrc1 \\ Vcomp2 = Vinn (DC) + R2 \cdot Intrc2 \end{matrix}) & (1) \end{matrix}$
The values of the resistors R[0021] 1 and R2 or the values of the output currents Itrc1 and Itrc2 are so determined as to cancel out the input offsets of the analog differential input signals Vinp and Vinn. That is, these resistance values and current values are determined in such a way that the DC offset voltage components of the applied signals are canceled out, and a slice level control operation (described later) is enabled.
When the input voltage Vcomp[0022] 1 is higher than the input voltage Vcomp2, the comparator 1 sets the logic level of the output voltage Vdata from the output terminal out1 to high (“1”). If the former voltage is lower than the latter voltage, the comparator sets the logic level to low (“0”). Thus, the comparator binarizes the analog differential input signals Vinp and Vinn and demodulates them into digital signals. These digital signals are used in a circuit at a later stage as digital signals read from a recording medium such as an optical disc and sent to the charge pump 2.
As shown in FIG. 2, the [0023] charge pump 2 connects a first current source 21, switches SW1, SW2, and a second current source 22 in series between power-supply terminals VDD (3 V) and VSS (0 V). The junction of the switches SW1 and SW2 is taken as an output terminal out. A capacitor C1 is connected between an output terminal out2 and the power-supply terminal VSS. When the logic level of the output voltage Vdata is low, the switch SW1 is turned on. Current Isource from the first current source 21 flows, charging the capacitor C1. This increases the output voltage Vcp from the output terminal out2. When the logic level of the output voltage Vdata is high, the switch SW2 is turned on. Current Isink flows from the capacitor C1 to the second current source 22, thus discharging the capacitor C1. This lowers the output voltage Vcp from the output terminal out2. Normally, the current values are determined such that ¦Isource ¦=¦Isink ¦. Let ΔTon be the period during which Vdata is kept high. Let ΔToff be the period during which Vdata is kept low. The output voltage from the charge pump 2 can be given by $\begin{matrix} Vcp = \frac{1}{C1} (Δ Toff \cdot Isource - Δ Ton \cdot I \sin k) & (2) \end{matrix}$
That is, the [0024] charge pump 2 delivers an output voltage Vcp corresponding to DSV of 1's and 0's of the digital signal from the output terminal out1.
The [0025] transconductance amplifier 3 compares the output voltage Vcp from the charge pump 2 with a reference voltage Vref and produces an output that is the current difference between output currents Itrc1 and Itrc2 that is proportional to the voltage difference. Let Vcp is the value of the output voltage Vcp. Let Vref be the value of the reference voltage Vref. Let Itrc1 be the values of the output currents Itrc1 and Itrc2 be the values of the output currents Itrc2, respectively. The transconductance amplifier 3 produces Itrc1=Itrc2 when Vref=Vcp. It produces Itrc1>Itrc2 when Vref<Vcp. It produces Itrc1<Itrc2 when Vref>Vcp.
The loop response frequency of FIG. 1 is determined by the capacitance value of the capacitor C[0026] 1 and the current values Isink and Isource. The loop frequency is set sufficiently lower than the input signal frequency. Its interval is made to correspond to an integral multiple of the interval at which the numbers of 1's and 0's giving DSV=0 in the data stream stored on the aforementioned recording medium such as an optical disc are read out. In other words, the loop frequency is made to correspond to the frequency of the analog differential input signal. That is, it is determined so as to correspond to the rate at which the recording medium is read.
The operation of the present invention is next described. [0027]
The analog differential input signals Vinp and Vinn are applied to the [0028] comparator 1 via the resistors R1 and R2, respectively. Thus, the signals are binarized and sent as the digital signal of output voltage Vdata to the charge pump 2. The charge pump 2 charges and discharges the capacitor C1 according to whether the output voltage Vdata is high or low. As mentioned above, the relation ¦Isource ¦=¦Isink ¦ has been set and, therefore, it can be seen from Eq. (2) that the output voltage Vcp from the charge pump 2 is in proportion to the difference between the period ΔTon of the high level and the period ΔToff of the low level, and corresponds to the DSV of 1's and 0's of the digital signal from the output terminal out1.
The [0029] transconductance amplifier 3 compares the output voltage Vcp and the reference voltage Vref and takes the current difference between the output currents Itrc1 and Itrc2 proportional to the voltage difference. When DSV=0, the output voltage Vcp corresponds with the reference voltage Vref (ideally, 0 V). Where Vref<Vcp, i.e., the digital signal from the output terminal out1 contains more 0's, the current Itrc1 is made greater than the current Itrc2 by an amount corresponding to the difference between the output voltage Vcp and the reference voltage Vref. Thus, R1•Itrc1 that is the DC voltage level shift component of the voltage Vcomp1 indicated by Eq. (1) is made larger than the DC voltage level shift component of the voltage Vcomp2 by R2•Itrc2. In this way, an effect equivalent to decreasing the slice level in the related art single-signal input data slicer circuit is obtained. Conversely, where Vref>Vcp, i.e., the digital signal from the out terminal outputl contains more 1's, the current Itrc1 is made lower than the current Itrc2 by an amount corresponding to the voltage difference between the output voltage Vcp and the reference voltage Vref. In this manner, R1•Itrc1 that is the DC voltage level shift component of the voltage Vcomp1 indicated by Eq. (1) is made lower than R2•Itrc2 that is the DC voltage level shift component of the voltage Vcomp2. As a result, an effect equivalent to increasing the slice level of the data slicer circuit of the related art single-signal input method is obtained. Because of the operations described thus far, the output voltage Vcp is controlled to correspond with the reference voltage Vref. The digital signal from the output terminal out1 accomplishes DSV=0.
In the present example, the effects of in-phase noise can be suppressed by binarizing the analog differential input signals using the [0030] comparator 1 consisting of a differential amplifier. Also, the effects of in-phase noise are suppressed by building the transconductance amplifier 3 as a differential configuration. In-phase noise tends to be introduced in the output voltage Vcp that is converted into a single signal. However, the effects of noise can be neglected by setting the frequency band of the output voltage Vcp sufficiently lower than the input signal frequency. Therefore, the slice level can be controlled without being affected by in-phase noise. Thus, ideal DSV=0 can be accomplished.
As described thus far, in the present embodiment, the slice level control in responsive to the differential input signals can be automatically provided. The analog signals are transferred differentially to thereby remove in-phase noise. The effects on S/N due to in-phase noise are alleviated. Thus, ideal DSV=0 is accomplished. The automatic slice level control is not digital signal processing but analog signal processing. The circuit components that are necessary in addition to the [0031] comparator 1 are only simple components including the charge pump 2 and the transconductance amplifier 3. Hence, the circuit scale can be reduced. In addition, the operating speed can be improved because of the analog signal processing compared with digital signal processing where the processing speed is limited by the operating clock.
A second embodiment of the present invention is next described. [0032]
It is conceivable that a low-pass filter is connected as a method of reducing the effects of noise further. For example, as shown in FIG. 3, a low-[0033] pass filter 31 is connected between the charge pump 2 and a transconductance amplifier 31, thus reducing noise introduced in the output voltage Vcp and the amount of voltage ripple contained in the output voltage Vcp due to switching of the charge pump.
A third example of the present invention is next described. [0034]
In the embodiments described above, the loop frequency is fixed within one system. The present invention is not limited to this. The frequency may be variable. This variable case is permitted by switching the current value through the charge pump or switching the capacitance value. Where the current value is switched, the charge pump is designed as shown in FIG. 4. That is, plural [0035] current sources 41 connected with power-supply terminal VDD are connected with a switch SW1 via switches SW10, and plural current sources 42 connected with a power-supply terminal VSS are connected with a switch SW2 via switches SW20. The switches SW10 and SW20 are selectively turned on by a switch control circuit 43, thus switching the current value. The current value is increased, thus elevating the loop frequency. The current value is reduced, thus lowering the loop frequency. Where the capacitance value is switched, the chargepump is designed as shown in FIG. 5. That is, capacitors 51 have their respective one terminal connected with the power-supply terminals VSS. The other terminals are connected with the output terminal out2 via switches SW3, respectively. The SW3 are selectively turned on by a switch control circuit 52, thus switching the capacitance value. The loop frequency is lowered by increasing the capacitance value. The loop frequency is elevated by reducing the capacitance value. In this way, it is possible to cope with plural analog differential input signals of different frequencies. That is, it is possible to cope with analog signals read from a recording medium at plural different frequencies or with analog signals transmitted at plural different frequencies.
In the embodiments described above, the data slicer circuit produces digital signals by binarizing analog differential input signals that are obtained by reading a recording medium (e.g., an optical disc) on which a certain bits of data are recorded under the condition DSV=0. The present invention is not restricted to this. The invention is also applicable to a circuit where the DSV of a certain bits of data has a given value. In this case, the reference voltage Vref for the transconductance amplifier may be set to the output voltage Vcp corresponding to ΔTon and ΔToff determined according to the value of the DSV. [0036]
In the present invention, analog differential input signals which are inverted with respect to each other and obtained by reading a recording medium are given to a comparator via resistors. A data stream is recorded on the recording medium while giving DSV=0, for example. A charge pump is driven according to a digital signal produced from the comparator. A transconductance amplifier produces output currents that are mutually differential signals and in proportion to the voltage difference between the output voltage from the charge pump and a reference voltage. The output currents are supplied to the input terminals of the comparator. Therefore, the slice level can be controlled by shifting the DC voltage level of the analog differential input signals by the output currents and the resistors. The digital signal produced from this comparator accomplishes given DSV (e.g., DSV=0). As a result, the slice level can be controlled in response to the analog differential input signals. The effects of in-phase noise coming from the power supply and so on are reduced by binarizing the analog differential input signals by the comparator. The reliability of the digital signal obtained by the binarization is enhanced. If a low-pass filter is mounted between the charge pump and the transconductance amplifier, the amount of voltage ripple due to switching of the charge pump can be reduced. The adverse effect of the voltage ripple can be reduced. More accurate desired DSV (e.g., DSV=0) can be accomplished. [0037]
As described thus far, the data slicer circuit in accordance with the present invention is functionally simple but can accomplish desired DSV with high precision (e.g., DSV=0) almost immune to in-phase noise by an analog signal processing, using the charge pump and the transconductance amplifier. Since no digital signal processing is used for the slice level control, the circuit scale can be reduced. Furthermore, the operating speed can be improved because of analog signal processing compared with digital signal processing where the processing speed is limited by the operating clock. [0038]
The charge pump is equipped with plural first current sources for charging capacitors and with plural second current sources for discharging the capacitors. It is possible to cope with analog differential input signals of plural frequencies by switching the loop frequency of the loop formed by comparator, charge pump, and transconductance amplifier by selectively using the first and second current sources when the capacitors are charged and discharged. Alternatively, the charge pump can perform charging and discharging operations by selectively using plural capacitors. In other words, it is possible to cope with analog signals read from a recording medium on which data is recorded at plural different frequencies or with analog signals transmitted at plural different frequencies. [0039]

Claims

What is claimed is:

1. A data slicer circuit comprising:

a comparator having first and second input terminals for receiving, via their respective resistors, first and second analog signals that are mutually differential signals based on data to which a given DSV (digital sum value) is given, said comparator comparing input voltages applied to said first and second input terminals and producing a two-valued digital output signal;

a charge pump driven by said digital output signal from said comparator;

a transconductance amplifier for supplying first and second output currents to said first and second input terminals, respectively, of said comparator, said first and second output currents being mutually differential signals proportional to a difference voltage between the output voltage from said charge pump and a reference voltage; and

wherein said digital signal is controlled to achieve said given DSV.

2. The data slicer circuit of claim 1, wherein the output voltage from said charge pump is applied to said transconductance amplifier via a low-pass filter.

3. The data slicer circuit of claim 1 or 2, wherein said charge pump is equipped with plural first current sources for charging capacitors and with plural second current sources for discharging said capacitors, and wherein the loop frequency of a loop formed by said comparator, said charge pump, and said transconductance amplifier is switched by selectively using said first and second current sources when said capacitors are charged and discharged.

4. The data slicer circuit of claim 1 or 2, wherein said charge pump can charge and discharge the capacitors using plural capacitors and switches the loop frequency of a loop formed by said comparator, said charge pump, and said transconductance amplifier.