+

US20020066943A1 - Lead frame for assembly for thin small outline plastic encapsulated packages - Google Patents

Lead frame for assembly for thin small outline plastic encapsulated packages Download PDF

Info

Publication number
US20020066943A1
US20020066943A1 US09/728,391 US72839100A US2002066943A1 US 20020066943 A1 US20020066943 A1 US 20020066943A1 US 72839100 A US72839100 A US 72839100A US 2002066943 A1 US2002066943 A1 US 2002066943A1
Authority
US
United States
Prior art keywords
lead
lead frame
additional
leads
package
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
US09/728,391
Other versions
US6392288B1 (en
Inventor
Aik Tan
Chee Chew
Shan Tan
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Components Industries LLC
Original Assignee
Semiconductor Components Industries LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Components Industries LLC filed Critical Semiconductor Components Industries LLC
Priority to US09/728,391 priority Critical patent/US6392288B1/en
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: TAN, AIK CHONG, CHEW, CHEE HIONG, TAN, SHAN CHONG
Application granted granted Critical
Publication of US6392288B1 publication Critical patent/US6392288B1/en
Publication of US20020066943A1 publication Critical patent/US20020066943A1/en
Assigned to JPMORGAN CHASE BANK, AS COLLATERAL AGENT reassignment JPMORGAN CHASE BANK, AS COLLATERAL AGENT SUPPLEMENT TO SECURITY AGREEMENT Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, SEMICONDUCTOR COMPONENTS OF RHODE ISLAND, INC.
Assigned to WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY AGREEMENT Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES OF RHODE ISLAND, INC., SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to JPMORGAN CHASE BANK reassignment JPMORGAN CHASE BANK SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH reassignment DEUTSCHE BANK AG NEW YORK BRANCH SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT
Assigned to SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK)
Assigned to DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT reassignment DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST. Assignors: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
Anticipated expiration legal-status Critical
Assigned to FAIRCHILD SEMICONDUCTOR CORPORATION, SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC reassignment FAIRCHILD SEMICONDUCTOR CORPORATION RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087 Assignors: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49503—Lead-frames or other flat leads characterised by the die pad
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to semiconductor packaging in general and, more particularly, to a lead frame assembly for increasing metallic lead count in a thin small outline semiconductor package such as TSOP, MSOP, and other micro-series packages.
  • Small outline packaging is well known in the art of micro series packages. Typical of the art are the TSOP 5 and TSOP 8 packages.
  • the TSOP 5 package has a greater die-mounting pad than the TSOP 8 package but is only available with five external conductive leads. This limits the complexity and functionality of the semiconductor device that can be encapsulated within the package.
  • the TSOP 8 package can have eight isolated conductive leads for an 8 pin I/O count but has a restrictive die-mounting portion. This smaller die-mounting portion is typically too small to accommodate an eight pin semiconductor device. This packaging may result in higher/bigger packaging and required packaging space.
  • FIG. 1 is an enlarged plan view of the lead frame of the present invention
  • FIG. 2 is a side view of the lead frame illustrating downward extending leads of the present invention
  • FIG. 3 is a side view of the encapsulated lead frame assembly and semiconductor package.
  • FIG. 4 illustrates a type of semiconductor circuit that may be manufactured utilizing the additional leads of the lead frame of FIG. 1.
  • FIG. 1 there is shown an expanded plan view of a generally rectangular lead frame 10 in accordance with the present invention that, when incorporated into a semiconductor package arrangement, provides additional leads for more complex circuitry in a microseries package as will be more completely described.
  • Lead frame 10 includes a pair of die mounting portions or flags 12 A and 12 B connected respectively to metallic or conductive leads 14 and 16 that extend externally to the molded plastic semiconductor package.
  • an integrated circuit die 11 shown in dashed outline form may be mounted to both flags 12 A and 12 B in which case only one of the leads 14 or 16 is used.
  • lead frame 10 includes conductive metallic leads 18 , 20 , 22 , and 24 also extending externally from one side of the plastic encapsulation package as will be shown.
  • Stamped lead frame 10 uses metallic tie bars 32 , 34 , 35 , and 37 to add stability to the thin lead frame during assembly process. Additional strips 36 and 38 provide stability, as well as, manufacturability in a typical manner. Openings 40 , 42 , 44 , and 46 formed in the strips 36 and 38 are utilized in a known manner to position lead frames 10 in process equipment such that the strip is moved through an assembly machine.
  • Lead frame 10 as so far described above is fairly conventional in structure.
  • the assembly process for bonding and connecting the semiconductor circuit to the leads within the plastic encapsulation package referred to above is also known.
  • the uniqueness of lead frame 10 and the semiconductor package made up thereof is the inclusion of additional conductive leads 48 and 50 formed at both ends of the elongated direction of lead frame 10 .
  • molded package 30 encapsulates lead frame 10 and opposing leads 48 and 50 .
  • Leads 48 and 50 are stamped during the manufacturing process in a general “S” shape so that they are effectively locked to the package such that the bottom foot pads 48 A and 50 A are essentially at the bottom level of package 30 but are exposed to provide connection to internal semiconductor circuitry.
  • FIG. 3 there is shown the final assembled semiconductor package 30 in side view.
  • the thickness of leads 48 and 50 as well as the other leads and tie bars are exaggerated in this view for clarity.
  • footpad's 48 A and 50 A are at the same level as the bottom of molded package 30 and lie within the external boundaries at opposing parallel and perpendicular ends thereof.
  • the aforedescribed novel lead frame enables a more complex integrated circuit to be placed within the package than prior art thin small outline packages (TSOP). This is possible since a larger die mounting portion is made possible by the additional leads 48 and 50 being placed at opposing longitudinal ends of lead frame 50 .
  • the “s” shape of these two leads allow the lead frame to fit within the footprint of a TSOP while providing two additional leads.
  • a more complex circuit can be incorporated into the inventive lead frame package than previous TSOPs.
  • a dual operational amplifier circuit is provided requiring eight leads.
  • the lead frame provides a die pad large enough to accommodate larger and more complex semiconductor circuitry by incorporating a pair of additional leads. These leads are placed at opposite ends along the longitudinal sides of the generally rectangular lead frame. They are then stamped in a “S” shaped configuration to provide effective locking in the package and to be exposed within the foot print of the package and at the bottom level thereof.
  • the lead frame, semiconductor package provides the advantage of keeping within conventional TSOP dimensional guidelines while providing up to two additional leads thereby allowing more complex circuitry to be used.

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

A lead frame for the assembly of thin small outline packages incorporating a semiconductor circuit is provided in a generally rectangular form including a plurality of conductive leads opposing one another about the longitudinal sides of the lead frame and a die mounting portion centered therebetween. In addition, a pair of leads is provided at the distal ends of the lead frame which are stamped in a general “S” shape. These stamped leads extend downwardly from the lead frame and are within the footprint of the lead frame. The footpads of these additional leads remain exposed as the lead frame is encapsulate in a plastic molded package and are level with the bottom of the molded package.

Description

    FIELD OF THE INVENTION
  • The present invention relates to semiconductor packaging in general and, more particularly, to a lead frame assembly for increasing metallic lead count in a thin small outline semiconductor package such as TSOP, MSOP, and other micro-series packages. [0001]
    • BACKGROUND OF THE INVENTION
  • Small outline packaging is well known in the art of micro series packages. Typical of the art are the [0002] TSOP 5 and TSOP 8 packages. The TSOP 5 package has a greater die-mounting pad than the TSOP 8 package but is only available with five external conductive leads. This limits the complexity and functionality of the semiconductor device that can be encapsulated within the package.
  • The TSOP 8 package can have eight isolated conductive leads for an 8 pin I/O count but has a restrictive die-mounting portion. This smaller die-mounting portion is typically too small to accommodate an eight pin semiconductor device. This packaging may result in higher/bigger packaging and required packaging space. [0003]
  • Accordingly, a need exists for a small outline package, which maintains the larger die-mounting area such as the TSOP 5 micro-series package while having superior lead count as available in the small outline micro-series package. In addition, the additional lead count should not cause an increase in the minimal packaging outline.[0004]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is an enlarged plan view of the lead frame of the present invention; [0005]
  • FIG. 2 is a side view of the lead frame illustrating downward extending leads of the present invention; [0006]
  • FIG. 3 is a side view of the encapsulated lead frame assembly and semiconductor package; and [0007]
  • FIG. 4 illustrates a type of semiconductor circuit that may be manufactured utilizing the additional leads of the lead frame of FIG. 1.[0008]
    • DETAILED DESCRIPTION OF THE DRAWINGS
  • Turning now to FIG. 1 there is shown an expanded plan view of a generally [0009] rectangular lead frame 10 in accordance with the present invention that, when incorporated into a semiconductor package arrangement, provides additional leads for more complex circuitry in a microseries package as will be more completely described. Lead frame 10 includes a pair of die mounting portions or flags 12A and 12B connected respectively to metallic or conductive leads 14 and 16 that extend externally to the molded plastic semiconductor package. In some cases an integrated circuit die 11 (shown in dashed outline form) may be mounted to both flags 12A and 12B in which case only one of the leads 14 or 16 is used. Additionally, lead frame 10 includes conductive metallic leads 18, 20, 22, and 24 also extending externally from one side of the plastic encapsulation package as will be shown. The outline of the plastic semiconductor package, which encapsulates lead frame 10 and within which the semiconductor circuit die 11 resides, is shown at 30. Stamped lead frame 10 uses metallic tie bars 32, 34, 35, and 37 to add stability to the thin lead frame during assembly process. Additional strips 36 and 38 provide stability, as well as, manufacturability in a typical manner. Openings 40, 42, 44, and 46 formed in the strips 36 and 38 are utilized in a known manner to position lead frames 10 in process equipment such that the strip is moved through an assembly machine.
  • [0010] Lead frame 10 as so far described above is fairly conventional in structure. In addition, the assembly process for bonding and connecting the semiconductor circuit to the leads within the plastic encapsulation package referred to above is also known. The uniqueness of lead frame 10 and the semiconductor package made up thereof is the inclusion of additional conductive leads 48 and 50 formed at both ends of the elongated direction of lead frame 10. As shown in FIG. 2 molded package 30 encapsulates lead frame 10 and opposing leads 48 and 50. Leads 48 and 50 are stamped during the manufacturing process in a general “S” shape so that they are effectively locked to the package such that the bottom foot pads 48A and 50A are essentially at the bottom level of package 30 but are exposed to provide connection to internal semiconductor circuitry.
  • Turning to FIG. 3 there is shown the final assembled [0011] semiconductor package 30 in side view. The thickness of leads 48 and 50 as well as the other leads and tie bars are exaggerated in this view for clarity. In reality, footpad's 48A and 50A are at the same level as the bottom of molded package 30 and lie within the external boundaries at opposing parallel and perpendicular ends thereof.
  • The aforedescribed novel lead frame enables a more complex integrated circuit to be placed within the package than prior art thin small outline packages (TSOP). This is possible since a larger die mounting portion is made possible by the [0012] additional leads 48 and 50 being placed at opposing longitudinal ends of lead frame 50. The “s” shape of these two leads allow the lead frame to fit within the footprint of a TSOP while providing two additional leads. For example, referring to FIG. 4, a more complex circuit can be incorporated into the inventive lead frame package than previous TSOPs. Thus, in one illustrative application, a dual operational amplifier circuit is provided requiring eight leads.
  • In summary, what has been described is a novel lead frame for use in micro-series packages. The lead frame provides a die pad large enough to accommodate larger and more complex semiconductor circuitry by incorporating a pair of additional leads. These leads are placed at opposite ends along the longitudinal sides of the generally rectangular lead frame. They are then stamped in a “S” shaped configuration to provide effective locking in the package and to be exposed within the foot print of the package and at the bottom level thereof. Thus, the lead frame, semiconductor package, provides the advantage of keeping within conventional TSOP dimensional guidelines while providing up to two additional leads thereby allowing more complex circuitry to be used. [0013]

Claims (13)

What is claimed is:
1. A lead frame for assembly of a semiconductor device within a package having a predetermined foot print, the lead frame having a plurality of leads that are formed about opposing longitudinal sides of the package, the lead frame comprising at least one additional lead formed within the area of the foot print of the package and being exposed at the bottom level of the package.
2. The lead frame of claim 1 wherein said at least one additional lead being formed at one of the distal ends of the semiconductor package.
3. The lead frame of claim 1 comprising an additional lead formed within the area of the footprint of the package and being exposed at the bottom level of the package.
4. The lead frame of claim 3 wherein said additional lead being formed at the opposite distal end of the semiconductor package.
5. The lead frame of claim 4 wherein said at least one additional lead and said additional lead having a generally “S” shape.
6. The lead frame of claim 2 wherein said at least one additional lead having a generally “S” shape.
7. A lead frame having a plurality of longitudinally extending opposing leads, a die bonding flag to which at least one of said opposing leads is attached, the lead frame comprising at least one additional lead formed at an end of the lead frame spatially between the opposing leads and having a generally S” shape.
8. The lead frame of claim 7 including an additional lead formed oppositely away from said at least one lead spatially between the opposing leads and having a generally “S” shape.
9. A thin small outline semiconductor package having a lead frame therein, the lead frame including a plurality of conductive leads extending outwardly of along the longitudinal sides of the semiconductor package, a die mounting portion to which a semiconductor circuit is mounted and to which one of said plurality of conductive leads is connected therewith, said lead frame having at least one additional conductive lead spaced at one of the distal ends of the semiconductor package and having a generally “S” shape such that said lead is formed internally to the semiconductor package.
10. The semiconductor package of claim 9 wherein said lead frame includes an additional conductive lead spaced at the opposite distal from said at least one additional lead, said additional lead having a generally “S” shape such that said additional lead is formed internally to the semiconductor package.
11. The semiconductor package of claim 10 wherein the respective bottoms of said at least one additional lead and said additional lead are exposed and are substantially level with the bottom of the semiconductor package.
12. A lead frame for the assembly of thin small outline packages incorporating a semiconductor circuit comprising:
a first group of metallic members including a die mounting portion and a first plurality of leads;
a first metallic interconnecting tie bar in proximity of said die mounting portion for holding said first plurality of leads in alignment;
a second group of metallic members including a second plurality of leads aligned opposite to said first plurality of leads;
a second metallic interconnecting tie bar for holding said second plurality of leads in alignment; and
at least one additional metallic lead grouped at one end of said lead frame and formed in an “S” shape extending downward from said lead frame within the interior thereof.
13. The lead frame of claim 12 including an additional metallic lead grouped at the other end of said lead framed and formed in a “S” shape extending downward from said lead frame within the interior thereof.
US09/728,391 2000-12-04 2000-12-04 Lead frame for assembly for thin small outline plastic encapsulated packages Expired - Lifetime US6392288B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
US09/728,391 US6392288B1 (en) 2000-12-04 2000-12-04 Lead frame for assembly for thin small outline plastic encapsulated packages

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/728,391 US6392288B1 (en) 2000-12-04 2000-12-04 Lead frame for assembly for thin small outline plastic encapsulated packages

Publications (2)

Publication Number Publication Date
US6392288B1 US6392288B1 (en) 2002-05-21
US20020066943A1 true US20020066943A1 (en) 2002-06-06

Family

ID=24926662

Family Applications (1)

Application Number Title Priority Date Filing Date
US09/728,391 Expired - Lifetime US6392288B1 (en) 2000-12-04 2000-12-04 Lead frame for assembly for thin small outline plastic encapsulated packages

Country Status (1)

Country Link
US (1) US6392288B1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050067677A1 (en) * 2003-09-26 2005-03-31 Golick Lawrence W. Packaged integrated circuit providing trace access to high-speed leads

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8710636B1 (en) 2013-02-04 2014-04-29 Freescale Semiconductor, Inc. Lead frame array package with flip chip die attach

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6118173A (en) * 1996-11-14 2000-09-12 Nippon Steel Semiconductor Corporation Lead frame and a semiconductor device
JP3027954B2 (en) * 1997-04-17 2000-04-04 日本電気株式会社 Integrated circuit device and manufacturing method thereof
JP2907186B2 (en) * 1997-05-19 1999-06-21 日本電気株式会社 Semiconductor device and manufacturing method thereof
EP0895287A3 (en) * 1997-07-31 2006-04-05 Matsushita Electric Industrial Co., Ltd. Semiconductor device and lead frame for the same
US6121674A (en) * 1998-02-23 2000-09-19 Micron Technology, Inc. Die paddle clamping method for wire bond enhancement

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050067677A1 (en) * 2003-09-26 2005-03-31 Golick Lawrence W. Packaged integrated circuit providing trace access to high-speed leads
US7009282B2 (en) 2003-09-26 2006-03-07 Agere Systems Inc. Packaged integrated circuit providing trace access to high-speed leads

Also Published As

Publication number Publication date
US6392288B1 (en) 2002-05-21

Similar Documents

Publication Publication Date Title
KR100302593B1 (en) Semiconductor package and fabricating method thereof
US6534344B2 (en) Integrated circuit chip and method for fabricating the same
US20080197464A1 (en) Integrated Circuit Device Package with an Additional Contact Pad, a Lead Frame and an Electronic Device
US4278991A (en) IC Package with heat sink and minimal cross-sectional area
US20050051876A1 (en) Integrated circuit package with leadframe enhancement and method of manufacturing the same
US6414379B1 (en) Structure of disturbing plate having down set
US6392288B1 (en) Lead frame for assembly for thin small outline plastic encapsulated packages
US6541856B2 (en) Thermally enhanced high density semiconductor package
KR960702178A (en) Integrated circuit package encapsulated in plastic and manufacturing method (PALSTIC ENCAPSULATED INTEGRATED CIRCUIT PACKAGE AND METHOD OF MANUFACTURING THE SAME)
US5914528A (en) Thermally-enhanced lead frame with reduced thermal gap
JPS63296252A (en) Resin sealed semiconductor device
JPS62158352A (en) Resin sealed semiconductor device
KR100280393B1 (en) Semiconductor package
KR0148203B1 (en) How to design internal leads in lead frames
KR19990034731A (en) Lead-on chip lead frames and packages using them
KR100373149B1 (en) Semiconductor package
KR0129198B1 (en) Semiconductor package
KR100567045B1 (en) Semiconductor package
US6472731B2 (en) Solder clad lead frame for assembly of semiconductor devices and method
KR200156932Y1 (en) Stacked modular chip size package
KR100440789B1 (en) Semiconductor package and manufacturing method the same
JPS62249464A (en) Semiconductor package
KR19990050778A (en) Leadframe for Vizage Packages
JPS59115551A (en) Semiconductor device
KR0145769B1 (en) Semiconductor package and manufacturing method

Legal Events

Date Code Title Description
AS Assignment

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:TAN, AIK CHONG;CHEW, CHEE HIONG;TAN, SHAN CHONG;REEL/FRAME:011344/0418;SIGNING DATES FROM 20001009 TO 20001012

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: JPMORGAN CHASE BANK, AS COLLATERAL AGENT, NEW YORK

Free format text: SUPPLEMENT TO SECURITY AGREEMENT;ASSIGNORS:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;SEMICONDUCTOR COMPONENTS OF RHODE ISLAND, INC.;REEL/FRAME:012991/0180

Effective date: 20020505

AS Assignment

Owner name: WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION,

Free format text: SECURITY AGREEMENT;ASSIGNORS:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;SEMICONDUCTOR COMPONENTS INDUSTRIES OF RHODE ISLAND, INC.;REEL/FRAME:012958/0638

Effective date: 20020506

AS Assignment

Owner name: JPMORGAN CHASE BANK, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:014007/0239

Effective date: 20030303

FPAY Fee payment

Year of fee payment: 4

FPAY Fee payment

Year of fee payment: 8

FPAY Fee payment

Year of fee payment: 12

AS Assignment

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, NEW YORK

Free format text: SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:038620/0087

Effective date: 20160415

AS Assignment

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:WELLS FARGO BANK MINNESOTA, NATIONAL ASSOCIATION, AS COLLATERAL AGENT;REEL/FRAME:038543/0039

Effective date: 20050217

AS Assignment

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT AND COLLATERAL AGENT;REEL/FRAME:038631/0345

Effective date: 20100511

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: RELEASE BY SECURED PARTY;ASSIGNOR:JPMORGAN CHASE BANK, N.A. (ON ITS BEHALF AND ON BEHALF OF ITS PREDECESSOR IN INTEREST, CHASE MANHATTAN BANK);REEL/FRAME:038632/0074

Effective date: 20160415

AS Assignment

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AG

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:039853/0001

Effective date: 20160415

Owner name: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT, NEW YORK

Free format text: CORRECTIVE ASSIGNMENT TO CORRECT THE INCORRECT PATENT NUMBER 5859768 AND TO RECITE COLLATERAL AGENT ROLE OF RECEIVING PARTY IN THE SECURITY INTEREST PREVIOUSLY RECORDED ON REEL 038620 FRAME 0087. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTEREST;ASSIGNOR:SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC;REEL/FRAME:039853/0001

Effective date: 20160415

AS Assignment

Owner name: FAIRCHILD SEMICONDUCTOR CORPORATION, ARIZONA

Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064070/0001

Effective date: 20230622

Owner name: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC, ARIZONA

Free format text: RELEASE OF SECURITY INTEREST IN PATENTS RECORDED AT REEL 038620, FRAME 0087;ASSIGNOR:DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT;REEL/FRAME:064070/0001

Effective date: 20230622

点击 这是indexloc提供的php浏览器服务，不要输入任何密码和下载