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US20020034853A1 - Structure and process flow for fabrication of dual gate floating body integrated mos transistors - Google Patents

Structure and process flow for fabrication of dual gate floating body integrated mos transistors Download PDF

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US20020034853A1
US20020034853A1 US09/342,022 US34202299A US2002034853A1 US 20020034853 A1 US20020034853 A1 US 20020034853A1 US 34202299 A US34202299 A US 34202299A US 2002034853 A1 US2002034853 A1 US 2002034853A1
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channel
drain region
forming
gate
layer
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US6392271B1 (en
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Mohsen Alavi
Ebrahim Andideh
Scott Thompson
Mark T. Bohr
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Intel Corp
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Priority to US10/102,319 priority patent/US6624032B2/en
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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/01Manufacture or treatment
    • H10D30/021Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/025Manufacture or treatment of FETs having insulated gates [IGFET] of vertical IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/611Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/63Vertical IGFETs
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00Field-effect transistors [FET]
    • H10D30/60Insulated-gate field-effect transistors [IGFET]
    • H10D30/711Insulated-gate field-effect transistors [IGFET] having floating bodies

Definitions

  • the present invention relates to the fabrication of integrated circuit devices on a semiconductor substrate. More particularly, the present invention relates to the fabrication of dual gate floating body MOS transistors.
  • Silicon-on-insulator (SOI) technology deals with forming transistors in a layer of semiconductor material that overlies an insulating later.
  • a common embodiment of SOI structures has a single crystal layer of silicon that overlies a layer of silicon dioxide.
  • High performance and high density integrated circuits are achievable using SOI technology, because of the reduced parasitic elements that are present in the integrated circuits that use SOI transistors. Problems exist with SOI transistor technology, however, relating to the floating body in partially depleted SOI technology.
  • ULSI MOSFET devices are being continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed.
  • the continuous scaling down of geometry requires new transistor structures.
  • Some innovative device structures and processes have been proposed that achieve the high performance of these small geometry devices, and yet can be made without requiring complicated fabrication techniques.
  • One such device structure is a vertical MOSFET structure that provides a dual gate device which solves the floating body problem of partially depleted SOI transistors.
  • a second important advantage of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The transistor channel length is instead determined by shallow trench etching and epitaxial layer growth techniques.
  • Transistors having two gate electrodes are known in the art, wherein there is a top gate and a bottom gate that may or may not be inherently self-aligned to the source/drain.
  • N-channel double-gate MOSFET's with a 25 nm thick silicon channel have been successfully demonstrated.
  • the process flow used to fabricate the two gate electrodes is complex and often uses non self-aligned source and drains.
  • fully depleted floating body MOS devices have been proposed using planar transistors and SOI technology, they do not offer voltage control on the second gate, they require advanced SOI, advanced start material (thin body, thin box), and STI isolation.
  • an improved structure and process flow allowing for fabrication of dual gate floating body NMOS and PMOS transistors is desired.
  • a dual gate transistor device and method for fabricating the same is described. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a first and a second gate electrode are formed next to the gate oxide layer, and a drain region is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region, a drain region, a first gate electrode, and a second gate electrode.
  • FIG. 1 is a cross-sectional view of a starting substrate for the manufacturing process for the device of the present invention.
  • FIG. 2 is a cross-sectional view of the P+ region of FIG. 1 that forms the basis of the fabrication process of the PMOS device to be described.
  • FIG. 3 is a cross-sectional view of the P+ layer of FIG. 2 with a layer of oxide deposited thereon.
  • FIG. 4 is a cross-sectional view of the layers illustrated in FIG. 3 with a mask deposited and patterned thereon.
  • FIG. 5 is a cross-sectional view of the trench formed in the exposed portion illustrated in FIG. 4.
  • FIG. 6 is a cross-sectional view of the trench formed in FIG. 5 with the mask removed.
  • FIG. 7 is a cross-sectional view of the device of FIG. 6 with selective doped Si deposition into the trench 18 .
  • FIG. 8 is a cross-sectional view of a sacrificial layer of nitride deposited on the device illustrated in FIG. 7.
  • FIG. 9 is a cross-sectional view illustrating the device of FIG. 8 after a nitride polish.
  • FIG. 10 is a cross-sectional view of the device of FIG. 9 after a partial oxide etch is performed.
  • FIG. 11 is a cross-sectional view of the device of FIG. 10 after gate oxidation.
  • FIG. 12 is a cross-sectional view of the device of FIG. 11 after poly deposition forms a layer over the device and a poly polish levels the poly layer such that it is approximately level with the nitride layer of FIG. 12.
  • FIG. 13 is a cross-sectional view of the device 12 with a mask applied for patterning the poly layer.
  • FIG. 14 is a cross-sectional view of the device showing the poly layer as it is patterned.
  • FIG. 15 is a cross-sectional view of the device of 14 after the mask is removed.
  • FIG. 16 is a cross-sectional view of the device of FIG. 15 after a partial poly etch is performed.
  • FIG. 17 is a cross-sectional view of the device of FIG. 16 as the poly layer is doped using a poly implant.
  • FIG. 18 is a cross-sectional view of the device of FIG. 17 after oxidation with the resulting poly oxide layer 36 illustrated.
  • FIG. 19 is a cross-sectional view of the device of FIG. 18 with the nitride layer removed.
  • FIG. 20A is a cross-sectional view of the device of FIG. 19 illustrating the formation of the drain contact through selective Si deposition.
  • FIG. 20B is a cross-sectional view of the device of FIG. 19 illustrating the formation of the drain contact through depositing a poly-Si layer that is then masked for and patterned.
  • FIG. 21 is a cross-sectional view of the device of FIG. 20A after an oxide etch is performed to remove the exposed sections of oxide layers.
  • FIG. 22 is a cross-sectional view of the device of FIG. 21 illustrating the nitride spacers 41 created and a subsequent salicidation process.
  • FIG. 23 is a cross-sectional view of the device of FIG. 22 illustrating an ILD deposition and polish.
  • FIG. 24 is a cross-sectional view of the device of FIG. 23 with a mask applied.
  • FIG. 25 is a cross-sectional view of the device of FIG. 6 with a selective Si deposition formed in the trench.
  • FIG. 26 is a cross-sectional view of the device of FIG. 25 after deposition of a sacrificial layer of nitride.
  • FIG. 27 is a cross-sectional view of the device of FIG. 26 after the nitride layer has been polished.
  • FIG. 28 is a cross-sectional view of the device of FIG. 27 after a partial oxide etch is performed.
  • FIG. 29 is a cross-sectional view of the device of FIG. 28 after gate oxidation.
  • FIG. 30 is a cross-sectional view of the device of FIG. 29 after a poly deposition and polish.
  • FIG. 31 is a cross-sectional view of the device of FIG. 30 with a mask applied.
  • FIG. 32 is a cross-sectional view of the device of FIG. 31 showing the poly layer as it is patterned.
  • FIG. 33 is a cross-sectional view of the device of FIG. 32 after the mask has been removed.
  • FIG. 34 is a cross-sectional view of the device of FIG. 33 after a partial poly etch.
  • FIG. 35 is a cross-sectional view of the device of FIG. 34 showing a poly implant.
  • FIG. 36 is a cross-sectional view of the device of FIG. 35 after the formation of a poly oxide layer.
  • FIG. 37 is a cross-sectional view of the device of FIG. 36 after the nitride layer is removed.
  • FIG. 38 is a cross-sectional view of the device of the present invention.
  • FIG. 39 is a cross-sectional view of the device of the present invention with each of the different gates, sources and drain labeled.
  • FIG. 40 is a top view of the device illustrated in FIG. 38.
  • FIG. 41 is a cross-sectional view of the device of FIG. 18 with a layer of oxide deposited thereon.
  • FIG. 42 is a cross-sectional view of the device of 41 after the oxide layer has been patterned.
  • FIG. 43 is a cross-sectional view of selective deposition of Si for a second layer device.
  • the present invention relates to dual gate floating body NMOS and PMOS transistors fabricated by a process offering several advantages over the prior art.
  • the process disclosed herein requires only two to three additional masking steps when compared with conventional bulk MOS processing.
  • the process flow described does not require silicon-on-insulator (SOI) technology or epi wafers as start material, offers full control over the second transistor gate based on planar interconnects, does not need STI isolation, and offers potential for successive vertical integration of multiple levels of transistors.
  • SOI silicon-on-insulator
  • the present invention discloses an apparatus and method for the fabrication of the dual gate floating body NMOS and PMOS transistors described herein, however, the process flow will be discussed using the PMOS device as an example. Note that the NMOS device is fabricated in a parallel procedure, with the opposite dopants resulting in NMOS transistors. FIGS. 1 - 24 illustrate the process steps of a first embodiment of fabricating a dual gate floating body transistor.
  • FIG. 1 is a cross-sectional view of a starting substrate 10 for the process described herein.
  • An SOI or epi wafer is not required for the starting substrate.
  • LOCOS or STI isolation is not needed, but n-well, N+, and P+ masks are needed here.
  • the process flow described below will use merely the PMOS device 12 as an example and to simplify the following explanation. (Note, however, that the NMOS device may be fabricated with the opposite dopants in parallel along side the PMOS device.)
  • FIG. 2 is a side view of the P+ layer 12 that forms the basis of the fabrication process described below.
  • FIG. 3 is a side cross-sectional view of the P+ layer 12 with a layer of oxide 14 (e.g., SiO 2 ) deposited or grown thereon.
  • oxide 14 e.g., SiO 2
  • both the P+ layer 12 and the oxide layer 14 have an approximate thickness of 0.5 ⁇ m.
  • the oxide layer 14 must be patterned separately (using two masks) for the NMOS and the PMOS transistors.
  • FIG. 4 illustrates the addition of one mask 16 for the masking of the oxide layer 14 used to pattern the oxide layer 14 for the PMOS transistor. It will be obvious to one with ordinary skill in the art that oxide layer 14 may be patterned using well known photolithographic masking and etching techniques, resulting in the trench 18 illustrated in FIG. 5 and again in FIG. 6 after the removal of the mask 16 .
  • FIG. 7 illustrates the device during selective Si deposition, generally formed using epitaxial growth, into the trench 18 with in-situ doping of the shown layers.
  • the two tip (P+) regions 20 and 22 shown can form automatically by thermal diffusion, with the middle region 24 remaining an undoped Si layer.
  • the trench 18 has an approximate thickness of 0.2 ⁇ m and regions 20 , 22 , and 24 have a combined thickness of approximately 0.4 ⁇ m.
  • a sacrificial layer 26 of nitride is deposited, as illustrated in FIG. 8.
  • the sacrificial layer 26 of nitride has an approximate thickness of 0.4 ⁇ m.
  • FIG. 9 illustrates the device after a nitride polish, resulting in a nitride layer 26 filling the remainder of trench 18 .
  • oxide regions 28 have an approximate thickness of 15 ⁇ . Note that if (110) oriented start material (layer 12 ) is used, the oxidation will be along the (100) oriented plane.
  • An alternative embodiment also uses sacrificial oxidation and etching prior to the gate oxidation to thin the channel region.
  • poly deposition forms a layer over the device fabricated thus far.
  • a poly polish is then used to level the poly layer 30 such that it is approximately level with the nitride level 26 , as shown in FIG. 12.
  • the poly layer 30 after polish is approximately 0.4 ⁇ m.
  • a mask 32 is placed above the poly layer 30 (see FIG. 13), such that the poly layer 30 may be patterned (see FIG. 14). The mask 32 is subsequently removed, leaving patterned poly layer 30 as illustrated in FIG. 15.
  • a partial poly etch such as a plasma etch, is then performed to minimize the poly-drain overlap.
  • the etch produces a thinner poly layer 30 as evident in FIG. 16.
  • the poly layer after etch is approximately 0.3 ⁇ m. Note that the poly-drain overlap can cause increased capacitance resulting in a slower transistor.
  • the poly layer 30 is doped using a poly implant 34 (note the use of a mask is not shown in the illustration) as shown in FIG. 17. This is followed by poly oxidation to further minimize the overlap capacitance. After oxidation, the poly layer has an approximate thickness of 0.2 ⁇ m. This results in a poly oxide layer 36 having an approximate thickness of 0.2 ⁇ m adjacent the poly layer 30 as shown in FIG. 18.
  • poly doping may be performed in-situ during poly deposition. In that case, the poly implant step above will not be required.
  • the nitride layer 26 is removed with an etching step, such as a plasma etch, as illustrated in FIG. 19.
  • selective Si deposition is applied using an epitaxial growth process to form the drain region, which is then doped to form layer 38 (as shown in FIG. 20A).
  • layer 38 has an approximate thickness of 0.5 ⁇ m.
  • the P+ dopant may be implanted into layer 38 or created by in-situ deposition.
  • the resulting layer 38 tends to look like a mushroom and may need further optimization since it often gets too thick.
  • FIG. 20B illustrates a second, alternative step to that described above.
  • a poly-Si layer 40 is deposited and then masked for patterning (not shown). Then, as with the above step, the P+ dopant may be implanted using a mask process (also not shown).
  • the poly-Si layer 40 has an approximate thickness of 0.5 ⁇ m.
  • an oxide etch is then performed to remove the exposed sections of layer 14 of SiO 2 and layer 36 of poly oxide as is illustrated in FIG. 21.
  • nitride spacers 41 are created using the same techniques as performed in conventional MOS fabrication.
  • the salicidation process forms salicide layer 42 as shown in FIG. 22.
  • salicide layer 42 has an approximate thickness of 300 ⁇ .
  • the formation of the spacer 41 is followed by an ILD deposition 44 having an approximate thickness of 1.5 ⁇ m and polish as illustrated in FIG. 23.
  • a mask 46 is then applied (see FIG. 24) followed by a contact etching step, resulting in the device 60 illustrated in FIG. 38 and labeled more extensively in FIG. 39.
  • FIGS. 25 - 37 An alternative method of forming the device 60 is illustrated in FIGS. 25 - 37 .
  • the method illustrated in FIGS. 25 - 37 is simpler and provides more control over the dimensions of the tips and channels in the final device 60 .
  • the initial steps are the same as the above described embodiment and illustrated in FIGS. 1 - 6 .
  • a selective Si deposition is formed in trench 18 to form layer 48 , as shown in FIG. 25. Unlike above, however, doping to form the tip regions is not done at this step.
  • a sacrificial layer 26 of nitride is deposited (see FIG. 26) and then polished (see FIG. 27).
  • a partial oxide etch is performed on layer 14 , leaving, for example, approximately 0.1 ⁇ m of SiO 2 to minimize overlap capacitance (see FIG. 28).
  • gate oxidation is performed to produce regions 28 (see FIG. 29).
  • the gate oxidation is followed by a poly deposition and poly polish to form layer 30 as illustrated in FIG. 30.
  • a mask 32 is then applied (see FIG. 31), followed by a partial poly etch to minimize the poly-drain overlap (see FIG. 32) resulting in the device shown in FIG. 33.
  • a poly implant 34 using a mask (not shown) illustrated in FIG. 35 is performed.
  • a subsequent oxidation step results in the formation of a poly oxide layer 36 that is used to minimize overlap capacitance (see FIG. 36).
  • nitride layer 26 is removed as shown in FIG. 37.
  • a P+ selective Si deposition for formation the drain contact 38 is performed (see FIG. 20A).
  • the two tip (P+) regions 20 and 22 are formed automatically by thermal diffusion from the source and drain regions.
  • the remaining steps of this second embodiment are the same as those illustrated above in FIGS. 21 - 24 and 38 .
  • FIG. 39 is a clearly labeled example of the device 60 formed by following the above manufacturing steps.
  • the device 60 includes a first gate 62 and a second gate 64 .
  • Source contacts 66 are made where ILD is directly on top of the substrate as shown.
  • the two gates 62 and 64 share a common drain 70 .
  • FIG. 40 shows an example of a top view of the device 60 . Use of an endcap 43 for the channel region beyond the poly boundary is necessary to separate the two gates as shown in FIG. 40.
  • a third embodiment may be followed to extend the above concept. Beginning with the device illustrated in FIG. 21, a layer 70 of oxide is deposited as illustrated in FIG. 41. A mask is then applied (not shown) and the oxide is patterned to form a trench 72 , as illustrated in FIG. 42. Selective deposition of Si is then deposited in trench 72 for the next layer device. From this point forward, the steps of the described embodiments can be followed to fabricate a stacked series of gates, as shown in FIG. 43. In one embodiment having a stacked series of gates, the first and second gate electrodes share a common source and drain as do the third and fourth gate electrodes. In a further embodiment, the common drain of the first and second gate electrodes also acts as the common source of the third and fourth gate electrodes.

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Abstract

A dual gate transistor device and method for fabricating the same. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a plurality of gate electrodes are formed next to the gate oxide layer and a drain is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region, a drain region, a first gate electrode, and a second gate electrode.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention relates to the fabrication of integrated circuit devices on a semiconductor substrate. More particularly, the present invention relates to the fabrication of dual gate floating body MOS transistors. [0002]
  • 2. Description of Related Art [0003]
  • As the semiconductor industry moves to smaller device feature sizes for ultra large integration (ULSI), transistor performance is expected in general to improve. However, the increased short channel effects due to the smaller feature sizes tends to limit the improved transistor performance. For example, in the past, field effect transistors (FETs) had gate electrodes and interconnecting lines made of polysilicon with widths that were greater than a micrometer (μm). Now the widths are much less than 0.15 μm, which leads to increased short channel effects. The increase in short channel effects results in higher transistor off state leakage, reduced current drive, and increased transition, all of which are detrimental in current day ULSI applications. [0004]
  • Silicon-on-insulator (SOI) technology, an important integrated circuit technology, deals with forming transistors in a layer of semiconductor material that overlies an insulating later. A common embodiment of SOI structures has a single crystal layer of silicon that overlies a layer of silicon dioxide. High performance and high density integrated circuits are achievable using SOI technology, because of the reduced parasitic elements that are present in the integrated circuits that use SOI transistors. Problems exist with SOI transistor technology, however, relating to the floating body in partially depleted SOI technology. [0005]
  • ULSI MOSFET devices are being continuously scaled down in channel length due to the increasing need for higher packing density and higher device speed. However, the continuous scaling down of geometry requires new transistor structures. Some innovative device structures and processes have been proposed that achieve the high performance of these small geometry devices, and yet can be made without requiring complicated fabrication techniques. One such device structure is a vertical MOSFET structure that provides a dual gate device which solves the floating body problem of partially depleted SOI transistors. A second important advantage of vertical MOS transistor technology is that the channel length scaling is not limited by the minimum lithographic resolution. The transistor channel length is instead determined by shallow trench etching and epitaxial layer growth techniques. [0006]
  • Transistors having two gate electrodes are known in the art, wherein there is a top gate and a bottom gate that may or may not be inherently self-aligned to the source/drain. N-channel double-gate MOSFET's with a 25 nm thick silicon channel have been successfully demonstrated. However, the process flow used to fabricate the two gate electrodes is complex and often uses non self-aligned source and drains. Further, although fully depleted floating body MOS devices have been proposed using planar transistors and SOI technology, they do not offer voltage control on the second gate, they require advanced SOI, advanced start material (thin body, thin box), and STI isolation. Thus, an improved structure and process flow allowing for fabrication of dual gate floating body NMOS and PMOS transistors is desired. [0007]
  • SUMMARY OF THE INVENTION
  • A dual gate transistor device and method for fabricating the same is described. First, a doped substrate is prepared with a patterned oxide layer on the doped substrate defining a channel. Next, a silicon layer is deposited to form the channel, with a gate oxide layer then grown adjacent the channel. Subsequently, a first and a second gate electrode are formed next to the gate oxide layer, and a drain region is formed on the channel. After the drain is formed, an ILD layer is deposited. This ILD layer is etched to form a source region, a drain region, a first gate electrode, and a second gate electrode. [0008]
  • BRIEF DESCRIPTION OF THE DRAWING
  • The invention is further described by way of example with reference to the accompanying drawings, wherein: [0009]
  • FIG. 1 is a cross-sectional view of a starting substrate for the manufacturing process for the device of the present invention. [0010]
  • FIG. 2 is a cross-sectional view of the P+ region of FIG. 1 that forms the basis of the fabrication process of the PMOS device to be described. [0011]
  • FIG. 3 is a cross-sectional view of the P+ layer of FIG. 2 with a layer of oxide deposited thereon. [0012]
  • FIG. 4 is a cross-sectional view of the layers illustrated in FIG. 3 with a mask deposited and patterned thereon. [0013]
  • FIG. 5 is a cross-sectional view of the trench formed in the exposed portion illustrated in FIG. 4. [0014]
  • FIG. 6 is a cross-sectional view of the trench formed in FIG. 5 with the mask removed. [0015]
  • FIG. 7 is a cross-sectional view of the device of FIG. 6 with selective doped Si deposition into the [0016] trench 18.
  • FIG. 8 is a cross-sectional view of a sacrificial layer of nitride deposited on the device illustrated in FIG. 7. [0017]
  • FIG. 9 is a cross-sectional view illustrating the device of FIG. 8 after a nitride polish. [0018]
  • FIG. 10 is a cross-sectional view of the device of FIG. 9 after a partial oxide etch is performed. [0019]
  • FIG. 11 is a cross-sectional view of the device of FIG. 10 after gate oxidation. [0020]
  • FIG. 12 is a cross-sectional view of the device of FIG. 11 after poly deposition forms a layer over the device and a poly polish levels the poly layer such that it is approximately level with the nitride layer of FIG. 12. [0021]
  • FIG. 13 is a cross-sectional view of the [0022] device 12 with a mask applied for patterning the poly layer.
  • FIG. 14 is a cross-sectional view of the device showing the poly layer as it is patterned. [0023]
  • FIG. 15 is a cross-sectional view of the device of [0024] 14 after the mask is removed.
  • FIG. 16 is a cross-sectional view of the device of FIG. 15 after a partial poly etch is performed. [0025]
  • FIG. 17 is a cross-sectional view of the device of FIG. 16 as the poly layer is doped using a poly implant. [0026]
  • FIG. 18 is a cross-sectional view of the device of FIG. 17 after oxidation with the resulting [0027] poly oxide layer 36 illustrated.
  • FIG. 19 is a cross-sectional view of the device of FIG. 18 with the nitride layer removed. [0028]
  • FIG. 20A is a cross-sectional view of the device of FIG. 19 illustrating the formation of the drain contact through selective Si deposition. [0029]
  • FIG. 20B is a cross-sectional view of the device of FIG. 19 illustrating the formation of the drain contact through depositing a poly-Si layer that is then masked for and patterned. [0030]
  • FIG. 21 is a cross-sectional view of the device of FIG. 20A after an oxide etch is performed to remove the exposed sections of oxide layers. [0031]
  • FIG. 22 is a cross-sectional view of the device of FIG. 21 illustrating the [0032] nitride spacers 41 created and a subsequent salicidation process.
  • FIG. 23 is a cross-sectional view of the device of FIG. 22 illustrating an ILD deposition and polish. [0033]
  • FIG. 24 is a cross-sectional view of the device of FIG. 23 with a mask applied. [0034]
  • FIG. 25 is a cross-sectional view of the device of FIG. 6 with a selective Si deposition formed in the trench. [0035]
  • FIG. 26 is a cross-sectional view of the device of FIG. 25 after deposition of a sacrificial layer of nitride. [0036]
  • FIG. 27 is a cross-sectional view of the device of FIG. 26 after the nitride layer has been polished. [0037]
  • FIG. 28 is a cross-sectional view of the device of FIG. 27 after a partial oxide etch is performed. [0038]
  • FIG. 29 is a cross-sectional view of the device of FIG. 28 after gate oxidation. [0039]
  • FIG. 30 is a cross-sectional view of the device of FIG. 29 after a poly deposition and polish. [0040]
  • FIG. 31 is a cross-sectional view of the device of FIG. 30 with a mask applied. [0041]
  • FIG. 32 is a cross-sectional view of the device of FIG. 31 showing the poly layer as it is patterned. [0042]
  • FIG. 33 is a cross-sectional view of the device of FIG. 32 after the mask has been removed. [0043]
  • FIG. 34 is a cross-sectional view of the device of FIG. 33 after a partial poly etch. [0044]
  • FIG. 35 is a cross-sectional view of the device of FIG. 34 showing a poly implant. [0045]
  • FIG. 36 is a cross-sectional view of the device of FIG. 35 after the formation of a poly oxide layer. [0046]
  • FIG. 37 is a cross-sectional view of the device of FIG. 36 after the nitride layer is removed. [0047]
  • FIG. 38 is a cross-sectional view of the device of the present invention. [0048]
  • FIG. 39 is a cross-sectional view of the device of the present invention with each of the different gates, sources and drain labeled. [0049]
  • FIG. 40 is a top view of the device illustrated in FIG. 38. [0050]
  • FIG. 41 is a cross-sectional view of the device of FIG. 18 with a layer of oxide deposited thereon. [0051]
  • FIG. 42 is a cross-sectional view of the device of [0052] 41 after the oxide layer has been patterned.
  • FIG. 43 is a cross-sectional view of selective deposition of Si for a second layer device. [0053]
  • DETAILED DESCRIPTION
  • An improved method for fabricating dual gate floating body NMOS and PMOS transistors is disclosed. In the following description, numerous specific details are set forth such as specific materials, process parameters, dimensions, etc. in order to provide a thorough understanding of the present invention. It will be obvious, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well-known materials or methods have not been described in detail in order to avoid unnecessarily obscuring the present invention. [0054]
  • The present invention relates to dual gate floating body NMOS and PMOS transistors fabricated by a process offering several advantages over the prior art. The process disclosed herein requires only two to three additional masking steps when compared with conventional bulk MOS processing. The process flow described does not require silicon-on-insulator (SOI) technology or epi wafers as start material, offers full control over the second transistor gate based on planar interconnects, does not need STI isolation, and offers potential for successive vertical integration of multiple levels of transistors. [0055]
  • The present invention discloses an apparatus and method for the fabrication of the dual gate floating body NMOS and PMOS transistors described herein, however, the process flow will be discussed using the PMOS device as an example. Note that the NMOS device is fabricated in a parallel procedure, with the opposite dopants resulting in NMOS transistors. FIGS. [0056] 1-24 illustrate the process steps of a first embodiment of fabricating a dual gate floating body transistor.
  • FIG. 1 is a cross-sectional view of a starting substrate [0057] 10 for the process described herein. An SOI or epi wafer is not required for the starting substrate. Similarly, LOCOS or STI isolation is not needed, but n-well, N+, and P+ masks are needed here. The process flow described below will use merely the PMOS device 12 as an example and to simplify the following explanation. (Note, however, that the NMOS device may be fabricated with the opposite dopants in parallel along side the PMOS device.) Thus, FIG. 2 is a side view of the P+ layer 12 that forms the basis of the fabrication process described below.
  • FIG. 3 is a side cross-sectional view of the [0058] P+ layer 12 with a layer of oxide 14 (e.g., SiO2) deposited or grown thereon. In one embodiment of the present invention, both the P+ layer 12 and the oxide layer 14 have an approximate thickness of 0.5 μm. Once the oxide layer 14 has been deposited, the oxide layer 14 must be patterned separately (using two masks) for the NMOS and the PMOS transistors. FIG. 4 illustrates the addition of one mask 16 for the masking of the oxide layer 14 used to pattern the oxide layer 14 for the PMOS transistor. It will be obvious to one with ordinary skill in the art that oxide layer 14 may be patterned using well known photolithographic masking and etching techniques, resulting in the trench 18 illustrated in FIG. 5 and again in FIG. 6 after the removal of the mask 16.
  • FIG. 7 illustrates the device during selective Si deposition, generally formed using epitaxial growth, into the [0059] trench 18 with in-situ doping of the shown layers. Alternatively, the two tip (P+) regions 20 and 22 shown can form automatically by thermal diffusion, with the middle region 24 remaining an undoped Si layer. This alternative embodiment will be discussed in detail below. In one embodiment of the present invention, the trench 18 has an approximate thickness of 0.2 μm and regions 20, 22, and 24 have a combined thickness of approximately 0.4 μm. After the Si deposition into trench 18, a sacrificial layer 26 of nitride is deposited, as illustrated in FIG. 8. In one embodiment of the present invention, the sacrificial layer 26 of nitride has an approximate thickness of 0.4 μm. FIG. 9 illustrates the device after a nitride polish, resulting in a nitride layer 26 filling the remainder of trench 18.
  • Next, a partial oxide etch is performed to remove the majority of [0060] oxide layer 14 as illustrated in FIG. 10. The oxide etch leaves a portion (e.g., approximately 0.1 μm) of the oxide layer 14 to minimize overlap capacitance. Next, gate oxidation is performed to grow oxide regions 28 as illustrated in FIG. 11. In one embodiment of the present invention, oxide regions 28 have an approximate thickness of 15 Å. Note that if (110) oriented start material (layer 12) is used, the oxidation will be along the (100) oriented plane. An alternative embodiment also uses sacrificial oxidation and etching prior to the gate oxidation to thin the channel region.
  • After the gate oxidation, poly deposition forms a layer over the device fabricated thus far. A poly polish is then used to level the [0061] poly layer 30 such that it is approximately level with the nitride level 26, as shown in FIG. 12. In one embodiment of the present invention, the poly layer 30 after polish is approximately 0.4 μm. Next, a mask 32 is placed above the poly layer 30 (see FIG. 13), such that the poly layer 30 may be patterned (see FIG. 14). The mask 32 is subsequently removed, leaving patterned poly layer 30 as illustrated in FIG. 15.
  • A partial poly etch, such as a plasma etch, is then performed to minimize the poly-drain overlap. The etch produces a [0062] thinner poly layer 30 as evident in FIG. 16. In one embodiment of the present invention, the poly layer after etch is approximately 0.3 μm. Note that the poly-drain overlap can cause increased capacitance resulting in a slower transistor. Next, the poly layer 30 is doped using a poly implant 34 (note the use of a mask is not shown in the illustration) as shown in FIG. 17. This is followed by poly oxidation to further minimize the overlap capacitance. After oxidation, the poly layer has an approximate thickness of 0.2 μm. This results in a poly oxide layer 36 having an approximate thickness of 0.2 μm adjacent the poly layer 30 as shown in FIG. 18. In another embodiment, poly doping may be performed in-situ during poly deposition. In that case, the poly implant step above will not be required.
  • After the poly oxidation, the [0063] nitride layer 26 is removed with an etching step, such as a plasma etch, as illustrated in FIG. 19. Next, selective Si deposition is applied using an epitaxial growth process to form the drain region, which is then doped to form layer 38 (as shown in FIG. 20A). In one embodiment of the present invention, layer 38 has an approximate thickness of 0.5 μm. The P+ dopant may be implanted into layer 38 or created by in-situ deposition. The resulting layer 38 tends to look like a mushroom and may need further optimization since it often gets too thick. FIG. 20B illustrates a second, alternative step to that described above. Instead of using a selective Si deposition for the drain region, in this alternative step, a poly-Si layer 40 is deposited and then masked for patterning (not shown). Then, as with the above step, the P+ dopant may be implanted using a mask process (also not shown). In one embodiment, the poly-Si layer 40 has an approximate thickness of 0.5 μm.
  • After the drain region (whether [0064] 38 or 40) has been deposited, an oxide etch is then performed to remove the exposed sections of layer 14 of SiO2 and layer 36 of poly oxide as is illustrated in FIG. 21. Next, nitride spacers 41 are created using the same techniques as performed in conventional MOS fabrication. Subsequently, the salicidation process forms salicide layer 42 as shown in FIG. 22. In one embodiment, salicide layer 42 has an approximate thickness of 300 Å. The formation of the spacer 41 is followed by an ILD deposition 44 having an approximate thickness of 1.5 μm and polish as illustrated in FIG. 23. A mask 46 is then applied (see FIG. 24) followed by a contact etching step, resulting in the device 60 illustrated in FIG. 38 and labeled more extensively in FIG. 39.
  • An alternative method of forming the [0065] device 60 is illustrated in FIGS. 25-37. The method illustrated in FIGS. 25-37 is simpler and provides more control over the dimensions of the tips and channels in the final device 60. The initial steps are the same as the above described embodiment and illustrated in FIGS. 1-6. After trench 18 is formed in the SiO2 layer 14, a selective Si deposition is formed in trench 18 to form layer 48, as shown in FIG. 25. Unlike above, however, doping to form the tip regions is not done at this step. Next, a sacrificial layer 26 of nitride is deposited (see FIG. 26) and then polished (see FIG. 27).
  • After the nitride deposition and polishing, a partial oxide etch is performed on [0066] layer 14, leaving, for example, approximately 0.1 μm of SiO2 to minimize overlap capacitance (see FIG. 28). Next, gate oxidation is performed to produce regions 28 (see FIG. 29). The gate oxidation is followed by a poly deposition and poly polish to form layer 30 as illustrated in FIG. 30. A mask 32 is then applied (see FIG. 31), followed by a partial poly etch to minimize the poly-drain overlap (see FIG. 32) resulting in the device shown in FIG. 33. After the partial poly etch, a poly implant 34 using a mask (not shown) illustrated in FIG. 35 is performed. A subsequent oxidation step results in the formation of a poly oxide layer 36 that is used to minimize overlap capacitance (see FIG. 36).
  • Next, [0067] nitride layer 26 is removed as shown in FIG. 37. Once the nitride layer 26 is removed, a P+ selective Si deposition for formation the drain contact 38 is performed (see FIG. 20A). The two tip (P+) regions 20 and 22 are formed automatically by thermal diffusion from the source and drain regions. The remaining steps of this second embodiment are the same as those illustrated above in FIGS. 21-24 and 38.
  • FIG. 39 is a clearly labeled example of the [0068] device 60 formed by following the above manufacturing steps. The device 60 includes a first gate 62 and a second gate 64. Source contacts 66 are made where ILD is directly on top of the substrate as shown. The two gates 62 and 64 share a common drain 70. FIG. 40 shows an example of a top view of the device 60. Use of an endcap 43 for the channel region beyond the poly boundary is necessary to separate the two gates as shown in FIG. 40.
  • Note that a third embodiment may be followed to extend the above concept. Beginning with the device illustrated in FIG. 21, a [0069] layer 70 of oxide is deposited as illustrated in FIG. 41. A mask is then applied (not shown) and the oxide is patterned to form a trench 72, as illustrated in FIG. 42. Selective deposition of Si is then deposited in trench 72 for the next layer device. From this point forward, the steps of the described embodiments can be followed to fabricate a stacked series of gates, as shown in FIG. 43. In one embodiment having a stacked series of gates, the first and second gate electrodes share a common source and drain as do the third and fourth gate electrodes. In a further embodiment, the common drain of the first and second gate electrodes also acts as the common source of the third and fourth gate electrodes.

Claims (23)

We claim:
1. A method of fabricating a dual gate MOS transistor device, comprising:
providing a doped substrate;
patterning an oxide layer on said doped substrate to define a channel;
depositing a silicon layer to form said channel;
growing a gate oxide layer adjacent said channel;
forming a first and a second gate electrode adjacent said gate oxide layer;
forming a drain region on said channel;
performing ILD deposition; and, etching said ILD to form a source region, a drain region, a first gate electrode, and a second gate electrode.
2. The method of claim 1 wherein etching said ILD further comprises etching said ILD to form a source region, a drain region, a first gate electrode, and a second gate electrode, wherein said first and second gate electrodes are approximately planar.
3. The method of claim 1 further comprising forming tip regions in said channel by in-situ doping.
4. The method of claim 1 wherein forming a drain region further comprises forming a drain region with selective silicon deposition.
5. The method of claim 1 wherein forming a drain region further comprises forming a drain region by depositing a layer of poly-silicon and then patterning said poly-silicon layer to form said drain region.
6. A method of fabricating a dual gate MOS transistor device, comprising:
providing a doped substrate;
patterning an oxide layer on said doped substrate to define a channel;
depositing a silicon layer to form said channel;
forming doped tip regions in said channel;
growing a gate oxide layer adjacent said channel;
forming a first and a second gate electrode adjacent said gate oxide layer;
forming a drain region on said channel;
performing ILD deposition; and, etching said ILD to form a source region, a drain region, a first gate electrode, and a second gate electrode.
7. The method of claim 6 wherein etching said ILD further comprises etching said ILD to form a source region, a drain region, a first gate electrode, and a second gate electrode, wherein said first and second gate electrodes are approximately planar.
8. The method of claim 6 further comprising forming tip regions in said channel by thermal diffusion.
9. The method of claim 6 wherein forming a drain region further comprises forming a drain region with selective silicon deposition.
10. The method of claim 6 wherein forming a drain region further comprises forming a drain region by depositing a layer of poly-silicon and then patterning said poly-silicon layer to form said drain region.
11. An apparatus comprising:
a substrate doped with a conductive type dopant;
a first gate electrode on said substrate; and,
a second gate electrode on said substrate, wherein said first and second gate electrodes are approximately planar.
12. The apparatus of claim 11 wherein said first and second gate electrodes share a common drain and a common source.
13. The apparatus of claim 11 further comprising a dual gate floating body NMOS transistor.
14. The apparatus of claim 11 further comprising a dual gate floating body PMOS transistor.
15. The apparatus of claim 12 further comprising a third and a fourth gate electrode, wherein said third and fourth gate electrodes are approximately planar, said third and fourth gate electrodes are stacked above said first and second gate electrodes, and said third and fourth gate electrodes share a common drain and a common source.
16. The apparatus of claim 15 wherein said common drain of said first and second gate electrodes is also said common source of said third and fourth gate electrodes.
17. The apparatus of claim 11 wherein both P and N doped transistor devices are formed on said substrate to provide MOS field effect transistor circuit capability.
18. A method of fabricating a dual gate MOS transistor device, comprising:
providing a substrate having a P+ doped region and an N+ doped region;
patterning an oxide layer on said substrate to define a first channel in said P+ doped region and a second channel in said N+ doped region;
depositing a silicon layer to form said first and said second channels;
growing a gate oxide layer adjacent said first and second channels;
forming a first and a second gate electrode adjacent said gate oxide layer and said first channel;
forming a third and a fourth gate electrode adjacent said gate oxide layer and said second channel;
forming a first drain region on said first channel and a second drain region on said second channel;
performing ILD deposition;
etching said ILD to form a first source region, a first drain region, and a first and a second gate electrode on said first channel; and, etching said ILD to form a second source region, a second drain region, and a third and a fourth gate electrode on said second channel.
19. The method of claim 18 wherein etching said ILD further comprises:
etching said ILD to form a first source region, a first drain region, and a first and a second gate electrode on said first channel, wherein said first and second gate electrodes are approximately planar; and, etching said ILD to form a second source region, a second drain region, and a third and a fourth gate electrode on said second channel, wherein said third and fourth gate electrodes are approximately planar.
20. The method of claim 18 further comprising forming tip regions in said first and second channels by in-situ doping.
21. The method of claim 18 further comprising forming tip regions in said first and second channels by thermal diffusion.
22. The method of claim 18 wherein forming a first and a second drain region further comprises:
forming a first drain region on said first channel with selective silicon deposition; and, forming a second drain region on said second channel with selective silicon deposition.
23. The method of claim 18 wherein forming a first and a second drain region further comprises:
forming a first drain region on said first channel by depositing a layer of poly-silicon and then pattering said poly-silicon layer to form said first drain region; and,
forming a second drain region on said second channel by depositing a layer of poly-silicon and then patterning said poly-silicon layer to form said second drain region.
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Cited By (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680504B2 (en) * 2000-12-22 2004-01-20 Texas Instruments Incorporated Method for constructing a metal oxide semiconductor field effect transistor
US20090045458A1 (en) * 2007-08-15 2009-02-19 Advanced Micro Devices, Inc. Mos transistors for thin soi integration and methods for fabricating the same
US20100207201A1 (en) * 2008-01-29 2010-08-19 Fujio Masuoka Semiconductor device and production method therefor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US20110215381A1 (en) * 2010-03-08 2011-09-08 Fujio Masuoka Solid state imaging device
US8343835B2 (en) 2008-01-29 2013-01-01 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US8487357B2 (en) 2010-03-12 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high sensitivity and high pixel density
US8486785B2 (en) 2010-06-09 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
US8564034B2 (en) 2011-09-08 2013-10-22 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8669601B2 (en) 2011-09-15 2014-03-11 Unisantis Electronics Singapore Pte. Ltd. Method for producing semiconductor device and semiconductor device having pillar-shaped semiconductor
US8748938B2 (en) 2012-02-20 2014-06-10 Unisantis Electronics Singapore Pte. Ltd. Solid-state imaging device
US8772175B2 (en) 2011-12-19 2014-07-08 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US8916478B2 (en) 2011-12-19 2014-12-23 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing semiconductor device and semiconductor device
US9153697B2 (en) 2010-06-15 2015-10-06 Unisantis Electronics Singapore Pte Ltd. Surrounding gate transistor (SGT) structure
US20170047328A1 (en) * 2013-09-03 2017-02-16 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device with surrounding gate transistors in a nand circuit
US9859421B1 (en) * 2016-09-21 2018-01-02 International Business Machines Corporation Vertical field effect transistor with subway etch replacement metal gate

Families Citing this family (48)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6297531B2 (en) * 1998-01-05 2001-10-02 International Business Machines Corporation High performance, low power vertical integrated CMOS devices
FR2810792B1 (en) * 2000-06-22 2003-07-04 Commissariat Energie Atomique MIG VERTICAL BURST TRANSISTOR AND METHOD OF MANUFACTURING THE SAME
US6426259B1 (en) * 2000-11-15 2002-07-30 Advanced Micro Devices, Inc. Vertical field effect transistor with metal oxide as sidewall gate insulator
US6599789B1 (en) * 2000-11-15 2003-07-29 Micron Technology, Inc. Method of forming a field effect transistor
US7176109B2 (en) * 2001-03-23 2007-02-13 Micron Technology, Inc. Method for forming raised structures by controlled selective epitaxial growth of facet using spacer
DE10142913B4 (en) * 2001-08-27 2004-03-18 Hahn-Meitner-Institut Berlin Gmbh Vertical transistor arrangement with a flexible substrate consisting of plastic films and method for the production thereof
US6798017B2 (en) * 2001-08-31 2004-09-28 International Business Machines Corporation Vertical dual gate field effect transistor
TW502453B (en) * 2001-09-06 2002-09-11 Winbond Electronics Corp MOSFET and the manufacturing method thereof
US6774437B2 (en) * 2002-01-07 2004-08-10 International Business Machines Corporation Fin-based double poly dynamic threshold CMOS FET with spacer gate and method of fabrication
US6580132B1 (en) * 2002-04-10 2003-06-17 International Business Machines Corporation Damascene double-gate FET
US7071043B2 (en) * 2002-08-15 2006-07-04 Micron Technology, Inc. Methods of forming a field effect transistor having source/drain material over insulative material
US6784491B2 (en) * 2002-09-27 2004-08-31 Intel Corporation MOS devices with reduced fringing capacitance
US6890813B2 (en) * 2003-01-06 2005-05-10 Intel Corporation Polymer film metalization
US6998670B2 (en) * 2003-04-25 2006-02-14 Atmel Corporation Twin EEPROM memory transistors with subsurface stepped floating gates
US6974733B2 (en) * 2003-06-16 2005-12-13 Intel Corporation Double-gate transistor with enhanced carrier mobility
US6909125B2 (en) * 2003-07-08 2005-06-21 Texas Instruments Incorporated Implant-controlled-channel vertical JFET
US6888199B2 (en) * 2003-10-07 2005-05-03 International Business Machines Corporation High-density split-gate FinFET
EP1709680A4 (en) * 2004-01-21 2008-07-02 Atmel Corp VERTICAL GRID CMOS WITH INDEPENDENT GRID LENGTH OF LITHOGRAPHY
US7141476B2 (en) * 2004-06-18 2006-11-28 Freescale Semiconductor, Inc. Method of forming a transistor with a bottom gate
US7132751B2 (en) * 2004-06-22 2006-11-07 Intel Corporation Memory cell using silicon carbide
US7190616B2 (en) * 2004-07-19 2007-03-13 Micron Technology, Inc. In-service reconfigurable DRAM and flash memory device
US7259420B2 (en) * 2004-07-28 2007-08-21 International Business Machines Corporation Multiple-gate device with floating back gate
US7262099B2 (en) * 2004-08-23 2007-08-28 Micron Technology, Inc. Methods of forming field effect transistors
US7144779B2 (en) * 2004-09-01 2006-12-05 Micron Technology, Inc. Method of forming epitaxial silicon-comprising material
US7132355B2 (en) * 2004-09-01 2006-11-07 Micron Technology, Inc. Method of forming a layer comprising epitaxial silicon and a field effect transistor
US8673706B2 (en) * 2004-09-01 2014-03-18 Micron Technology, Inc. Methods of forming layers comprising epitaxial silicon
US7547945B2 (en) 2004-09-01 2009-06-16 Micron Technology, Inc. Transistor devices, transistor structures and semiconductor constructions
US7531395B2 (en) * 2004-09-01 2009-05-12 Micron Technology, Inc. Methods of forming a layer comprising epitaxial silicon, and methods of forming field effect transistors
US7384849B2 (en) 2005-03-25 2008-06-10 Micron Technology, Inc. Methods of forming recessed access devices associated with semiconductor constructions
US7387946B2 (en) * 2005-06-07 2008-06-17 Freescale Semiconductor, Inc. Method of fabricating a substrate for a planar, double-gated, transistor process
US7282401B2 (en) 2005-07-08 2007-10-16 Micron Technology, Inc. Method and apparatus for a self-aligned recessed access device (RAD) transistor gate
US7867851B2 (en) 2005-08-30 2011-01-11 Micron Technology, Inc. Methods of forming field effect transistors on substrates
US7679125B2 (en) 2005-12-14 2010-03-16 Freescale Semiconductor, Inc. Back-gated semiconductor device with a storage layer and methods for forming thereof
US7700441B2 (en) 2006-02-02 2010-04-20 Micron Technology, Inc. Methods of forming field effect transistors, methods of forming field effect transistor gates, methods of forming integrated circuitry comprising a transistor gate array and circuitry peripheral to the gate array, and methods of forming integrated circuitry comprising a transistor gate array including first gates and second grounded isolation gates
US7602001B2 (en) 2006-07-17 2009-10-13 Micron Technology, Inc. Capacitorless one transistor DRAM cell, integrated circuitry comprising an array of capacitorless one transistor DRAM cells, and method of forming lines of capacitorless one transistor DRAM cells
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
US7589995B2 (en) 2006-09-07 2009-09-15 Micron Technology, Inc. One-transistor memory cell with bias gate
US7410856B2 (en) * 2006-09-14 2008-08-12 Micron Technology, Inc. Methods of forming vertical transistors
FR2916902B1 (en) * 2007-05-31 2009-07-17 Commissariat Energie Atomique FIELD EFFECT TRANSISTOR WITH CARBON NANOTUBES
US7923373B2 (en) 2007-06-04 2011-04-12 Micron Technology, Inc. Pitch multiplication using self-assembling materials
JP2009123882A (en) * 2007-11-14 2009-06-04 Elpida Memory Inc Semiconductor device and manufacturing method thereof
JP5623005B2 (en) * 2008-02-01 2014-11-12 ピーエスフォー ルクスコ エスエイアールエルPS4 Luxco S.a.r.l. Semiconductor device and manufacturing method thereof
WO2009110048A1 (en) * 2008-02-15 2009-09-11 日本ユニサンティスエレクトロニクス株式会社 Semiconductor devuce and manufacturing method thereof
WO2009153880A1 (en) * 2008-06-20 2009-12-23 日本ユニサンティスエレクトロニクス株式会社 Semiconductor storage device
KR101950003B1 (en) 2012-08-31 2019-04-25 에스케이하이닉스 주식회사 Semiconductor device and method for forming the same
US9812555B2 (en) 2015-05-28 2017-11-07 Semiconductor Components Industries, Llc Bottom-gate thin-body transistors for stacked wafer integrated circuits
US9564464B2 (en) 2015-06-03 2017-02-07 Semiconductor Components Industries, Llc Monolithically stacked image sensors
US9812567B1 (en) * 2016-05-05 2017-11-07 International Business Machines Corporation Precise control of vertical transistor gate length

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS577162A (en) 1980-06-17 1982-01-14 Toshiba Corp Nonvolatile semiconductor memory and manufacture therefor
US4517731A (en) * 1983-09-29 1985-05-21 Fairchild Camera & Instrument Corporation Double polysilicon process for fabricating CMOS integrated circuits
US4835586A (en) * 1987-09-21 1989-05-30 Siliconix Incorporated Dual-gate high density fet
US5172200A (en) 1990-01-12 1992-12-15 Mitsubishi Denki Kabushiki Kaisha MOS memory device having a LDD structure and a visor-like insulating layer
US5243234A (en) 1991-03-20 1993-09-07 Industrial Technology Research Institute Dual gate LDMOSFET device for reducing on state resistance
US5298463A (en) * 1991-08-30 1994-03-29 Micron Technology, Inc. Method of processing a semiconductor wafer using a contact etch stop
US5266507A (en) 1992-05-18 1993-11-30 Industrial Technology Research Institute Method of fabricating an offset dual gate thin film field effect transistor
US5482871A (en) 1994-04-15 1996-01-09 Texas Instruments Incorporated Method for forming a mesa-isolated SOI transistor having a split-process polysilicon gate
US5757038A (en) 1995-11-06 1998-05-26 International Business Machines Corporation Self-aligned dual gate MOSFET with an ultranarrow channel
US5723893A (en) 1996-05-28 1998-03-03 Taiwan Semiconductor Manufacturing Company, Ltd. Method for fabricating double silicide gate electrode structures on CMOS-field effect transistors
US6034389A (en) * 1997-01-22 2000-03-07 International Business Machines Corporation Self-aligned diffused source vertical transistors with deep trench capacitors in a 4F-square memory cell array
US5990509A (en) * 1997-01-22 1999-11-23 International Business Machines Corporation 2F-square memory cell for gigabit memory applications
US6320222B1 (en) * 1998-09-01 2001-11-20 Micron Technology, Inc. Structure and method for reducing threshold voltage variations due to dopant fluctuations
US6107660A (en) * 1999-05-19 2000-08-22 Worldwide Semiconductor Manufacturing Corp. Vertical thin film transistor

Cited By (33)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6680504B2 (en) * 2000-12-22 2004-01-20 Texas Instruments Incorporated Method for constructing a metal oxide semiconductor field effect transistor
US20090045458A1 (en) * 2007-08-15 2009-02-19 Advanced Micro Devices, Inc. Mos transistors for thin soi integration and methods for fabricating the same
US8482041B2 (en) 2007-10-29 2013-07-09 Unisantis Electronics Singapore Pte Ltd. Semiconductor structure and method of fabricating the semiconductor structure
US20100207201A1 (en) * 2008-01-29 2010-08-19 Fujio Masuoka Semiconductor device and production method therefor
US8343835B2 (en) 2008-01-29 2013-01-01 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8372713B2 (en) 2008-01-29 2013-02-12 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8598650B2 (en) 2008-01-29 2013-12-03 Unisantis Electronics Singapore Pte Ltd. Semiconductor device and production method therefor
US8497548B2 (en) 2009-04-28 2013-07-30 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
US20100270611A1 (en) * 2009-04-28 2010-10-28 Fujio Masuoka Semiconductor device including a mos transistor and production method therefor
US8647947B2 (en) 2009-04-28 2014-02-11 Unisantis Electronics Singapore Pte Ltd. Semiconductor device including a MOS transistor and production method therefor
EP2246893A3 (en) * 2009-04-28 2012-07-25 Unisantis Electronics Singapore Pte. Ltd. Semiconductor device including a MOS transistor and a production method therefor
US8610202B2 (en) 2009-10-01 2013-12-17 Unisantis Electronics Singapore Pte Ltd. Semiconductor device having a surrounding gate
US20110079841A1 (en) * 2009-10-01 2011-04-07 Fujio Masuoka Semiconductor device
US8575662B2 (en) 2010-03-08 2013-11-05 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high pixel density
US20110215381A1 (en) * 2010-03-08 2011-09-08 Fujio Masuoka Solid state imaging device
US8487357B2 (en) 2010-03-12 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Solid state imaging device having high sensitivity and high pixel density
US8486785B2 (en) 2010-06-09 2013-07-16 Unisantis Electronics Singapore Pte Ltd. Surround gate CMOS semiconductor device
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US9859421B1 (en) * 2016-09-21 2018-01-02 International Business Machines Corporation Vertical field effect transistor with subway etch replacement metal gate

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