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US20020023766A1 - Method and apparatus for polygonal heat slug - Google Patents

Method and apparatus for polygonal heat slug Download PDF

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Publication number
US20020023766A1
US20020023766A1 US09/842,305 US84230501A US2002023766A1 US 20020023766 A1 US20020023766 A1 US 20020023766A1 US 84230501 A US84230501 A US 84230501A US 2002023766 A1 US2002023766 A1 US 2002023766A1
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Prior art keywords
package
top surface
heat slug
circuit board
printed circuit
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Granted
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US09/842,305
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US6459563B1 (en
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Robert Chroneos
Koushik Banerjee
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/16—Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • H01L23/18—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device
    • H01L23/24—Fillings characterised by the material, its physical or chemical properties, or its arrangement within the complete device solid or gel at the normal operating temperature of the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/642—Capacitive arrangements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
    • H01L2224/491—Disposition
    • H01L2224/49105—Connecting at different heights
    • H01L2224/49109—Connecting at different heights outside the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01027—Cobalt [Co]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01028—Nickel [Ni]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/15165—Monolayer substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/1901—Structure
    • H01L2924/1904—Component type
    • H01L2924/19041—Component type being a capacitor

Definitions

  • the present invention relates to a package for an integrated circuit.
  • Integrated circuits are typically housed within a package that is soldered to a printed circuit board. Some packages contain a heat slug to facilitate the removal of heat generated by the integrated circuit. The package may also contain a number of discrete capacitors which filter the power and/or signals provided to the integrated circuit.
  • FIG. 1 shows a top surface of an integrated circuit package 2 of the prior art.
  • the package 2 has a rectangular heat slug 4 that is surrounded by a number of through hole vias 6 .
  • the vias 6 provide interconnect to a plurality of lands located on the opposite bottom surface of the package.
  • the lands are typically soldered to an external printed circuit board.
  • the number of lands for the package are typically limited by the number of vias 6 that can be formed in the package 2 .
  • capacitors 8 Mounted to the top surface of the package are a number of capacitors 8 .
  • the capacitors 8 are mounted to surface pads 10 located on the top surface.
  • the capacitors 8 and accompanying pads are relatively large and occupy valuable space on the top of the package.
  • Some of the vias 6 must be eliminated to provide room for the capacitors. Eliminating vias reduces the number of lands and the pin throughput of the package. Adding more capacitors to the package would necessitate the elimination of more vias and further reduce the output pins of the package. It would be desirable to provide a package design that can add capacitors without eliminating more vias and corresponding lands.
  • FIG. 2 is a top view of an electronic package of the present invention
  • FIGS. 2 - 4 show an electronic package 20 of the present invention.
  • the package 20 has a heat slug 22 extending from the top surface 24 of a substrate 26 .
  • the heat slug 22 has a polygonal shape to reduce the overall area of the slug 22 .
  • the heat slug 22 has an octagonal shape. Although an octagonal shape is shown and described, it is to be understood that the heat slug 22 may have any shape that has at least five sides.
  • the heat slug 22 is preferably constructed from a thermally conductive material such as a nickel plated copper.
  • the substrate 26 is preferably a printed circuit board which has a two-dimensional array of vias 28 .
  • the vias 28 on the top surface of the package 20 typically extend to via pads 30 located on the bottom surface 31 of the package shown in FIG. 3.
  • the via pads 30 are connected to corresponding land pads 32 .
  • the land pads 32 are typically soldered to an external printed circuit board (not shown).
  • land pads 32 in a land grid array (LGA) package are shown and described, it is to be understood that the package may contain pins within a pin grid array package (PGA), or solder bumps within a ball grid array (BGA) package.
  • PGA pin grid array package
  • BGA ball grid array
  • a printed circuit board is shown and described, it is to be understood that the substrate 26 may be constructed from other materials such as co-fired ceramic.
  • the package 20 has a plurality of discrete electronic devices 34 mounted to the top surface of the substrate 26 .
  • the discrete devices 34 are capacitors.
  • the capacitors 34 typically filter power and/or signals provided to the package. Although capacitors are shown and described, it is to be understood that the discrete devices 34 may be any active or passive component such as a resistor.
  • the heat slug 22 is mounted to a surface pad 50 of the circuit board 26 which is dedicated to electrical ground (Vss).
  • Vss electrical ground
  • One surface pad 36 of each device 34 may be routed to the ground pad 50 .
  • the other pad 36 may be connected to one of the vias 28 to electrically couple the devices to the internal circuitry of the package 20 .
  • the package 20 typically contains an integrated circuit 52 that is mounted to the package and located within a cavity 54 of the printed circuit board 26 .
  • the integrated circuit 52 may be mounted directly to the heat slug 22 to improve the thermal performance of the package.
  • the integrated circuit 52 is coupled to the printed circuit board 26 by a plurality of bond wires 56 .
  • the cavity 54 and integrated circuit 52 are enclosed by an encapsulant 58 .
  • the integrated circuit 52 is preferably a microprocessor, although it is to be understood that the package 20 may contain any electrical device.
  • the package 20 is typically assembled by initially mounting the heat slug 22 and electrical devices 34 to the printed circuit board 26 with a solder reflow process.
  • the integrated circuit 52 is then mounted to the heat slug 22 and wire bonded to the printed circuit board 26 .
  • the cavity 54 is then filled with an encapsulant 58 to enclose the integrated circuit 52 .

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Chemical & Material Sciences (AREA)
  • Dispersion Chemistry (AREA)
  • Materials Engineering (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

An electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package.

Description

    BACKGROUND OF THE INVENTION
  • 1. FIELD OF THE INVENTION [0001]
  • The present invention relates to a package for an integrated circuit. [0002]
  • 2. DESCRIPTION OF RELATED ART [0003]
  • Integrated circuits are typically housed within a package that is soldered to a printed circuit board. Some packages contain a heat slug to facilitate the removal of heat generated by the integrated circuit. The package may also contain a number of discrete capacitors which filter the power and/or signals provided to the integrated circuit.[0004]
  • FIG. 1 shows a top surface of an [0005] integrated circuit package 2 of the prior art. The package 2 has a rectangular heat slug 4 that is surrounded by a number of through hole vias 6. The vias 6 provide interconnect to a plurality of lands located on the opposite bottom surface of the package. The lands are typically soldered to an external printed circuit board. The number of lands for the package are typically limited by the number of vias 6 that can be formed in the package 2.
  • Mounted to the top surface of the package are a number of [0006] capacitors 8. The capacitors 8 are mounted to surface pads 10 located on the top surface. The capacitors 8 and accompanying pads are relatively large and occupy valuable space on the top of the package. Some of the vias 6 must be eliminated to provide room for the capacitors. Eliminating vias reduces the number of lands and the pin throughput of the package. Adding more capacitors to the package would necessitate the elimination of more vias and further reduce the output pins of the package. It would be desirable to provide a package design that can add capacitors without eliminating more vias and corresponding lands.
    • SUMMARY OF THE INVENTION
  • The present invention is an electronic package which has a polygonal shaped heat slug. The heat slug extends from a top surface of a package which has a plurality of vias. The package also has a number of capacitors that are mounted to the top surface. Some of the capacitors are located between the heat slug and the vias. The polygonal shape of the heat slug provides additional space on the top surface so that capacitors can be added without eliminating vias from the package. [0007]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • The objects and advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein: [0008]
  • FIG. 1 is a top view of an electronic package of the prior art; [0009]
  • FIG. 2 is a top view of an electronic package of the present invention; [0010]
  • FIG. 3 is a bottom view of the package shown in FIG. 2; [0011]
  • FIG. 4 is a cross-sectional view of the package shown in FIG. 2. [0012]
    • DETAILED DESCRIPTION OF THE INVENTION
  • Referring to the drawings more particularly by reference numbers, FIGS. [0013] 2-4 show an electronic package 20 of the present invention. As shown in FIG. 2, the package 20 has a heat slug 22 extending from the top surface 24 of a substrate 26. The heat slug 22 has a polygonal shape to reduce the overall area of the slug 22. In the preferred embodiment the heat slug 22 has an octagonal shape. Although an octagonal shape is shown and described, it is to be understood that the heat slug 22 may have any shape that has at least five sides. The heat slug 22 is preferably constructed from a thermally conductive material such as a nickel plated copper.
  • The [0014] substrate 26 is preferably a printed circuit board which has a two-dimensional array of vias 28. The vias 28 on the top surface of the package 20 typically extend to via pads 30 located on the bottom surface 31 of the package shown in FIG. 3. The via pads 30 are connected to corresponding land pads 32. The land pads 32 are typically soldered to an external printed circuit board (not shown). Although land pads 32 in a land grid array (LGA) package are shown and described, it is to be understood that the package may contain pins within a pin grid array package (PGA), or solder bumps within a ball grid array (BGA) package. Additionally, although a printed circuit board is shown and described, it is to be understood that the substrate 26 may be constructed from other materials such as co-fired ceramic.
  • Referring to FIG. 2, the [0015] package 20 has a plurality of discrete electronic devices 34 mounted to the top surface of the substrate 26. In the preferred embodiment, the discrete devices 34 are capacitors. The capacitors 34 typically filter power and/or signals provided to the package. Although capacitors are shown and described, it is to be understood that the discrete devices 34 may be any active or passive component such as a resistor.
  • The [0016] devices 34 are preferably soldered to a pair of surface pads 36 located on the top surface of the printed circuit board 26. Four of the devices 34 can be mounted in an area adjacent to a pair of opposing sides 38 and 40 of the heat slug 22. In the embodiment disclosed, the side mounted devices 34 will each eliminate three vias 28 from the package to provide room for the surface pads 36.
  • The [0017] package 20 also has four additional devices that are mounted between the corner sides 42-48 of the heat slug 22 and the vias 28. The polygonal shape provides enough clearance between the heat slug 22 and the vias 28 to allow the devices 34 to be mounted to the printed circuit board 26 without eliminating vias from the package 20. The polygonal shaped heat slug 22 thus provides a package that will support additional capacitors without eliminating vias 28 and corresponding land pads 32.
  • In the preferred embodiment, the [0018] heat slug 22 is mounted to a surface pad 50 of the circuit board 26 which is dedicated to electrical ground (Vss). One surface pad 36 of each device 34 may be routed to the ground pad 50. The other pad 36 may be connected to one of the vias 28 to electrically couple the devices to the internal circuitry of the package 20.
  • As shown in FIG. 3, the [0019] package 20 typically contains an integrated circuit 52 that is mounted to the package and located within a cavity 54 of the printed circuit board 26. The integrated circuit 52 may be mounted directly to the heat slug 22 to improve the thermal performance of the package. The integrated circuit 52 is coupled to the printed circuit board 26 by a plurality of bond wires 56. The cavity 54 and integrated circuit 52 are enclosed by an encapsulant 58. The integrated circuit 52 is preferably a microprocessor, although it is to be understood that the package 20 may contain any electrical device.
  • The [0020] package 20 is typically assembled by initially mounting the heat slug 22 and electrical devices 34 to the printed circuit board 26 with a solder reflow process. The integrated circuit 52 is then mounted to the heat slug 22 and wire bonded to the printed circuit board 26. The cavity 54 is then filled with an encapsulant 58 to enclose the integrated circuit 52.
  • While certain exemplary embodiments have been described and shown in the accompanying drawings, it is to be understood that such embodiments are merely illustrative of and not restrictive on the broad invention, and that this invention not be limited to the specific constructions and arrangements shown and described, since various other modifications may occur to those ordinarily skilled in the art. [0021]

Claims (19)

What is claimed is:
1. An electronic package, comprising:
a package which has a top surface and an opposite bottom surface;
a plurality of contacts located on said bottom surface of said package; and,
a polygonal shaped heat slug located in said top surface of said package.
2. The package as recited in claim 1, further comprising an electrical device mounted to said top surface of said package.
3. The package as recited in claim 2, wherein said top surface has a two-dimensional array of vias and said electrical device is located between said heat slug and said vias.
4. The package as recited in claim 3, wherein said top surface has a rectangular shape defined by a pair of intersecting diagonal lines that extend from opposing corners of said top surface, and said electrical device is located on one of the diagonal lines.
5. The package as recited in claim 2, wherein said electrical device is a capacitor.
6. An electronic package, comprising:
a printed circuit board which has a plurality of contacts on a bottom surface and a plurality of vias on an opposite top surface;
a polygonal heat slug that is mounted to said top surface of said printed circuit board; and,
an electrical device that is mounted to said top surface of said printed circuit board and located between said heat slug and said vias.
7. The package as recited in claim 6, wherein said top surface has a rectangular shape defined by a pair of intersecting diagonal lines that extend from opposing corners of said top surface, and said electrical device is located on one of the diagonal lines.
8. The package as recited in claim 6, wherein said electrical device is a capacitor.
9. The package as recited in claim 6, wherein said heat slug is mounted to a ground pad of said printed circuit board.
10. The package as recited in claim 9, wherein said electrical device is connected to said ground pad and a via.
11. An electronic package, comprising:
a printed circuit board which has a plurality of contacts on a bottom surface and a plurality of vias on an opposite top surface;
an integrated circuit coupled to said printed circuit board;
a polygonal heat slug that is mounted to said top surface of said printed circuit board; and,
an electrical device that is mounted to said top surface of said printed circuit board and located between said heat slug and said vias.
12. The package as recited in claim 11, wherein said top surface has a rectangular shape defined by a pair of intersecting diagonal lines that extend from opposing corners of said top surface, and said electrical device is located on one of the diagonal lines.
13. The package as recited in claim 12, wherein said electrical device is a capacitor.
14. The package as recited in claim 13, wherein said heat slug is mounted to a ground pad of said printed circuit board.
15. The package as recited in claim 14, wherein said electrical device is connected to said ground pad and a via.
16. A method for assembling an electronic package, comprising the steps of:
a) providing a printed circuit board which has a plurality of contacts on a bottom surface and a plurality of vias on an opposite top surface;
b) mounting a heat slug to said top surface of said printed circuit board;
c) mounting an electrical device to said top surface of said printed circuit board at a location between said heat slug and said vias.
17. The method as recited in claim 16, further comprising the step of mounting an integrated circuit to said printed circuit board.
18. The method as recited in claim 17, further comprising the step of enclosing said integrated circuit with an encapsulant.
19. A heat slug for an electronic package, comprising:
a heat slug which has a top surface, a bottom surface and at least five sides.
US09/842,305 1996-03-29 2001-04-25 Method and apparatus for polygonal heat slug Expired - Lifetime US6459563B1 (en)

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US09/842,305 US6459563B1 (en) 1996-03-29 2001-04-25 Method and apparatus for polygonal heat slug

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US08/626,174 US6256189B1 (en) 1996-03-29 1996-03-29 Heat slug design which facilitates mounting of discrete components on a package without losing lands or pins in the package
US09/842,305 US6459563B1 (en) 1996-03-29 2001-04-25 Method and apparatus for polygonal heat slug

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US11929317B2 (en) * 2020-12-07 2024-03-12 Macom Technology Solutions Holdings, Inc. Capacitor networks for harmonic control in power devices

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