US20020014691A1

US20020014691A1 - Multiple line grid array package

Info

Publication number: US20020014691A1
Application number: US09/203,196
Authority: US
Inventors: Chong Kwang Yoon; Chan Keun Kim
Original assignee: Glotech Inc
Current assignee: Glotech Inc
Priority date: 1997-04-26
Filing date: 1998-11-30
Publication date: 2002-02-07
Anticipated expiration: 2018-04-24
Also published as: US6384477B2

Abstract

A multiple line grid array package comprising a package body having a first surface and a second surface opposite to the first surface; a first pattern formed on the first surface of the package body and including a number of input/output nodes; a second pattern formed on the second surface of the package body; and a lead frame having a nonconductive grid body and a number of conductors formed parallel to a longitudinal axis of the nonconductive grid body on the outer peripheral portion and/or within the inner portion of the lead frame and bonded to the package body; wherein each of conductors is electrically isolated from each other and matches the corresponding one of the number of input/output nodes of the first pattern.

Description

This application is a continuation-in-part of co-pending U.S. patent application Ser. No. 09/065,882, filed on Apr. 24, 1998, entitled MUTIPLE LINE GRID ARRAY PACKAGE AND METHOD OF MANUFACTURING THE SAME and from which priority is claimed under 35USC § 120.[0001]

BACKGROUND OF THE INVENTION

1. Field of the invention

The present invention relates to a multiple line grid array package (MLGA package), and more particularly, to the multiple line grid array package having a package body with electrical circuit patterns according, specific design rues, on which a semiconductor chip is equipped and input/output nodes for supplying electrical signals to the semiconductor chip are exposed, and lead frames which electrically connect the input/output nodes with a power source.

2. Related Art

Generally, a ceramic pin grid array package (PGA) includes a multilayer ceramic structure which is formed by a desired process, and cylindrical metallic lead frames which are attached on the multilayer ceramic structure.

FIG. 1A to 1C are shown an example of a conventional ceramic package which has the structure as described the above.

As shown in FIG. 1A, there is provided a multilayer ceramic structure (package body 1) which is comprised of, for example, four

ceramic layers

1 a, 1 b, 1 c, 1 d. Here, a first ceramic layer 1 a located at the very bottom of the four ceramic layers is a dummy layer, and at the center portion of a second ceramic layer 1 b is mounted a semiconductor chip 2. First electrode lines 4 a are printed around the semiconductor chip 2 on the upper face of the second ceramic layer 1 b for transferring electrical signals to each part of the semiconductor chip 2.

A third

ceramic layer

1 c is provided with a first cavity (not shown) which has a size capable of accommodating the semiconductor chip 2. Second electrode lines 4 b are printed around the first cavity on the upper face of the third ceramic layer 1 c. A fourth ceramic layer 1 d is also provided with a second cavity which has a size capable of accommodating the semiconductor chip 2.

Around the

second cavity

3 on the upper face of the fourth ceramic layer 1 d, there are a plurality of input/output nodes 6 aligned apart from each other at regular intervals.

In addition, a plurality of via holes (not shown) for electrically connecting the respective input/

output nodes

6 with the corresponding first and

second electrode lines

4 a, 4 b are formed in the second, third and fourth

ceramic layers

1 b, 1 c, 1 d. The via holes are filled with conductive paste. In FIG. 1A, there are shown upper portions 5 of the via holes filled with the conductive paste. Therefore, when the electrical signals are transferred to the input/output nodes 6, the electrical signals are continuously transferred through the first and

second electrode lines

4 a, 4 b to terminals in the semiconductor chip 2.

Lead frames

7 for transferring the electrical signals are bonded to the package body 1. The lead frames 7 are typically made of a metal, and are formed into cylindrical pins. Furthermore, each of the lead frames 7 is connected with each of the corresponding input/output nodes 6.

FIG. 1B is a partially enlarged view of the

package body

1 in FIG. 1A. The lead frames 7 in the shape of pins are bonded to the corresponding input/output nodes 6 by brazing 7 a.

FIG. 1C is a cross-sectional view along the line C-C′ of FIG. 1B. The plurality of via holes are formed in the

package body

1, and the via holes are filled with the conductive paste T. The respective

ceramic layers

1 a, 1 b, 1 c, 1 d composing the package body 1 are provided with the first and

second electrode lines

4 a, 4 b which are printed on the upper face of the

ceramic layers

1 a, 1 b, 1 c, 1 d. The

ceramic layers

1 a, 1 b, 1 c, 1 d are laminated each other by a pressure, followed by fired at high temperatures.

However, in the conventional pin grid array package as mentioned above, there are some problems as follows:

First, since the

lead frames

7 of pin shapes are respectively connected with the corresponding input/output nodes 6 on the upper face of the ceramic package body 1, it is required that the number of the lead frames 7 should be formed as many as that of the input/output nodes 6. Therefore, the higher the semiconductor chip is integrated, the more the number of the input/output nodes 6 is increased.

Such increase in the number of the semiconductor chip caused the manufacturing cost of the ceramic package to increase, and the size of the package is also increased.

SUMMARY OF THE INVENTION

It is therefore an object of the present invention to a multiple line grid array package which can be decreased the manufacturing cost and the size thereof.

One of the above objects which will be apparent to one skilled in the art upon a reading of this disclosure are attained by:

A multiple line grid array package comprising a package body on which a semiconductor chip is mounted and input/output nodes for supplying a electrical signal for the semiconductor chip are exposed, a lead frame for electrically connecting the input/output nodes of the package body with a power source is characterized in that a number of conductors are formed parallel to an axis on the outer side or interior of the lead frame, and that a conductor is respectively formed on each outer side or interior, the conductors are bonded to the respective unit input/output nodes corresponding to each other.

The package body has electrical circuit patterns and includes a nonconductive substrate such as a polymer, a ceramic, or a polymer-ceramic composite, a number of wire bond pads, input/output nodes and electrode lines. If necessary, the package body further includes via hole pads. A number of electrode lines may be located between the lead frame and the adjacent lead frame on the upper surface of the package body. Alternatively, no electrode line may be located between the two adjacent lead frames. The via hole pads may also be located in the inside and/or outside of he areas where the lead frames are to be attached. The input/output node has various shapes and various sizes depending on the shape and size of the lead frame.

The lead frame made of a conductive material and a nonconductive material may be formed into one of a rectangular disc, a circular disc, a cylindrical shape, an elliptical cylinder and a hexahedron, etc., and the height of the lead frame is formed to be longer or shorter than its width.

According to the present invention, one lead frame can be connected with a number of the input/output nodes, whereby the number of lead frames can be reduced considerably.

In addition, according to the pattern of the present invention, a number of the input/output nodes are arranged within small area and the signal delivery delay is prevented due to the reduction of the length of the electrode lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The above object, and other features and advantages of the present invention will be more apparent after a reading of the following detailed description taken in conjunction with the drawings, in which: [0024]
FIGS. 1A to [0025] 1C are one example of prior art of a pin grid array package; FIG. 1A is an exploded perspective view of a conventional pin grid array package; FIG. 1B is a partial perspective view of FIG. 1A; and FIG. 1C is a cross-sectional view taken along a line C-C′ of FIG. 1B;
FIG. 2 is a schematic perspective view of one type of multiple line grid array packages applicable according to the present invention; [0026]
FIGS. 3A and 3B are partially enlarged perspective views of lead frame of the multiple line grid array package of FIG. 2; [0027]
FIGS. 3C to [0028] 3E are other embodiments of lead frames which is to be applicable to the multiple line grid array package of FIG. 2.
FIG. 4 is a cross-sectional view taken along a line IV-IV′ of FIG. 2; [0029]
FIGS. 5A and 5B are plan views showing examples of electrical circuit patterns printed on bottom and top surfaces of the package body, respectively. [0030]
FIGS. 6A to [0031] 6C are schematic perspective views showing one of methods of manufacturing the lead frame according to this invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring now to FIGS. [0032] 2 to 6, there are illustrated embodiments of the present invention.
As shown in FIGS. [0033] 2 to 6 c, a reference numeral 9 designates a nonconductive body of various types of lead frames, and 10 a is a conductor on the outer surface or interior of the body 9, and 11 is a lead frame comprising the nonconductive body 9 and the conductor 10 a. In addition, reference numerals 20 a, 20 b, 20 c, 20 d designate the package layers which include metallic electrode lines and electrical contacts on ceramic layers or plastic layers. 20 is a package body which includes the package layers 20 a, 20 b, 20 c, 20 d stacked and electrically connected to each other, and 21 is a cavity if needed in which a semiconductor chip is to be located, and 22 is an input/output node which is arranged on the upper face of the package body 20, and 23 is a solder provided on each of the input/output node 22.
In the present invention, a semiconductor package in which a plurality of input/output nodes is connected with one lead frame of multiple conductors in order to decrease the number of lead frames and the size of the package is called “multiple line grid array package”. [0034]
Referring to FIG. 2, the multiple line grid array package is described in the below. [0035]
The [0036] body 20 of the multiple line grid array package has a structure of stacking up and down a number of, for example, four package layers 20 a, 20 b, 20 c, 20 d. The input/output nodes 22 are exposed on the surface of the most upper package layer 20 d, and are electrically connected with lower corresponding first and second electrode lines(not shown) in via contact manner. The package body 20 includes metallic electrode lines and electrical contacts on ceramic and/or plastic materials.
At the center of the [0037] package body 20, there is, if necessary, provided a cavity 21 in which a semiconductor chip is to be located. However, the semiconductor chip may be located in other types different from FIG. 2. The lead frames 11 of the present embodiment are attached to input/output nodes 22, and receive the electrical signals from an external power source (not shown). Each of the lead frames 11 is attached to a number of input/output nodes 22 by soldering process which is cheaper than brazing process. That is, for example, the lead frame 11 in the present embodiment connects a number of, for example, eight input/output nodes 22.
Referring to FIGS. 3A to [0038] 3E, the structure of the multiple line grid array package of the present embodiment is described more clearly in the below.
As shown in FIG. 3A, one of the lead frames [0039] 11 used in the multiple line grid array package of present invention is a rectangular type.
The [0040] lead frame 11 includes a plurality of conductors 10 a, a plurality of grooves H and a grid body 9. On each of the outer sides of the lead frame 11, a plurality of grooves H are formed parallel to the longitudinal direction of the lead frame 11. The conductor 10 a is provided on the outer sides between the adjacent grooves H to facilely transfer the electrical signal. Preferably, the inner portion of the lead frame 11, that is, a grid body 9 is formed of nonconductive materials such as ceramic, polymer, a composite of ceramics and polymers, and silicon. Furthermore, in this embodiment, four grooves are formed on the outer sides of the lead frame 11 at regular intervals.
In addition, the [0041] lead frame 11 can be various forms according to an aspect ratio which is the ratio of a width n_x, n_yto a height n_zof the lead frame 11. Therefore, in the multiple line grid array package of the present invention, the lead frame 11 may be formed into a rectangular disc type of which the width n_x, n_yis relatively longer than the height n_zas shown in FIG. 3A. Alternatively, the lead frame 11 may be formed into a rod type in which the width n_x, n_yis relatively shorter than the height n_zas shown in FIG. 3B.
Furthermore, the [0042] lead frame 11 may be formed into other types instead of the rectangular disc or rod type described above. FIGS. 3C to 3E are enlarged perspective views which show other embodiments of the lead frame 11 which are applicable to the multiple line grid array packages according to this invention. Lead frames comprising a nonconductive grid body 9 and conductors 10 a of disc type are shown in FIGS. 3C to 3E. In FIG. 3C, a number of conductors 10 a of semi-circular cylinder shape are formed parallel to the longitudinal direction of the lead frame 11 at a peripheral portion of the nonconductive grid body 9. The number of conductors are electrically isolated with each other. In FIG. 3D, a number of conductors 10 a of circular cylinder shape are formed within the nonconductive grid body 9 with the number of conductors 10 a being electrically isolated with each other. In FIG. 3E, a lead frame 11 is shown where a number of conductors 10 a of a circular cylinder shape are formed within a nonconductive grid body 9 of a circular disc shape. The number of conductors 10 a are also electrically isolated with each other.
The [0043] conductors 10 a shown in FIGS. 3C to 3E are formed such that both top and bottom faces thereof are protruded a little more than both top and bottom surfaces of the grid body 9. As a result, the lead frame 11 is attached to the package body 20 such that each of the protruded portions matches the corresponding unit input/output node 22 (refer to FIG. 4). It is, of course, contemplated that the nonconductive grid body and the conductor may be modified to other various shapes. Some examples of the grid body and the conductor shown in FIGS. 3A to 3E are not limited, but illustrative.
According to the present invention, each of the [0044] conductors 10 a coated with the conductive material or located within the interior of the lead frame body shown in FIGS. 3A to 3E serves as a unit lead frame in a conventional sense. Therefore, one lead frame 11 includes a number of leads according to the number of the conductors 10 a and can be thus connected with a number of input/output nodes.
For example, the [0045] lead frame 11 of the rectangular disc type has eight conductors 10 a as shown in FIG. 3A. Eight input/output nodes are connected with one lead frame 11, whereby the number of the lead frames which are used in the conventional BGA, PGA and QFP packages can be reduced to one-eighth and the surface area thereof can be also reduced to below one-fourth. In addition, in FIGS. 3B to 3E, the same concept is applied.
FIG. 4 is a cross-sectional view taken along the line IV-IV′ of FIG. 2, which is illustrated the cross-sectional view of multiple line grid array package. As shown in FIG. 4, a [0046] package body 20 includes four layers 20 a, 20 b, 20 c, and 20 d, each of which comprises a nonconductive substrate, and metallic electrode lines 20-1, 20-2, and the via holes. The top layer 20 d further includes input/output nodes 22 on the surface thereof. On the bottom surface of the lowest layer 20 a there is provided bottom pattern (refer to FIG. 5A). On the top surface of the most top layer 20 d there is also provided a top pattern(refer to FIG. 5B). The top pattern includes a plurality of input/output nodes 22 which are electrically connected to the corresponding conductors of the lead frame 11.
Each of the package layers is heat-adhered each other by a pressure and the via holes are filled with conductive paste T. On the upper face of each of the package layers [0047] 20 a, 20 b, 20 c, 20 d, there are printed a number of electrodes 20-1, 20-2. And the input/output nodes 22 are exposed to the upper face of the package body 20.
According to the present invention, one [0048] lead frame 11 is connected with the same number of the input/output nodes 22 as that of the conductors 10 a which are formed on the outer sides or interior of the lead frame 11. That is, for example, in this embodiment FIG. 3A, since four grooves H are formed on the outer sides of one lead frame 11 in the form of rectangular disc, the lead frame 11 can be connected with eight input/output nodes 22. At this time, the input/output nodes 22 are bonded to the conductor 10 a coated on the outer sides of the lead frame 11 by solder 23, as shown in FIG. 4. Although two nodes 22 are shown in FIG. 4, the lead frame 11 is connected to the same number of the input/output nodes 22 as those of the conductors 10 a which are formed on the outer sides of the lead frame 11, as described above. The lead frame according to the present invention may be applied to array type packages, chip scale packages, flip chip packages, wafer level packages, and connectors.
FIGS. 5A and 5B are plan views showing electrical circuit patterns printed on bottom and top surfaces of the package body, respectively. The electrical circuit patterns on the [0049] package body 20 can be of various forms depending on the types of lead frame 11 and IC chips used. One example of such patterns are described in the following.
The most bottom layer of the [0050] package body 20 has a nonconductive substrate and a pattern on the surface of the substrate as shown in FIG. 5A. The pattern includes a number of wire bond pads 24, via hole pads 25, and electrode lines 26. The number of wire bond pads 24 are formed such that the package body 20 is connected to the semiconductor chip by a wire bonding or other connecting methods such as redistribution for wafer level packaging method and C4 (Controlled Collapsed Chip Connection) method. The number of via hole pads 25 serve as providing the electrical connection between the package layers and the electrode lines 26 function as providing the electrical connection between the input/output nodes 22, the wire bond pads 24 and the via hole pads 25. The wire bond pads may be located on any area of the package body 20.
The pattern shown in FIG. 5B will be described hereinafter. The pattern shown in FIG. 5B is not limited but illustrative. The electrical circuit pattern is designed by the following design rules. [0051]
For example, in the case that the lead frame includes eight conductors, input/[0052] output nodes 22 are, as shown in FIG. 5B, formed in such manner that each of the input/output nodes 22 corresponds to each of the conductors 10 a of the lead frame 11. The conductors 10 a and input/output nodes 22 are connected by soldering.
As shown in FIG. 5B, the configuration of the input/[0053] output nodes 22 forms rectangular shape. Besides, the configuration of the input/output nodes may form various shapes such as triangular shape, etc. and may have various sizes depending on the shape and the size of the lead frame 11. Some of the via hole pads 25 the electrode lines 26 are positioned outside an area A where the lead frame 11 and the other of the via hole pads and electrode lines 26 are positioned within an area A where the lead frame is located. Alternatively, all via hole pads and electrode lines are positioned may be positioned within an area A where the lead frame is located.
For example, when the design rules of the FIG. 5A and FIG. 5B are such that at most two electrode lines are placed between the two adjacent lead frames [0054] 11, the input/output node pitch is about 500 micrometers, the via hole diameter is about 200 micrometers, line width and spacing is about 75 micrometers and each of the input/output nodes 22 of rectangular shape has a dimension of about 200 micrometer×200 micrometer, then 200 input/output nodes 22 can be placed in the package body with two package layers and the dimensions of the package body is about 9.8 millimeters×9.8 millimeters. This kind of the design rules results in the lower manufacturing cost than any other package design, while giving the smaller package substrate area and footprint area on PCB. When the multiple line grid array package is surface-mounted on the printed circuit board and the input/output nodes 22 are connected to the input/output nodes 22 on the printed circuit board, the design rules for circuit patterns on the printed circuit board will be the same as the design rules aforementioned.
The patterns described in the present invention may be applied to other types of plastic and ceramic packages such as QFP, BGA, CSP (Chip Scale Packages) and wafer level packages. The patterns described in this invention may be also applied to PCB (Printed Circuit Board) and ceramic substrate for hybrid ICs. [0055]
Besides, the pattern design described in the present invention can also be applied to conventional PCB pattern design. [0056]
According to the pattern in the present invention, a number of input/output nodes are arranged within small area and the signal delivery delay is prevented due to the reduction of the length of the electrode lines. [0057]
Referring to FIGS. 6A to [0058] 6C, the method for manufacturing the one type of lead frame used in the multiple line grid array package in accordance with one embodiment of the present invention is to ba explained hereinafter.
First, for example, a [0059] lead frame body 9 of circular disc is formed of a nonconductive material such as ceramic and plastic as shown in FIG. 6A. In addition, the circular disc 9 can be formed into a cylindrical shape in which its height m_zis longer than its diameter (m_x, m_y)
Secondly, the [0060] conductor 10 a is coated on the outer side around the circular disc 9, as shown in FIG. 6B. The conductor 10 a can be formed on the outer side of the circular disc 9 in a manner of, for example, the electroless plating, conductive paste coating, or conductive paste filling.
Finally, as shown in FIG. 6C, a number of grooves H and a number of [0061] conductors 10 a parallel to the longitudinal direction m_zare formed on the outer side of the circular disc 9 by a cutting process such as diamond saw cutting, laser cutting, ultrasonic cutting or punching, thereby being formed the lead frame 11 connected to a number of the input/output nodes 22. In this embodiment, the order of the steps of forming the conductor 10 and forming the grooves H parallel to the axial direction m_zon the outer side of the circular disc 9 can be reversed.
Therefore, since a number of the grooves H parallel to the axial direction m[0062] _zare formed on the outer side of the lead frame 11, the conductor 10 a coated on the outer side of the lead frame 11 are separated independently from each other by the inner portion of the nonconductive circular disc 9. Each of such insulated conductors 10 a is a unit lead to be connected to a single node. One lead frame 11 is connected with a number of nodes.
Furthermore, in the method of forming the lead frame according to the present invention, the [0063] lead frame 11 may be formed of a ceramic, a polymer, a silicon, or a compound of ceramic and plastic material.
According to the present invention, although the lead frame used in the multiple line grid array package is described in the form of the rectangular or circular disc in the preferred embodiments, the lead frame can also have various shapes such as a cylinder, an elliptical disc, a hexahedron disc and cylindrical types of aforementioned shapes. [0064]
Moreover, the package body can be formed of a plastic and/or ceramic structures. [0065]
As described above in detail, according to the present invention, one lead frame can be connected with a number of the input/output nodes, whereby the number of lead frames can be reduced considerably. [0066]
Accordingly, the present invention has the advantage of reducing the manufacturing cost as well as the size of package. [0067]
Furthermore, in order to connect the input/output nodes with the lead frame of the invention, the soldering process is applied instead of the brazing process, thereby further reducing the manufacturing cost. [0068]
The single lead frame of the invention can be connected with a number of the input/output nodes, whereby it can be facilely applied to the highly integrated semiconductor packages. [0069]
Having described the preferred embodiments of the present invention, it will appear to those ordinary skilled in the art that various modifications may be made to the disclosed embodiments, and that such modifications are intended to be within the scope of the present invention. [0070]

Claims

What is claimed is:

1. A multiple line grid array package comprising:

a package body having a first surface and a second surface opposite to the first surface;

a first pattern formed on the first surface of the package body and including a number of input/output nodes;

a second pattern formed on the second surface of the package body;

a lead frame having a nonconductive grid body and a number of conductors formed parallel to a longitudinal direction of the nonconductive grid body on the outer peripheral portion and/or within the inner portion of the lead frame and bonded to the package body; wherein each of conductors is electrically isolated from each other and matches the corresponding one of the number of input/output nodes of the first pattern.

2. The package according to claim 1, wherein the package body includes at least one layer.

3. The package according to claim 2, wherein the layer comprises a ceramic layer, a polymeric layer, or a composite layer of ceramics and polymers.

4. The package according to claim 1, wherein the nonconductive grid body of the lead frame is selected from the group consisting of a ceramic, a polymer, a composite material of ceramics and polymers, and silicon.

5. The package according to claim 1, wherein the lead frame is formed into one of a rectangular disc, a circular disc, a cylinder, an elliptical disc, a hexahedron disc and a cylinder.

6. The package to claim 5, wherein the height of the lead frame is the same as its width or longer than its width.

7. The package to claim 4, wherein the height of the lead frame is shorter than its width.

8. The package to claim 1, wherein the package body comprises at least two layers selected from the group consisting of a ceramic layer, a polymer layer, a composite layer of ceramics and polymers.

9. The package according to claim 1, wherein the first pattern formed the first surface of the package comprises a number of electrode lines, wire bond pads, and via hole pads and input/output modes.

10. The package according to claim 1, wherein each of the conductors is bonded to the corresponding input/output node by soldering.

11. The package according to claim 9, wherein, the input/output nodes form various configurations in the first pattern depending on the position of the corresponding conductors of the lead frame, some of the number of electrode lines are positioned in the first pattern within an area where the lead frame is located and the other of the number of electrode lines are positioned in the first pattern outside the area where the lead frame is located, some of the number of via hole pads are positioned in the first pattern within the area where the lead frame is located, and the other of the number of via hole pads are positioned in the first pattern outside the area where the lead frame is located.

12. The package according to claim 9, wherein the input/output nodes form various configurations in the first pattern depending on the position of the corresponding conductors of the lead frame, all the electrode lines and via hole pads are positioned in the first pattern within an area where the lead frame is located.

13. The pattern described in claim 11, wherein the pattern is applicable to QFP, BGA, CSP, flip chip packages and wafer level packages, printed circuit board and ceramic substrate for hybrid ICs.

14. The pattern described in claim 12, wherein the pattern is applicable to QFP, BGA, CSP, flip chip packages and wafer level packages, printed circuit board and ceramic substrate for hybrid ICs.

15. The lead frame described in claim 1, wherein the lead frame is applicable to array type packages, chip scale packages, flip chip packages, wafer level packages, and connectors.