US20010035538A1

US20010035538A1 - Charge coupled device having charge accumulating layer free from tow-dimensional effect under miniaturization and process for fabrication thereof

Info

Publication number: US20010035538A1
Application number: US09/451,770
Authority: US
Inventors: Yukiya Kawakami; Shigeru Tohyama
Original assignee: Individual
Current assignee: NEC Corp
Priority date: 1998-12-07
Filing date: 1999-12-01
Publication date: 2001-11-01
Anticipated expiration: 2019-12-01
Also published as: NL1013774C2; US6369414B2; JP2000174258A; JP3276005B2; NL1013774A1

Abstract

A charge coupled device has an n- type charge accumulating layer equal to or less than 5 micron in width, and the unit cells suffer from reduction of signal charge accumulated therein and an increased pulse height of a pulse signal for a substrate shutter, wherein at least one p- type local impurity region is formed in such a manner as to form a p-n junction together with the n- type charge accumulating layer and the n- type semiconductor substrate, thereby increasing the amount of signal charge accumulated in each unit cell without sacrifice of the pulse height of the pulse signal for the substrate shutter.

Description

FIELD OF THE INVENTION

This invention relates to a charge coupled device and, more particularly, to a charge coupled device having a miniature charge accumulating layer and a process for fabricating the charge coupled device.

DESCRIPTION OF THE RELATED ART

The charge coupled device has found a wide variety of application such as, for example, an image sensor. The charge coupled device used in the image sensor is categorized in a frame- transfer type, and has the structure shown in FIGS. 1A and 1B. The prior art frame- transfer type charge coupled device is fabricated on an n-

type semiconductor substrate

1, and a p-type well 11 is formed in a surface portion of the n-type semiconductor substrate 1. P-type isolating regions 2 are spaced from each other in the p-type well 11, and n-type charge accumulating layer 3 is formed between the p-type isolating regions 2. The isolating regions 2 and the n-type charge accumulating layer 3 are covered with an insulating layer 4, and transfer electrodes 5 are patterned on the insulating layer 4 along the charge accumulating layer 3.

A driving pulse signal is selectively applied to the

transfer electrodes

5. Then, potential wells are sequentially created in the charge accumulating layer 3 under the transfer electrodes 5,and charge packets are conveyed from the potential wells to the next potential wells. Signal charge forms each charge packet, and is representative of a piece of visual image. A part of the charge accumulating layer for creating a potential well and associated transfer electrode or electrodes 5 are hereinbelow referred to as “unit cell” which is a pixel of the frame- transfer type charge coupled device image sensor, also.

Though not shown in FIGS. 1A and 1B, a certain voltage is applied to the n-

type substrate

1, and excess signal charge is discharged through the p-type well 11 to the n- type substrate 1. Thus, the adjacent potential wells are prevented from the excess charge. While the charge packets are being conveyed along the charge accumulating layer 3, the p-n junction between the n-type semiconductor substrate 1 and the p- type well 11 is reversely biased, and the p- type well 11 is electrically isolated from the n- type semiconductor substrate 1. When a pulse signal is applied to the n- type semiconductor substrate 1, the p- n junction is much stronger biased in reverse than ever, and the signal charge is discharged to the n- type semiconductor substrate 1. This phenomenon is called as a substrate shutter or an electronic shutter, and the exposure is controlled with the substrate shutter.

Users request the manufacturer to reduce the price of the image sensor. In order to reduce the production cost, the manufacturer scales down the image sensor and, accordingly, the charge coupled device. Another request for the manufacturer is a fine visual image on a screen, and the manufacturer increases the photo- electric converting elements per unit area. This means that the unit cell is miniaturized as well as the photo- electric converting element. Thus, the common concept for both approaches is miniaturization.

Research and development efforts have been made for a miniature unit cell, and it is found that the p- type well is not required for the unit cell. This means that the

charge accumulating layer

3, the isolating regions 2 the insulating layer 4 and the transfer electrodes 5 form in combination a charge coupled device as shown in FIGS. 2A and 2B (see “Design Options for ¼″ FT-CCD Pixels”, J. T. Bosiers et. al., Proceedings of 1995 IEEE Workshop on Charge- Coupled Devices and Advanced Image Sensors, April, 1995). The prior art charge coupled device without the p- type well is simpler than the standard charge coupled device, and the production cost is reduced. However, the manufacturer encounters the following problems in the miniaturized charge coupled device. First, the isolating regions 2 increase influences on the charge accumulating layer 3, and the designer can not analyze the miniature unit cell as a one-dimensional model in the direction of the depth of the charge accumulating layer 3. Two- dimensional analysis is required for the miniature unit cell. The phenomenon which the designer experiences in the design work for the miniature unit cell is hereinbelow referred to as “two-dimensional effect”.

In this situation, when the manufacturer designs the

charge accumulating layer

3, the amount of actually accumulated signal charge is less than the amount of accumulated signal charge predicted on the basis of the ratio of areas. On the other hand, when the manufacturer designs the substrate shutter, the substrate shutter requires the pulse signal with a higher pulse height for discharging the signal charge to the substrate, because the pulse signal is expected to deplete the isolating regions 2 increased at the ratio of areas as well as the charge accumulating layer 3. If the dopant concentration of the charge accumulating layer 3 is increased, the amount of accumulated signal charge is increased. However, the substrate shutter requires a higher pulse height due to the charge accumulating layer 3 increased in the dopant concentration. The pulse height may exceed the maximum voltage level for portable electronic goods. Moreover, the higher pulse height is causative of increase of the electric power consumption. Thus, there is a trade- off between the increase of the amount of accumulated signal charge and the decrease of the pulse height of the pulse signal.

SUMMARY OF THE INVENTION

It is therefore an important object of the present invention to provide a charge coupled device, which has a unit cell increased in the amount of signal charge without sacrifice of the pulse height of a pulse signal used for a substrate shutter.

It is also an important object of the present invention to provide a process for fabricating the charge coupled device.

The present inventors contemplated the problems inherent in the prior art charge coupled device, and found that the dopant impurity concentration was different between a central region of a charge accumulating layer and a peripheral region thereof due to the diffusion of the dopant impurity. The peripheral region was relatively low in the dopant impurity concentration, and was liable to be depleted around the p-n junctions between the charge accumulating layer and the isolating regions. This resulted in that the peripheral region merely accumulated a small amount of signal charge. The two- dimensional effect was derived from the lightly-doped peripheral region.

The present inventors simulated the amount of accumulated charge per unit area for miniature charge accumulating layers, and plotted the amount of accumulated charge per unit area in FIG. 3. The present inventors concluded that the two- dimensional effect became serious in the charge coupled device with the charge accumulating layer equal in width to or less than 5 microns.

Subsequently, the present inventors considered how to restrict the two-dimensional effect. As described hereinbefore, the non- uniform dopant concentration was the origin of the two- dimensional effect. The present inventors made the charge accumulating layer higher in dopant impurity concentration in the peripheral region and lower in the central region. The higher the dopant impurity concentration, the more the amount of accumulated charge. The depletion layer extending from the p-n junction was relatively thin in the heavily- doped peripheral region. An approach to the heavily- doped peripheral region was formed by using a counter doping in the central region, which had been already heavily doped. An impurity region opposite in conductivity type to the central region was formed through the counter doping, and a p-n junction took place between the impurity region and the central region. The p-n junction was conducive to the increase of the amount of accumulated charge.

The reason for the high pulse height was that the electric lines of force were converged for depleting the heavily-doped isolating region as well as the charge accumulating layer. The present inventors considered that a protection for the isolating regions against the electric lines of force was effective against the increase of the pulse height. Otherwise, the electric lines of force had to be converged for depleting the charge accumulating layer before the isolating regions. The present inventors noticed that the p-n junction formed through the counter doping was available for the convergence of the electric lines of force. However, it is important to space the impurity region formed through the counter- doping from the isolating regions. Because the impurity region held in contact with the isolating regions merely prolonged the p-n junctions of the isolating regions. Thus, the impurity region formed through the counter doping was locally formed under the charge accumulating layer.

To accomplish the object, the present invention proposes to form an impurity region opposite in conductivity type to a charge accumulating layer locally under the charge accumulating layer.

In accordance with one aspect of the present invention, there is provided a charge coupled device fabricated on a semiconductor substrate of a first conductivity type isolating regions having a second conductivity type opposite to the first conductivity type and spaced from each other in a surface portion of the semiconductor substrate, a charge accumulating layer of the first conductivity type formed in the surface portion between the isolating regions, an insulating layer formed on the isolating regions and the charge accumulating layer, transfer electrodes formed on the insulating layer along the charge accumulating layer and a local impurity region of the second conductivity type formed in the semiconductor substrate, projecting into a central region of the charge accumulating layer for forming a p-n junction and spaced from the isolating regions.

In accordance with another aspect of the present invention, there is provided a process for fabricating a charge coupled device comprising the steps of a) preparing a semiconductor substrate of a first conductivity type covered with an insulating layer, b) introducing a first dopant impurity into a surface portion of the semiconductor substrate for forming a charge accumulating layer of the first conductivity type, c) introducing a second dopant impurity into surface portions of the semiconductor substrate on both sides of the surface portion for forming isolating regions of a second conductivity type opposite to the first conductivity type, d) introducing a third dopant impurity into a region of the semiconductor substrate for forming a local impurity region of the second conductivity type projecting into a central region of the charge accumulating layer and spaced from the isolating regions and e) forming transfer electrodes over the charge accumulating layer.

BRIEF DESCRIPTION OF THE DRAWINGS

The features and advantages of the charge coupled device and the process will be more clearly understood from the following description taken in conjunction with the accompanying drawings in which: [0017]
FIG. 1A is a cross sectional view showing the prior art frame- transfer type charge coupled device; [0018]
FIG. 1B is a cross sectional view taken along line A-A′ in FIG. 1A and showing the charge accumulating layer located between the isolating regions; [0019]
FIG. 2A is a cross sectional view showing the prior art frame- transfer type charge coupled device fabricated without a p-type well; [0020]
FIG. 2B is a cross sectional view taken along line A-A′ in FIG. 2A and showing the charge accumulating layer located between the isolating regions; [0021]
FIG. 3 is a graph showing a relation between the amount of accumulated charge per unit area and the width of a charge accumulating layer; [0022]
FIG. 4A is a cross sectional view showing the structure of a unit cell incorporated in a charge coupled device according to the present invention; [0023]
FIG. 4B is a cross sectional view taken along A-A′ in FIG. 4A and showing the location of a local impurity region under a charge accumulating layer; [0024]
FIG. 5A is a cross sectional view showing the structure of a unit cell incorporated in another charge coupled device according to the present invention; [0025]
FIG. 5B is a cross sectional view taken along A-A′ in FIG. 5A and showing the locations of two local impurity regions under a charge accumulating layer; [0026]
FIG. 6A to [0027] 6G are cross sectional views showing essential steps of a process for fabricating a charge coupled device according to the present invention;
FIGS. 7A to [0028] 7I are cross sectional views showing essential steps of another process for fabricating a charge coupled device according to the present invention; and
FIGS. 8A to [0029] 8I are cross sectional views showing essential steps of yet another process for fabricating a charge coupled device according to the present invention.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Structure of Charge Coupled Device

First Embodiment

Referring to FIGS. 4A and 4B of the drawings, a charge coupled device embodying the present invention is fabricated on an n- [0030] type semiconductor substrate 1. Heavily- doped p-type isolating regions 2 are formed in surface portions of the n- type semiconductor substrate 1, and are spaced from each other. Between the heavily- doped p-type isolating regions 2 is formed a heavily- doped n- type charge accumulating layer 3 which is equal to or less than 5 microns in width. The n- type charge accumulating layer 3 and the heavily- doped p- type isolating regions 2 are covered with an insulating layer 4, and transfer electrodes 5 are patterned on the isolating layer 4 along the n-type charge accumulating layer 3. A p-type local impurity region 6 projects into a central region of the n- type charge accumulating layer 3 and the n-type semiconductor substrate 1. The p- type local impurity region 6 is narrower than the n- type charge accumulating layer 3, and, accordingly, is spaced from the heavily- doped p- type isolating regions 2. The p- type local impurity region 6 extends along the n-type charge accumulating layer 3, and keeps the width constant in the longitudinal direction thereof. The width of the p- type local impurity region 6 is equal to or less than a half of the distance between the heavily- doped p-type isolating regions 2. The location of the p-type local impurity region 6 is indicated by hatching lines in FIG. 4B for easily discrimination.
In this instance, the p- n junction between the n- [0031] type semiconductor substrate 1 and the p- type well 11 is reversely biased with certain voltage which controls accumulated charge, i.e., there is no accumulated charge in excess bias voltage. Then, a shutter operation as an exposure time limitation is realized by controlling duty ratio between normal bias voltage applying- time and excess bias voltage applying- time in which there is no accumulated charge. The excess bias voltage is achieved by adding a pulse signal voltage with the normal bias voltage, i.e., the pulse signal is applied to the n-type semiconductor substrate 1. The n-type semiconductor substrate 1 is doped at 1×10¹⁴to 1×10¹⁵atoms/ cm³. The central region of the n-type charge accumulating layer 3 is doped at 1×10¹⁵to 1×10¹⁸atoms/cm³, and the peripheral region of the n-type charge accumulating layer 3 is doped at 1×10¹⁵to 1×10¹⁸atoms/cm³. The heavily- doped p-type isolating regions 2 are doped at 1×10¹⁸to 1×10²⁰atoms/cm³, and the p-type local impurity region 6 is doped at 1×10¹⁵to 1×10¹⁷atoms/cm³.
The heavily- doped n- type [0032] charge accumulating layer 3 has peripheral regions heavily- doped with the n- type dopant impurity, and the p- type local impurity region 6 forms a p- n junction together with the heavily- doped n-type charge accumulating layer 3 and the n- type semiconductor substrate 1. The heavily-doped peripheral regions and the p-n junction increase the amount of signal charge accumulated in each unit cell. Moreover, the p-n junction of the p- type local impurity region 6 is depleted with electric lines of force from the n- type semiconductor substrate 1 earlier than the p- n junctions of the heavily- doped p- type isolating regions 2, and a high pulse height is not required for a pulse signal for the substrate shutter.

Second Embodiment

Turning to FIGS. 5A and 5B, another charge coupled device embodying the present invention is fabricated on an n-[0033] type semiconductor substrate 1. Heavily- doped p-type isolating regions 2 are formed in surface portions of the n- type semiconductor substrate 1, and are spaced from each other. Between the heavily- doped p-type isolating regions 2 is formed a heavily- doped n- type charge accumulating layer 3 which is equal to 5 microns in width. The n- type charge accumulating layer 3 and the heavily- doped p- type isolating regions 2 are covered with an insulating layer 4, and transfer electrodes 5 are patterned on the isolating layer 4 along the n- type charge accumulating layer 3. A pair of p-type local impurity regions 6 projects into a central region of the n- type charge accumulating layer 3 and the n- type semiconductor substrate 1. Each of the p- type local impurity regions 6 are narrower than the n- type charge accumulating layer 3, and, accordingly, the p- type local impurity regions are spaced from the heavily- doped p- type isolating regions 2. The p- type local impurity regions 6 extend in parallel along the n-type charge accumulating layer 3, and are constant in width. The location of the p-type local impurity regions 6 is indicated by hatching lines in FIG. 5B for easily discrimination. The charge accumulating layer 3 is as wide as 5 microns, and the two- dimensional effect is not so strong. However, the pair of p-type local impurity regions 6 increases the amount of signal charge accumulated in each unit cell, and restricts the pulse height of the pulse signal for the substrate shutter.

Process of Fabrication

FIGS. 6A to [0034] 6G illustrate a process for fabricating the charge coupled device shown in FIGS. 3A and 3B. The process starts with preparation of the n-type semiconductor substrate 1 such as, for example, an n- type single crystalline silicon substrate. Insulating material such as silicon oxide is grown on the major surface of the n- type semiconductor substrate 1, and forms an insulating layer 4. Photo- resist solution is spread over the entire surface of the insulating layer 4, and is baked so as to cover the insulating layer 4 with a photo- resist layer. A pattern image for the n-type charge accumulating layer 3 is transferred from a photo- mask (not shown) to the photo- resist layer, and forms a latent image in the photo- resist layer. The latent image is developed, and a photo- resist ion- implantation mask 7 is left on the insulating layer 4. Thus, the photo- resist ion- implantation mask 7 is patterned on the insulating layer 4 through a photo- lithography.
Using the photo- resist ion- [0035] implantation mask 7, n- type dopant impurity 9 such as, for example, phosphorous is implanted into the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under acceleration energy of 50 to 200 keV as shown in FIG. 6A.
The n- [0036] type dopant impurity 9 forms the n-type charge accumulating layer 3 in the surface portion of the n- type semiconductor substrate 1. The photo-resist ion- implantation mask 7 is stripped off, and the n- type dopant impurity is activated through an appropriate annealing. Thus, the n-type charge accumulating layer 3 is formed in the surface portion of the n- type semiconductor substrate 1 as shown in FIG. 6B.
Subsequently, another photo- resist ion- [0037] implantation mask 7 is formed on the insulating layer 4 through the photo- lithography, and p- type dopant impurity 8 such as, for example, boron is ion implanted into the surface portion of the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 20 to 200 keV as shown in FIG. 6C.
The photo- resist ion- [0038] implantation mask 7 is stripped off. The p- type dopant impurity is activated through an appropriate annealing, and forms the heavily- doped p- type isolating regions 2 on both sides of the n- type charge accumulating layer 3 as shown in FIG. 6D.
Subsequently, yet another photo- resist ion- [0039] implantation mask 7 is patterned on the insulating layer 4 through the photo- lithography, and p- type dopant impurity 10 is ion implanted into the surface portion of the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 50 to 200 keV as shown in FIG. 6E.
The photo- resist ion- [0040] implantation mask 7 is stripped off, and the ionimplanted p- type dopant impurity 10 forms the p- type local impurity region 6 as shown in FIG. 6F.
Conductive material is deposited over the entire surface of the resultant structure, and forms a conductive layer extending over the insulating [0041] layer 4. A photo- resist etching mask is patterned on the conductive layer through the photo- lithography, and an appropriate etchant selectively removes the conductive material from the conductive layer. As a result, the transfer electrodes 5 are left on the insulating layer 4 as shown in FIG. 6G.
As will be understood from the foregoing description, the n- type [0042] charge accumulating layer 3 is formed through the heavy doping, which is followed by the ion-implantation with the p- type dopant impurity 10. This results in the heavily- doped peripheral regions of the n- type charge accumulating layer 3 and the p-n junction penetrating into both of the central region and the n-type semiconductor substrate 1. The heavily- doped n- type peripheral regions and the p-n junction increase the amount of signal charge accumulated in each unit cell, and restrict the pulse height of the pulse signal for the substrate shutter.
Turning to FIGS. 7A to [0043] 7I of the drawings, the charge coupled device shown in FIGS. 4A and 4B is fabricated as follows. The process starts with preparation of the n-type semiconductor substrate 1. Insulating material such as silicon oxide is grown on the major surface of the n- type semiconductor substrate 1, and forms an insulating layer 4. A photo- resist ion- implantation mask 7 is patterned on the insulating layer 4 through a photo- lithography. Using the photo- resist ion- implantation mask 7, n- type dopant impurity 9 is implanted into the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under acceleration energy of 50 to 200 keV as shown in FIG. 7A. The n- type dopant impurity 9 forms the n-type charge accumulating layer 3 in the surface portion of the n- type semiconductor substrate 1. The photo-resist ion- implantation mask 7 is stripped off, and the n- type dopant impurity is activated through an appropriate annealing. Thus, the n-type charge accumulating layer 3 is formed in the surface portion of the n- type semiconductor substrate 1 as shown in FIG. 7B.
Subsequently, another photo- resist ion- [0044] implantation mask 7 is formed on the insulating layer 4 through the photo- lithography, and p- type dopant impurity 8 is ion implanted into the surface portion of the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 20 to 200 keV as shown in FIG. 7C.
The photo- resist ion- [0045] implantation mask 7 is stripped off. The p- type dopant impurity is activated through an appropriate annealing, and forms the heavily- doped p- type isolating regions 2 on both sides of the n- type charge accumulating layer 3 as shown in FIG. 7D.
Subsequently, yet another photo- resist ion- [0046] implantation mask 7 is patterned on the insulating layer 4 through the photo- lithography, and has an opening over the central region of the n-type charge accumulating layer 3. The p- type dopant impurity 10 is ion implanted into the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹²under the acceleration energy of 50 to 200 keV as shown in FIG. 7E.
The p- [0047] type dopant impurity 10 makes the dopant impurity concentration in the central region of the n-type charge accumulating layer 3 low. The photo- resist ion- implantation mask 7 is stripped off, and the central region of the n-type charge accumulating layer 3 becomes thinner than the peripheral regions due to the p-type dopant impurity 10 as shown in FIG. 7F.
Subsequently, still another photo- resist ion- [0048] implantation mask 7 is patterned on the insulating layer 4, and has two elongated openings located in parallel over the central region of the n-type charge accumulating layer 3. The p- type dopant impurity 10 is ion implanted through the photo- resist ion-implantation mask 7 into the n-type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 50 to 200 keV as shown in FIG. 7G.
The photo- resist ion- implantation mask[0049] 7 is stripped off, and the p- type dopant impurity 10 forms the pair of p-type local impurity regions 6 as shown in FIG. 7H. The central region of the n-type charge accumulating layer 3 has been already decreased in dopant impurity concentration, and, accordingly, the p- type local impurity regions 6 have a high dopant impurity concentration.
Conductive material is deposited over the entire surface of the resultant structure, and forms a conductive layer extending over the insulating [0050] layer 4. A photo- resist etching mask is patterned on the conductive layer through the photo- lithography, and an appropriate etchant selectively removes the conductive material from the conductive layer. As a result, the transfer electrodes 5 are left on the insulating layer 4 as shown in FIG. 7I.
As will be understood from the foregoing description, the n- type [0051] charge accumulating layer 3 is formed through the heavy doping, which is followed by the ion-implantations with the p- type dopant impurity 10. This results in the heavily- doped peripheral regions of the n- type charge accumulating layer 3 and the p-n junctions penetrating into both of the central region and the n-type semiconductor substrate 1. The heavily- doped n- type peripheral regions and the p-n junctions increase the amount of signal charge accumulated in each unit cell, and restrict the pulse height of the pulse signal for the substrate shutter. Even though the n-type charge accumulating layer 3 is as wide as 5 microns, the pair of p- type local impurity regions 6 offers the p-n junction long enough to increase the amount of signal charge accumulated in each unit cell.
FIGS. 8A to [0052] 8I illustrate another process for fabricating the charge coupled device shown in FIGS. 4A and 4B. The process starts with preparation of the n-type semiconductor substrate 1. Insulating material such as silicon oxide is grown on the major surface of the n- type semiconductor substrate 1, and forms an insulating layer 4. A photo- resist ion- implantation mask 7 is patterned on the insulating layer 4 through a photo- lithography. Using the photo- resist ion- implantation mask 7, n- type dopant impurity 9 is implanted into the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under acceleration energy of 50 to 200 keV as shown in FIG. 8A.
The photo- resist ion- [0053] implantation mask 7 is stripped off, and the n- type dopant impurity 9 forms the n-type charge accumulating layer 3 in the surface portion of the n- type semiconductor substrate 1 as shown in FIG. 8B.
Subsequently, another photo- resist ion- [0054] implantation mask 7 is formed on the insulating layer 4 through the photo- lithography, and p- type dopant impurity 8 is ion implanted into the surface portion of the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 20 to 200 keV as shown in FIG. 8C.
The photo- resist ion- [0055] implantation mask 7 is stripped off. The p- type dopant impurity 8 forms the heavily- doped p- type isolating regions 2 on both sides of the n- type charge accumulating layer 3 as shown in FIG. 8D.
Subsequently, yet another photo- resist ion- [0056] implantation mask 7 is patterned on the insulating layer 4 through the photo- lithography, and has an opening over the central region of the n-type charge accumulating layer 3. The p- type dopant impurity 10 is obliquely ion implanted into the n- type semiconductor substrate 1 at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 50 to 200 keV as shown in FIG. 8E. The direction of ion-implantation is from 10 to 60 degrees with respect to a normal line to the major surface of the n-type semiconductor substrate 1. The photo- resist ion-implantation mask 7 offers shade in the area exposed to the opening thereof, and the p- type dopant impurity 10 is not introduced into the n- type semiconductor substrate 1 under the shade.
The p- type [0057] local impurity region 6 is formed in the right portion of the central region of the n- type charge accumulating layer 3 as shown in FIG. 8F. The p- type local impurity region 6 is narrower than the opening of the photo- resist ion- implantation mask 7. Thus, the extremely narrow p-type local impurity region 6 is formed through the oblique ion- implantation.
Subsequently, still another photo- resist ion- [0058] implantation mask 7 is patterned on the insulating layer 4, and the oblique ion- implantation is carried out at a different direction at dosage of 5×10¹¹to 1×10¹³under the acceleration energy of 50 to 200 keV as shown in FIG. 8G. The direction of ion-implantation is 50 to 200 degrees with respect to the normal line. The p- type dopant impurity 10 forms the other p- type local impurity region 6 in the left portion of the central region of the n- type charge accumulating layer 3. The photo- resist ion- implantation mask 7 is stripped off, and the pair of p- type local impurity regions 6 are formed in the central region of the n-type charge accumulating layer 3 like stripes as shown in FIG. 8H.
As described hereinbefore, the p- type [0059] local impurity regions 6 are narrower than the opening of the photo- resist ion- implantation mask 7. If the opening has the minimum width patternable through the photo- lithography, each of the p- type local impurity regions 6 is narrower than the minimum pattern width, and the manufacturer can form the plural p- type local impurity regions 6 in the miniature unit cells less than 5 microns by using the oblique ion- implantation.
Conductive material is deposited over the entire surface of the resultant structure, and forms a conductive layer extending over the insulating [0060] layer 4. A photo- resist etching mask is patterned on the conductive layer through the photo- lithography, and an appropriate etchant selectively removes the conductive material from the conductive layer. As a result, the transfer electrodes 5 are left on the insulating layer 4 as shown in FIG. 8I.
As will be understood from the foregoing description, the n- type [0061] charge accumulating layer 3 is formed through the heavy doping, which is followed by the oblique ion-implantations with the p- type dopant impurity 10. This results in the heavily- doped peripheral regions of the n- type charge accumulating layer 3 and the p-n junctions penetrating into both of the central region and the n- type semiconductor substrate 1. The heavily- doped n- type peripheral regions and the p-n junctions increase the amount of signal charge accumulated in each unit cell, and restrict the pulse height of the pulse signal for the substrate shutter. Even though the n-type charge accumulating layer 3 is less than 5 microns in width, the pair of p- type local impurity regions 6 offers the p-n junction long enough to increase the amount of signal charge accumulated in each unit cell.
Moreover, the effective photo- electric converting region becomes deep, and the sensitivity is enhanced. [0062]
Although particular embodiments of the present invention have been shown and described, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention. [0063]
For example, the p- type local impurity region or regions may be shaped in another configuration different from the stripe or stripes. [0064]
If the photo- resist ion- [0065] implantation mask 7 shown in FIG. 6E is replaced with another photo- resist ion- implantation mask with two parallel openings, the process for the charge coupled device shown in FIGS. 3A and 3B are available for the charge coupled device shown in FIGS. 4A and 4B.
The manufacturer may change the order of the steps shown in FIGS. 6A and 6B, the steps shown in FIGS. 6C and 6D and the steps shown in FIGS. 6E and 6F. [0066]
The manufacturer may change the order of the steps shown in FIGS. 7A and 7B, the steps shown in FIGS. 7C and 7D, the steps shown in FIGS. 7E and 7F and the steps shown in FIGS. 7G and 7H. [0067]
The manufacturer may change the order of the steps shown in FIGS. 8A and 8B, the steps shown in FIGS. 8C and 8D and the steps shown in FIGS. 8E, 8F, [0068] 8G and 8H.
The n-type dopant impurity and the p- type dopant impurity may be exchanged in still another process according to the present invention. [0069]
The dosage and the acceleration energy described in conjunction with the processes are appropriate on the assumption that the semiconductor substrate, the n-type dopant impurity and the p- type dopant impurity are a silicon substrate, phosphorous and boron. However, if the semiconductor substrate is, by way of example, formed of gallium arsenide or silicon carbide, different dopant impurities are used, and, accordingly, the conditions of ion- implantation are different. Thus, the process conditions are variable together with the material used for the substrate. [0070]

Claims

What is claimed is:

1. A charge coupled device fabricated on a semiconductor substrate of a first conductivity type:

isolating regions having a second conductivity type opposite to said first conductivity type, and spaced from each other in a surface portion of said semiconductor substrate;

a charge accumulating layer of said first conductivity type formed in said surface portion between said isolating regions;

an insulating layer formed on said isolating regions and said charge accumulating layer;

transfer electrodes formed on said insulating layer along said charge accumulating layer; and

a local impurity region of said second conductivity type formed in said semiconductor substrate, projecting into a central region of said charge accumulating layer for forming a p-n junction, and spaced from said isolating regions.

2. The charge coupled device as set forth in

claim 1

, in which said charge accumulating layer is equal in width to or less than 5 microns.

3. The charge coupled device as set forth in

claim 2

, in which said local impurity region extends like a single stripe along said charge accumulating layer.

4. The charge coupled device as set forth in

claim 3

, in which said local impurity region has a width equal to or less than a half of the distance between said isolating regions.

5. The charge coupled device as set forth in

claim 2

, in which said local impurity region has plural local impurity sub- regions extending in parallel along said charge accumulating layer like stripes.

6. A process for fabricating a charge coupled device, comprising the steps of:

a) preparing a semiconductor substrate of a first conductivity type covered with an insulating layer;

b) introducing a first dopant impurity into a surface portion of said semiconductor substrate for forming a charge accumulating layer of said first conductivity type;

c) introducing a second dopant impurity into surface portions of said semiconductor substrate on both sides of said surface portion for forming isolating regions of a second conductivity type opposite to said first conductivity type;

d) introducing a third dopant impurity into a region of said semiconductor substrate for forming a local impurity region of said second conductivity type projecting into a central region of said charge accumulating layer and spaced from said isolating regions; and

e) forming transfer electrodes over said charge accumulating layer.

7. The process as set forth in

claim 6

, in which said third dopant impurity is introduced into said region by using an ion- implantation.

8. The process as set forth in

claim 6

, in which said step d) includes the sub-steps of

d-1) forming a first mask having an opening on said insulating layer over said central region, and

d-2) implanting said third dopant impurity through said opening into said central region for forming said local impurity regions.

9. The process as set forth in

claim 6

, in which said step d) includes the sub-steps of

d-1) forming a first mask having a first opening on said insulating layer over said central region,

d-2) implanting said third dopant impurity through said first opening into said central region so as to make said central region thinner than peripheral regions of said charge accumulating layer on both sides of said central region,

d-3) removing said first mask from said insulating layer,

d-4) forming a second mask having second openings each narrower than said first opening on said insulating layer over said charge accumulating layer,

d-5) implanting said third dopant impurity through said second openings into said central region for forming a pair of local impurity sub- regions serving as said local impurity region in said central region, and

d-6) removing said second mask from said insulating layer.

10. The process as set forth in

claim 6

, in which said step d) includes the sub- steps of

d-2) obliquely implanting said third dopant impurity through said first opening into said central region for forming a first local impurity sub-region in a first side sub-region of said central region,

d-3) removing said first mask from said insulating layer,

d-4) forming a second mask having a second opening on said insulating layer over said central region,

d-5) obliquely implanting said third dopant impurity through said second opening into a second side sub-region of said central region opposite to said first side sub-region for forming a second local impurity sub- region in said second side sub-region, said first local impurity sub-region and said second local impurity sub-region serving as said local impurity region, and

d-6) removing said second mask from said insulating layer.