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US20010013625A1 - Diode structure compatible with silicide processes for esd protection - Google Patents

Diode structure compatible with silicide processes for esd protection Download PDF

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Publication number
US20010013625A1
US20010013625A1 US09/270,830 US27083099A US2001013625A1 US 20010013625 A1 US20010013625 A1 US 20010013625A1 US 27083099 A US27083099 A US 27083099A US 2001013625 A1 US2001013625 A1 US 2001013625A1
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diode structure
diffusion region
conductivity type
type
semiconductor layer
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US09/270,830
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US6297536B2 (en
Inventor
Ta-Lee Yu
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Winbond Electronics Corp
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Winbond Electronics Corp
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Assigned to WINDBOND ELECTRONICS CORP. reassignment WINDBOND ELECTRONICS CORP. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: YU, TA-LEE
Assigned to WINBOND ELECTRONICS CORP. reassignment WINBOND ELECTRONICS CORP. CORRECTIVE ASSIGNMENT TO CORRECT THE NAME OF ASSIGNEE PREVIOUSLY RECORDED ON REEL 9836, FRAME 0553. Assignors: YU, TA-LEE
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/201—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits
    • H10D84/204—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors
    • H10D84/221—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of only components covered by H10D1/00 or H10D8/00, e.g. RLC circuits of combinations of diodes or capacitors or resistors of only diodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00—Diodes
    • H10D8/411—PN diodes having planar bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D89/00—Aspects of integrated devices not covered by groups H10D84/00 - H10D88/00
    • H10D89/60—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD]
    • H10D89/601—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs
    • H10D89/611—Integrated devices comprising arrangements for electrical or thermal protection, e.g. protection circuits against electrostatic discharge [ESD] for devices having insulated gate electrodes, e.g. for IGFETs or IGBTs using diodes as protective elements

Definitions

  • the present invention generally relates to electrostatic discharge protection for semiconductor integrated circuitry. More particularly, the present invention relates to an improved diode structure compatible with silicide processes for electrostatic discharge protection.
  • ESD electrostatic discharge
  • the diode D 1 or D 2 of FIG. 1 disposed on a semiconductor substrate 20 is illustrated in a cross-sectional view.
  • an insulator 21 such as field oxide grown by means of local oxidation, are provided on the P-type semiconductor substrate 20 .
  • An N-type diffusion region 22 is formed in the semiconductor substrate 20 and encircled by the insulator 21 . Therefore, diodes D 1 or D 2 are constituted by the P/N junction between the N-type diffusion region 22 and the P-type substrate 20 .
  • a silicide layer 23 can be formed over the N-type diffusion region 22 by a so-called self-aligned silicidation (salicide) process to reduce the contact sheet resistance.
  • the above object can be realized by providing a diode structure comprising: a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region.
  • the doped region has a doping concentration less than the diffusion region to provide a ballastic resistance under a high current stressing condition.
  • FIG. 1 depicts the circuit diagram of a conventional diode-based ESD protection circuit
  • FIG. 2 depicts the diode of FIG. 1 disposed on a semiconductor substrate in a cross-sectional view
  • FIG. 3 depicts one preferred embodiment in accordance with the present invention disposed on a semiconductor substrate in a cross-sectional view
  • FIG. 4 depicts the top view of FIG. 3;
  • FIG. 5 depicts another preferred embodiment in accordance with the present invention disposed on a semiconductor substrate in a cross-sectional view.
  • reference numeral 30 designates a P-type semiconductor substrate or a P-well formed in a semiconductor substrate, commonly termed a “P-type semiconductor layer”.
  • a ring-shaped gate structure 31 is formed on the P-type semiconductor layer 30 .
  • the gate structure 31 includes a gate electrode layer 31 A and a gate dielectric layer 31 B.
  • An inner sidewall spacer 32 is formed on the inner sidewall of the gate structure 31 and an outer sidewall spacer 33 is formed on the outer sidewall thereof.
  • N-type lightly-doped regions 34 and 35 are formed in the semiconductor layer 30 beneath the inner spacer 32 and outer spacer 33 , respectively.
  • An N-type heavily-doped diffusion region 36 is formed in the P-type semiconductor layer 30 within the range encircled by the gate structure 31 .
  • the diffusion edge is encircled by the N-type lightly-doped region 34 having a doping concentration and a junction depth less than those of the N-type diffusion region 36 .
  • a silicide layer 37 is formed over the N-type diffusion region 36 so as to reduce the contact sheet resistance.
  • the whole edge of the diffusion region 36 is encompassed by the N-type lightly-doped region 34 to increase the ballastic resistance of the diode under high current stressing conditions. Therefore, during an ESD event a discharge current can flow through the silicide layer 37 as well as the N-type diffusion region 36 , and then pass through the junction between the N-type diffusion region 36 and the P-type semiconductor layer 30 uniformly. Accordingly, the diode structure of the present invention prevents the diffusion edge from current localization and thus protects the diode contact from ESD damage.
  • the diode structure of the present invention is compatible with the self-aligned silicidation and lightly-doped drain (LDD) processes applied to the internal circuit.
  • LDD lightly-doped drain
  • the N-type and P-type are exemplified in FIGS. 3 and 4, the fact that the N-type and P-type are interchangeable is apparent to those skilled in the art.
  • reference numeral 50 designates a P-type semiconductor substrate or a P-well formed in a semiconductor substrate, commonly termed a “P-type semiconductor layer”.
  • a ring-shaped insulative structure 51 is formed on the P-type semiconductor layer 50 .
  • the insulative structure 51 is field oxide formed by local oxidation of silicon (LOCOS) procedure.
  • An N-type heavily-doped diffusion region 52 is formed in the P-type semiconductor layer 50 within the range encircled by the insulative structure 51 .
  • the diffusion edge is encircled by an N-well region 53 having a doping concentration less than that of the N-type diffusion region 52 and a junction depth greater than that of the N-type diffusion region 36 .
  • a silicide layer 54 is formed over the N-type diffusion region 52 so as to reduce the contact sheet resistance.
  • the whole edge of the diffusion region 52 is encompassed by the N-well 53 to increase the ballastic resistance of the diode under high current stressing conditions. Therefore, during an ESD event a discharge current can flow through the silicide layer 54 as well as the N-type diffusion region 52 , and then pass through the junction between the N-type diffusion region 52 and the P-type semiconductor layer 50 uniformly. Accordingly, the diode structure of the present invention prevents the diffusion edge from current localization and thus protects the diode contact from ESD damage.
  • the diode structure of the present invention is compatible with the self-aligned silicidation and lightly-doped drain (LDD) processes applied to the internal circuit.
  • LDD lightly-doped drain
  • the N-type and P-type are exemplified in FIG. 5, the fact that the N-type and P-type are interchangeable is apparent to those skilled in the art.
  • the diode structure of the present invention is provided with a light-doped region or well region encircling the diffusion edge to increase the ballastic resistance under high current stressing conditions.
  • a discharge current can flow through the silicide layer as well as the diffusion junction, and then pass through the P/N junction between the diffusion region and the substrate uniformly. Accordingly, the discharge current is prevented from localization through the diffusion edge to protect the diode from ESD damage.

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  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

A diode structure compatible with silicide processes for electrostatic discharge protection is disclosed. The diode structure comprises a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region. The doped region has a doping concentration less than that of the diffusion region to provide a ballastic resistance under a high current stressing condition.

Description

    BACKGROUND OF THE INVENTION
  • 1. Field of the Invention [0001]
  • The present invention generally relates to electrostatic discharge protection for semiconductor integrated circuitry. More particularly, the present invention relates to an improved diode structure compatible with silicide processes for electrostatic discharge protection. [0002]
  • 2. Description of the Related Art [0003]
  • In sub-micron MOS-based technology, electrostatic discharge, ESD hereinafter, becomes a reliability concern. As shown in FIG. 1, a pair of diodes D[0004] 1 and D2 are provided at the pad 1 of a conventional integrated circuit. When ESD occurs at the pad 1, the diode D1 or D2 enters breakdown to bypass the ESD stress so as to protect the internal circuit 2 from ESD damage.
  • Referring to FIG. 2, the diode D[0005] 1 or D2 of FIG. 1 disposed on a semiconductor substrate 20 is illustrated in a cross-sectional view. In FIG. 2, an insulator 21, such as field oxide grown by means of local oxidation, are provided on the P-type semiconductor substrate 20. An N-type diffusion region 22 is formed in the semiconductor substrate 20 and encircled by the insulator 21. Therefore, diodes D1 or D2 are constituted by the P/N junction between the N-type diffusion region 22 and the P-type substrate 20. In addition, a silicide layer 23 can be formed over the N-type diffusion region 22 by a so-called self-aligned silicidation (salicide) process to reduce the contact sheet resistance.
  • However, under high current stressing conditions the ballastic resistance is dramatically reduced. Hence, once the hot spot is initiated at the [0006] diffusion edge 24, there is very little resistance to prevent current localization through the hot spot. Therefore, when the temperature at the silicide reaches up to 1000° C., the silicide can begin to decompose or interact with the silicon, or both, and cause damage to the diode D1 or D2.
    • SUMMARY OF THE INVENTION
  • Therefore, it is an object of the present invention to provide a diode structure compatible with the silicide process without additional process steps. [0007]
  • The above object can be realized by providing a diode structure comprising: a semiconductor layer of a first conductivity type, a diffusion region of a second conductivity type formed in the semiconductor layer, and a doped region of the second conductivity type formed in the semiconductor layer around the diffusion region. The doped region has a doping concentration less than the diffusion region to provide a ballastic resistance under a high current stressing condition. [0008]
  • Accordingly, during an ESD event a discharge current can flow through the silicide layer as well as the diffusion junction, and then pass through the P/N junction between the diffusion region and the substrate uniformly. Therefore, the discharge current is prevented from localization through the diffusion edge so as to protect the diode from ESD damage. [0009]
    • BRIEF DESCRIPTION OF DRAWINGS
  • The following detailed description, given by way of examples and not intended to limit the invention to the embodiments described herein, will best be understood in conjunction with the accompanying drawings, in which: [0010]
  • FIG. 1 depicts the circuit diagram of a conventional diode-based ESD protection circuit; [0011]
  • FIG. 2 depicts the diode of FIG. 1 disposed on a semiconductor substrate in a cross-sectional view; [0012]
  • FIG. 3 depicts one preferred embodiment in accordance with the present invention disposed on a semiconductor substrate in a cross-sectional view; [0013]
  • FIG. 4 depicts the top view of FIG. 3; and [0014]
  • FIG. 5 depicts another preferred embodiment in accordance with the present invention disposed on a semiconductor substrate in a cross-sectional view. [0015]
    • DETAILED DESCRIPTION OF THE INVENTION
  • First Embodiment [0016]
  • Referring to FIGS. 3 and 4, the cross-sectional view and top view of a diode structure disposed on a semiconductor substrate in accordance with one preferred embodiment of the present invention are illustrated, respectively. In the drawing, [0017] reference numeral 30 designates a P-type semiconductor substrate or a P-well formed in a semiconductor substrate, commonly termed a “P-type semiconductor layer”.
  • In this case, a ring-[0018] shaped gate structure 31 is formed on the P-type semiconductor layer 30. From top to bottom the gate structure 31 includes a gate electrode layer 31A and a gate dielectric layer 31B. An inner sidewall spacer 32 is formed on the inner sidewall of the gate structure 31 and an outer sidewall spacer 33 is formed on the outer sidewall thereof. N-type lightly-doped regions 34 and 35 are formed in the semiconductor layer 30 beneath the inner spacer 32 and outer spacer 33, respectively. An N-type heavily-doped diffusion region 36 is formed in the P-type semiconductor layer 30 within the range encircled by the gate structure 31. Preferably, the diffusion edge is encircled by the N-type lightly-doped region 34 having a doping concentration and a junction depth less than those of the N-type diffusion region 36. Moreover, a silicide layer 37 is formed over the N-type diffusion region 36 so as to reduce the contact sheet resistance.
  • As shown in FIGS. 3 and 4, the whole edge of the [0019] diffusion region 36 is encompassed by the N-type lightly-doped region 34 to increase the ballastic resistance of the diode under high current stressing conditions. Therefore, during an ESD event a discharge current can flow through the silicide layer 37 as well as the N-type diffusion region 36, and then pass through the junction between the N-type diffusion region 36 and the P-type semiconductor layer 30 uniformly. Accordingly, the diode structure of the present invention prevents the diffusion edge from current localization and thus protects the diode contact from ESD damage.
  • Furthermore, the diode structure of the present invention is compatible with the self-aligned silicidation and lightly-doped drain (LDD) processes applied to the internal circuit. Thus, effective ESD protection can be provided without additional processing steps. In addition, though the N-type and P-type are exemplified in FIGS. 3 and 4, the fact that the N-type and P-type are interchangeable is apparent to those skilled in the art. [0020]
  • Second Embodiment [0021]
  • Referring to FIG. 5, the cross-sectional view of a diode structure disposed on a semiconductor substrate in accordance with another preferred embodiment of the present invention is illustrated. In the drawing, [0022] reference numeral 50 designates a P-type semiconductor substrate or a P-well formed in a semiconductor substrate, commonly termed a “P-type semiconductor layer”.
  • In this embodiment, a ring-shaped [0023] insulative structure 51 is formed on the P-type semiconductor layer 50. For example, the insulative structure 51 is field oxide formed by local oxidation of silicon (LOCOS) procedure. An N-type heavily-doped diffusion region 52 is formed in the P-type semiconductor layer 50 within the range encircled by the insulative structure 51. In addition, the diffusion edge is encircled by an N-well region 53 having a doping concentration less than that of the N-type diffusion region 52 and a junction depth greater than that of the N-type diffusion region 36. Moreover, a silicide layer 54 is formed over the N-type diffusion region 52 so as to reduce the contact sheet resistance.
  • As shown in FIG. 5, the whole edge of the [0024] diffusion region 52 is encompassed by the N-well 53 to increase the ballastic resistance of the diode under high current stressing conditions. Therefore, during an ESD event a discharge current can flow through the silicide layer 54 as well as the N-type diffusion region 52, and then pass through the junction between the N-type diffusion region 52 and the P-type semiconductor layer 50 uniformly. Accordingly, the diode structure of the present invention prevents the diffusion edge from current localization and thus protects the diode contact from ESD damage.
  • Furthermore, the diode structure of the present invention is compatible with the self-aligned silicidation and lightly-doped drain (LDD) processes applied to the internal circuit. Thus, effective ESD protection can be provided without additional processing steps. In addition, though the N-type and P-type are exemplified in FIG. 5, the fact that the N-type and P-type are interchangeable is apparent to those skilled in the art. [0025]
  • In summary, the diode structure of the present invention is provided with a light-doped region or well region encircling the diffusion edge to increase the ballastic resistance under high current stressing conditions. During an ESD event a discharge current can flow through the silicide layer as well as the diffusion junction, and then pass through the P/N junction between the diffusion region and the substrate uniformly. Accordingly, the discharge current is prevented from localization through the diffusion edge to protect the diode from ESD damage. [0026]
  • While the invention has been described with reference to various illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to those person skilled in the art upon reference to this description. It is therefore contemplated that the appended claims will cover any such modifications or embodiments as may fall within the scope of the invention defined by the following claims and their equivalents. [0027]

Claims (20)

What is claimed is:
1. A diode structure, comprising:
a semiconductor layer of a first conductivity type;
a diffusion region of a second conductivity type formed in said semiconductor layer; and
a doped region of the second conductivity type formed in said semiconductor layer around the edge of said diffusion region, wherein said doped region has a doping concentration less than that of said diffusion region to provide a ballastic resistance under a high current stressing condition.
2. The diode structure as claimed in
claim 1
, further comprising a gate ring formed on said semiconductor layer around said diffusion region.
3. The diode structure as claimed in
claim 2
, further comprising a spacer formed on the inner sidewall of said gate ring.
4. The diode structure as claimed in
claim 3
, wherein said doped region has a junction depth less than that of said diffusion region.
5. The diode structure as claimed in
claim 1
, wherein said doped region is a well region.
6. The diode structure as claimed in
claim 5
, wherein said doped region has a junction depth greater than that of said diffusion region.
7. The diode structure as claimed in
claim 1
, wherein the first conductivity type is P-type and the second conductivity type is N-type.
8. The diode structure as claimed in
claim 1
, wherein the first conductivity type is N-type and the second conductivity type is P-type.
9. The diode structure as claimed in
claim 1
, further comprising a silicide layer overlying said diffusion region.
10. A diode structure, comprising:
a semiconductor layer of a first conductivity type;
a diffusion region of a second conductivity type formed in said semiconductor layer;
a gate ring formed on said semiconductor layer around said diffusion region; and
a doped region of the second conductivity type formed in said semiconductor layer around the edge of said diffusion region, wherein said doped region has a doping concentration less than that of said diffusion region to provide a ballastic resistance under a high current stressing condition.
11. The diode structure as claimed in
claim 10
, further comprising a spacer formed on the inner sidewall of said gate ring.
12. The diode structure as claimed in
claim 11
, wherein said doped region has a junction depth less than that of said diffusion region.
13. The diode structure as claimed in
claim 10
, wherein the first conductivity type is P-type and the second conductivity type is N-type.
14. The diode structure as claimed in
claim 10
, wherein the first conductivity type is N-type and the second conductivity type is P-type.
15. The diode structure as claimed in
claim 10
, further comprising a silicide layer overlying said diffusion region.
16. A diode structure, comprising:
a semiconductor layer of a first conductivity type;
a diffusion region of a second conductivity type formed in said semiconductor layer;
a gate ring formed on said semiconductor layer around said diffusion region; and
a well region of the second conductivity type formed in said semiconductor layer around the edge of said diffusion region, wherein said well region has a doping concentration less than that of said diffusion region to provide a ballastic resistance under a high current stressing condition.
17. The diode structure as claimed in
claim 16
, wherein said well region has a junction depth greater than that of said diffusion region.
18. The diode structure as claimed in
claim 16
, wherein the first conductivity type is P-type and the second conductivity type is N-type.
19. The diode structure as claimed in
claim 16
, wherein the first conductivity type is N-type and the second conductivity type is P-type.
20. The diode structure as claimed in
claim 16
, further comprising a silicide layer overlying said diffusion region.
US09/270,830 1998-11-30 1999-03-18 Diode structure compatible with silicide processes for ESD protection Expired - Fee Related US6297536B2 (en)

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TW087119832A TW454251B (en) 1998-11-30 1998-11-30 Diode structure used in silicide process

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050230714A1 (en) * 2002-08-30 2005-10-20 Fujitsu Limited Semiconductor memory device and manufacturing method thereof
CN112185956A (en) * 2020-06-23 2021-01-05 晶焱科技股份有限公司 Bidirectional electrostatic discharge protection device
US11043520B2 (en) * 2016-09-02 2021-06-22 Sony Semiconductor Solutions Corporation Light-receiving device, method of manufacturing light-receiving device, imaging device, and electronic apparatus
US20230063032A1 (en) * 2017-10-31 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and static random access memory thereof

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US7605431B2 (en) * 2006-09-20 2009-10-20 Himax Technologies Limited Electrostatic discharge protection apparatus for semiconductor devices
TWI489616B (en) * 2011-08-26 2015-06-21 Himax Tech Ltd Electrostatic discharge protection component and circuit thereof

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US3246177A (en) * 1963-06-19 1966-04-12 Rca Corp Electronic switching circuit employing an insulated gate field-effect transistor having rectifier means connected between its gate and source or drain electrodes
US3339086A (en) * 1964-06-11 1967-08-29 Itt Surface controlled avalanche transistor
DE2159592C3 (en) * 1971-12-01 1981-12-17 Licentia Patent-Verwaltungs-Gmbh, 6000 Frankfurt Integrated semiconductor device
DE3818533C2 (en) * 1987-06-01 1994-05-26 Mitsubishi Electric Corp Field effect transistor
JP2785772B2 (en) * 1995-11-20 1998-08-13 日本電気株式会社 Method for manufacturing semiconductor device

Cited By (10)

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US20050230714A1 (en) * 2002-08-30 2005-10-20 Fujitsu Limited Semiconductor memory device and manufacturing method thereof
US7202540B2 (en) * 2002-08-30 2007-04-10 Fujitsu Limited Semiconductor memory device
US20070117303A1 (en) * 2002-08-30 2007-05-24 Fujitsu Limited Semiconductor memory device (as amended)
US20070114617A1 (en) * 2002-08-30 2007-05-24 Fujitsu Limited Semiconductor memory device
US7482226B2 (en) 2002-08-30 2009-01-27 Fujitsu Limited Semiconductor memory device
US7759745B2 (en) 2002-08-30 2010-07-20 Fujitsu Limited Semiconductor memory device
US11043520B2 (en) * 2016-09-02 2021-06-22 Sony Semiconductor Solutions Corporation Light-receiving device, method of manufacturing light-receiving device, imaging device, and electronic apparatus
US20230063032A1 (en) * 2017-10-31 2023-03-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and static random access memory thereof
US11910586B2 (en) * 2017-10-31 2024-02-20 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and static random access memory thereof
CN112185956A (en) * 2020-06-23 2021-01-05 晶焱科技股份有限公司 Bidirectional electrostatic discharge protection device

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TW454251B (en) 2001-09-11

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