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US20010003375A1 - Dual-die integrated circuit package - Google Patents

Dual-die integrated circuit package Download PDF

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Publication number
US20010003375A1
US20010003375A1 US09/458,264 US45826499A US2001003375A1 US 20010003375 A1 US20010003375 A1 US 20010003375A1 US 45826499 A US45826499 A US 45826499A US 2001003375 A1 US2001003375 A1 US 2001003375A1
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Prior art keywords
chip
die
chips
integrated circuit
circuit package
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Granted
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US09/458,264
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US6376914B2 (en
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Julius A. Kovats
Ken M. Lam
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Atmel Corp
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Individual
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Priority to US09/458,264 priority Critical patent/US6376914B2/en
Assigned to ATMEL CORPORATION reassignment ATMEL CORPORATION ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: KOVATS, JULIUS A., LAM, KEN M.
Priority to KR1020027007245A priority patent/KR20020055603A/en
Priority to JP2001543781A priority patent/JP2003516637A/en
Priority to PCT/US2000/041466 priority patent/WO2001043193A2/en
Priority to CN00816866A priority patent/CN1408125A/en
Priority to EP00986833A priority patent/EP1238430A2/en
Priority to CA002392975A priority patent/CA2392975A1/en
Priority to TW089124874A priority patent/TW472327B/en
Priority to MYPI20005650A priority patent/MY135947A/en
Publication of US20010003375A1 publication Critical patent/US20010003375A1/en
Publication of US6376914B2 publication Critical patent/US6376914B2/en
Application granted granted Critical
Priority to NO20022736A priority patent/NO20022736L/en
Assigned to MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT reassignment MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT PATENT SECURITY AGREEMENT Assignors: ATMEL CORPORATION
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Assigned to JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT reassignment JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
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Assigned to JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT reassignment JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INC., MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
Assigned to MICROSEMI STORAGE SOLUTIONS, INC., MICROSEMI CORPORATION, MICROCHIP TECHNOLOGY INC., ATMEL CORPORATION, SILICON STORAGE TECHNOLOGY, INC. reassignment MICROSEMI STORAGE SOLUTIONS, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
Assigned to WELLS FARGO BANK, NATIONAL ASSOCIATION reassignment WELLS FARGO BANK, NATIONAL ASSOCIATION SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INC., MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
Assigned to WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT reassignment WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT SECURITY INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: ATMEL CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., SILICON STORAGE TECHNOLOGY, INC.
Assigned to SILICON STORAGE TECHNOLOGY, INC., MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC., MICROCHIP TECHNOLOGY INCORPORATED, ATMEL CORPORATION reassignment SILICON STORAGE TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
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Assigned to MICROSEMI CORPORATION, ATMEL CORPORATION, SILICON STORAGE TECHNOLOGY, INC., MICROSEMI STORAGE SOLUTIONS, INC., MICROCHIP TECHNOLOGY INCORPORATED reassignment MICROSEMI CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Assigned to MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI STORAGE SOLUTIONS, INC., MICROSEMI CORPORATION, ATMEL CORPORATION, SILICON STORAGE TECHNOLOGY, INC. reassignment MICROCHIP TECHNOLOGY INCORPORATED RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Assigned to SILICON STORAGE TECHNOLOGY, INC., ATMEL CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI CORPORATION, MICROSEMI STORAGE SOLUTIONS, INC. reassignment SILICON STORAGE TECHNOLOGY, INC. RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Assigned to ATMEL CORPORATION, SILICON STORAGE TECHNOLOGY, INC., MICROSEMI CORPORATION, MICROCHIP TECHNOLOGY INCORPORATED, MICROSEMI STORAGE SOLUTIONS, INC. reassignment ATMEL CORPORATION RELEASE BY SECURED PARTY (SEE DOCUMENT FOR DETAILS). Assignors: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49575—Assemblies of semiconductor devices on lead frames
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32135—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/8538—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/85399—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes
    • H01L2225/04—All the devices being of a type provided for in the same main group of the same subclass of class H10, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same main group of the same subclass of class H10
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06555—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06562—Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking at least one device in the stack being rotated or offset
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/30107—Inductance

Definitions

  • This invention relates to integrated circuit packages and more particularly to integrated circuit packages having multiple semiconductor chips (dies).
  • a chip package is used to protect integrated circuit chips from contamination and abuse and is used to provide a durable and substantial electrical lead system for connecting integrated circuit chips onto an external printed circuit board or directly into a electronic product.
  • IC integrated circuit
  • the multi-chip package minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuities between the chips mounted on the substrate by replacing the die-wirebond-pin-board-pin-wirebond-die path with a much superior die-bump-interconnect-bump-die path. Additionally, narrower and shorter wires on the ceramic substrate have much less capacitance and inductance than the printed circuit board interconnections. It is often advantageous to stack multiple identical IC chips into the same chip package in order to increase memory without using valuable space on the printed circuit board.
  • one of the common methods of combining IC chips into a single package is to use a stacked die IC package 50 in which the top IC chip 16 is smaller than the bottom IC chip 14 in order to allow access on the bottom IC chip 14 for wirebonding leads 26 . If the two IC chips are the same size, as in the stacked IC die package 60 of FIG. 7, then the top IC chip 16 must be offset from the bottom IC chip 14 in order to allow wirebonding access to the bottom IC chip 14 . This limits access for the wirebonding leads 26 to one or two sides of the package, which is frequently not practical for assembly.
  • FIG. 8 Another common method of combining IC chips of the same size, that is known in the prior art, involves placing one of the IC chips underneath the leadframe in a package, as shown in FIG. 8.
  • the top IC chip 16 is stacked on top of the leadframe 18 of the chip package while the bottom IC chip 14 is attached underneath the leadframe 18 .
  • the disadvantage to the die-underneath method of FIG. 8 is that the chips must be mirror images of each other, thereby requiring two complete IC fabrication steps.
  • U.S. Pat. No. 5,399,898 to Rostoker discloses multi-chip, multi-tier semiconductor package arrangements based upon single and double-sided flip chips. These arrangements are based on a stacked structure similar to FIGS. 6 and 7 noted above.
  • U.S. Pat. No. 5,656,553 to Leas et al. discloses a fabrication method and resultant monolithic module comprising a plurality of stacked planar extending arrays of integrated circuit chips.
  • the stacked die arrangement shown in the '553 patent uses edge connections to connect the upper die to the lower die. While this method of stacking multiple IC die addresses the case where two identical die are stacked, the method does not allow for routing flexibility, as the circuit routing is vertical from top to bottom and if there is any crossover, the chip package will not operate properly.
  • a dual-die integrated circuit package having two chips (dies) which can be identically constructed from a wafer fabrication processing standpoint and are “flip chip” attached to each other using standard solder bumping and solder reflow technology.
  • the first chip is aligned at a specified angle in relation to the second chip such that at least one of the bonding pads on the surface of each of the chips remain exposed for connection into a standard chip package.
  • two rectangular chips are aligned such that one chip is rotated at an angle of 90 degrees in relation to the other chip, such that the non-overlapping surfaces are exposed to enable chip package assembly.
  • the chips are aligned at an angle of less than 90 degrees such that at least a small portion, such as a corner, of each chip is exposed for chip package assembly. This embodiment would be preferable for the case when the two chips are of a square shape.
  • the two chips are of different sizes, as a larger chip is arranged on top of a smaller chip and is rotated at an angle such that the lower chip has at least some minimum area accessible for assembly. This ability to mount a larger IC chip over a smaller IC chip would be valuable to an IC manufacturer who controls the design of the smaller die, but purchases the larger die from another source.
  • the present invention allows for doubling the functionality or memory of a chip package while using the same package footprint as a single chip and using only one IC design.
  • the integrated circuit package of the present invention allows for flexibility in wirebonding and routing and can be implemented in a single IC fabrication step.
  • the present invention allows IC manufacturers to develop products with double the memory or functionality in a much faster time frame by providing the ability to use multiple identical chips in the same package without having to make significant design changes to the chips.
  • FIG. 1 is a top view of a first embodiment of the dual-die integrated circuit package of the present invention, with the encapsulant material removed.
  • FIG. 2 is a perspective view of the two chips showing the interconnection between the two chips.
  • FIG. 3 is a top view of the dual-die integrated circuit package of FIG. 1 showing the two chips being attached to a leadframe.
  • FIG. 4 is a side view of the dual-die integrated circuit package of FIG. 1.
  • FIG. 5 is a top view of a second embodiment of the dual-die integrated circuit package of the present invention, with the encapsulant material removed.
  • FIG. 6 is a side view of a first stacked die IC package, as known in the prior art.
  • FIG. 7 is a side view of a second stacked die IC package, as known in the prior art.
  • FIG. 8 is a side view of a die-underneath IC package, as known in the prior art.
  • a first embodiment of the integrated circuit (IC) package 10 of the present invention is shown to include a top IC chip 16 and a bottom IC chip 14 which are aligned in a 90 degree relation with respect to each other.
  • the chips 14 , 16 are arranged on a flat die-attachment surface 12 of a leadframe 18 .
  • the leadframe 18 is made of a single piece of metal and extends from the die-attachment surface 12 to a plurality of outer leads 20 that are arranged around the perimeter of the IC package 10 and which extend downward for use in mounting the IC package 10 to an external printed circuit board.
  • the top IC chip 16 is mechanically and electrically connected to the bottom IC chip 14 using a “flip chip” method with standard solder bumping and solder reflow technology.
  • the connections between the chips 16 and 14 are made by solder bumps 22 on each of the chips which can be arranged in a diagonal or in an “x” pattern.
  • the solder bumps 22 can be made as part of the original fabrication process or can be added afterwards using redistribution of electrical traces.
  • FIG. 2 illustrates the case where the process of redistribution is used.
  • On the original fabricated chip layer 23 of each of the chips 14 and 16 there are a plurality of bonding pads 49 , shown in dashed lines, arranged around the perimeter of the chips. In FIG.
  • the bonding pads 49 are arranged on the bottom side 17 of the top chip 16 and on the top side 15 of the bottom chip 14 .
  • the bonding pads 49 are electrical terminals used for connecting the chips 14 , 16 into a chip package.
  • Each of the bonding pads 49 correspond to a particular circuit in the chip, such as power input, ground, memory address, etc.
  • a series of solder pads 22 are arranged in a diagonal pattern on the surface of the chip layer 23 . If only a few connections are required, it is preferable that the solder bumps be made at the corners of the chips in order to minimize the number of solder bumps in the middle part of a chip, since that is where the memory array and other sensitive circuitry are located.
  • routing traces 24 are then provided on the surface of each of the chips 14 , 16 in order to connect the circuitry from the bonding pads 49 to the solder bumps 22 .
  • Circuits that are common to both chips 14 , 16 such as ground, power input, and the clock signal for example, would be routed on each chip from the particular bonding pad corresponding to that circuit to a particular solder bump on each chip, the particular solder bumps on each chip being aligned together for interconnection. Circuits that are not common to each chip, such as chip enable for example, would not be routed to the solder bumps.
  • the solder bumps 22 can also function as jumpers in order to connect circuits on the bottom chip 14 with circuits on the top chip 16 when the two chips are attached.
  • routing traces may be added on the surface of the chip in order to connect the solder bumps with particular bonding pads which will be used for connecting the chips into the chip package.
  • a new passivation layer 21 is provided over the surfaces 15 , 17 of the chips 14 , 16 and the solder bumps 22 are brought through the passivation layer 21 to be exposed for interconnection.
  • Some of the wire bonding pads 49 are also brought through the passivation layer 21 , and will constitute the exposed bonding pads 29 used for connection of the chip into the chip package.
  • the two chips 14 , 16 are then aligned at a 90 degree angle such that the solder bumps 22 are lined up for interconnection when the top chip 16 is flipped over on top of the bottom chip 14 , as shown by the arrow 11 .
  • Other methods of connecting the two chips together can include the use of anisotropic (“Z-axis”) epoxy or other conductive solder metalizations.
  • the bottom chip 14 of the attached chips is secured to the die-attachment surface 12 of the leadframe by an epoxy material. Because the two rectangular IC chips 14 and 16 are aligned at a 90 degree angle with respect to each other, the exposed bonding pads 29 on the bottom chip 14 are accessible for wirebond attachment into the chip package 10 . Wire bonding leads 26 are used to attach the exposed bonding pads 29 to the inner leads 19 of the leadframe. The inner leads 19 extend outward to form the outer leads 20 which are used to provide connection to other external circuits which provide the power and other input and output signals to the chip package 10 .
  • the die-attachment surface 12 of the leadframe 18 supports the bottom IC chip 14 which is wirebonded 26 to the leadframe 18 and leads 20 .
  • the top IC chip 16 is connected by the solder bumps 22 to the bottom IC chip 14 . Because the chips are rotated 90 degrees with respect to one another the portion on either end of the bottom IC chip is exposed for connection of the wirebond leads 26 .
  • An encapsulant material 28 is then used to cover the top of the IC package 10 , including the two chips 14 , 16 and the top of the die attachment surface 12 , such that the leads 20 of the leadframe 18 remain at least partially exposed.
  • the encapsulant material 28 has been cut away so that the interior of the IC package 10 can be viewed, but in the production of the chip package the encapsulant material 28 would completely cover the chips 14 , 16 .
  • the encapsulant material 28 is preferably an epoxy overcoat or plastic molding.
  • the IC chip package 30 of the second embodiment shows the top IC chip 36 being aligned with the bottom IC chip 34 at an angle of less than 90 degrees. This configuration is useful for IC chips that are square, but can also be used for rectangular chips. By aligning the top IC chip 36 at an offset angle from the bottom IC chip 34 , an area 38 on the bottom chip 34 is exposed for wirebonding of the chip 34 to the leads 40 .
  • the present invention can also be implemented with two chips of differing sizes.
  • the top IC chip 36 would be larger than the bottom IC chip. Because the top IC chip 36 is rotated in relation to the bottom IC chip 34 , even though the larger IC chip 36 is on top, the bottom chip 34 still has an area 38 exposed to allow accessibility for wirebonding. This would be valuable to a manufacturer who controls the design of the smaller IC chip but purchases the larger IC chip from a second source.
  • the dual-die IC package of the present invention has been described above in terms of being a PLCC (Plastic Leadless Chip Carrier) type of package, the dual-die IC chip package of the present invention can also be implemented with other types of package designs known in the art, such as ball grid arrays which use solder bumps on the bottom of the package rather than leads in order to connect the chip package to a printed circuit board.
  • the method of constructing the chip package is the same as described above, except for the particular manner in which the electrical connections are made between the chip package and an external circuit.
  • the dual-die IC package of the present invention can also be a thin package type, such as a flat pack, or small outline IC (SOIC), by using the same construction techniques described above.

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  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
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Abstract

A dual-die integrated circuit package having two integrated circuit chips “flip chip” attached to each other and with one of the chips being aligned at a specified angle in relation to the other chip to allow access to bonding pads on the surface of each chip for wirebonding connection into the chip package. In a first embodiment, the two chips are rectangular in shape and are aligned at an angle of 90 degrees with respect to each other, thus allowing the end portions of the bottom chip to be accessible for connection into the chip package. Other embodiments maintain the chips at angles of less than 90 degrees, such that corner portions of each chip are accessible for connection into the chip package. The invention allows two identically constructed chips to be used for doubling or even greater multiplication of the functionality or memory of the IC package, while still using the same package footprint as for a single chip. Also, being able to use two chips that are identically constructed from a wafer fabrication standpoint provides the advantage of requiring only one IC design process.

Description

    TECHNICAL FIELD
  • This invention relates to integrated circuit packages and more particularly to integrated circuit packages having multiple semiconductor chips (dies). [0001]
    • BACKGROUND ART
  • A chip package is used to protect integrated circuit chips from contamination and abuse and is used to provide a durable and substantial electrical lead system for connecting integrated circuit chips onto an external printed circuit board or directly into a electronic product. There are numerous advantages to providing a multi-chip integrated circuit (IC) package over single-chip carriers. By placing multiple chips directly on a substrate that provides low-inductance and low-capacitance connections between the chips and the signal/power lines, and that supplies a very dense interconnection network, packaging density and system performance can be improved. The multi-chip package minimizes the chip-to-chip spacing and reduces the inductive and capacitive discontinuities between the chips mounted on the substrate by replacing the die-wirebond-pin-board-pin-wirebond-die path with a much superior die-bump-interconnect-bump-die path. Additionally, narrower and shorter wires on the ceramic substrate have much less capacitance and inductance than the printed circuit board interconnections. It is often advantageous to stack multiple identical IC chips into the same chip package in order to increase memory without using valuable space on the printed circuit board. [0002]
  • With reference to FIG. 6, in the prior art, one of the common methods of combining IC chips into a single package is to use a stacked [0003] die IC package 50 in which the top IC chip 16 is smaller than the bottom IC chip 14 in order to allow access on the bottom IC chip 14 for wirebonding leads 26. If the two IC chips are the same size, as in the stacked IC die package 60 of FIG. 7, then the top IC chip 16 must be offset from the bottom IC chip 14 in order to allow wirebonding access to the bottom IC chip 14. This limits access for the wirebonding leads 26 to one or two sides of the package, which is frequently not practical for assembly. Another common method of combining IC chips of the same size, that is known in the prior art, involves placing one of the IC chips underneath the leadframe in a package, as shown in FIG. 8. In the IC package 70 of FIG. 8, the top IC chip 16 is stacked on top of the leadframe 18 of the chip package while the bottom IC chip 14 is attached underneath the leadframe 18. The disadvantage to the die-underneath method of FIG. 8 is that the chips must be mirror images of each other, thereby requiring two complete IC fabrication steps.
  • U.S. Pat. No. 5,399,898 to Rostoker discloses multi-chip, multi-tier semiconductor package arrangements based upon single and double-sided flip chips. These arrangements are based on a stacked structure similar to FIGS. 6 and 7 noted above. U.S. Pat. No. 5,656,553 to Leas et al. discloses a fabrication method and resultant monolithic module comprising a plurality of stacked planar extending arrays of integrated circuit chips. The stacked die arrangement shown in the '553 patent uses edge connections to connect the upper die to the lower die. While this method of stacking multiple IC die addresses the case where two identical die are stacked, the method does not allow for routing flexibility, as the circuit routing is vertical from top to bottom and if there is any crossover, the chip package will not operate properly. [0004]
  • It is the object of the present invention to provide a multi-chip IC package having two or more similar semiconductor IC chips. [0005]
  • It is a further object of the invention to provide a multi-chip IC package having two or more similar IC chips that does not limit wirebonding to one side of the chip and does not require two complete IC fabrication steps. [0006]
  • It is still a further object of the invention to provide a multi-chip IC package that allows for flexibility in circuit routing. [0007]
    • SUMMARY OF THE INVENTION
  • The above objects have been met by a dual-die integrated circuit package having two chips (dies) which can be identically constructed from a wafer fabrication processing standpoint and are “flip chip” attached to each other using standard solder bumping and solder reflow technology. The first chip is aligned at a specified angle in relation to the second chip such that at least one of the bonding pads on the surface of each of the chips remain exposed for connection into a standard chip package. In one embodiment of the invention, two rectangular chips are aligned such that one chip is rotated at an angle of 90 degrees in relation to the other chip, such that the non-overlapping surfaces are exposed to enable chip package assembly. In another embodiment of the invention, the chips are aligned at an angle of less than 90 degrees such that at least a small portion, such as a corner, of each chip is exposed for chip package assembly. This embodiment would be preferable for the case when the two chips are of a square shape. In another embodiment of the invention, the two chips are of different sizes, as a larger chip is arranged on top of a smaller chip and is rotated at an angle such that the lower chip has at least some minimum area accessible for assembly. This ability to mount a larger IC chip over a smaller IC chip would be valuable to an IC manufacturer who controls the design of the smaller die, but purchases the larger die from another source. [0008]
  • The present invention allows for doubling the functionality or memory of a chip package while using the same package footprint as a single chip and using only one IC design. The integrated circuit package of the present invention allows for flexibility in wirebonding and routing and can be implemented in a single IC fabrication step. The present invention allows IC manufacturers to develop products with double the memory or functionality in a much faster time frame by providing the ability to use multiple identical chips in the same package without having to make significant design changes to the chips. [0009]
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 is a top view of a first embodiment of the dual-die integrated circuit package of the present invention, with the encapsulant material removed. [0010]
  • FIG. 2 is a perspective view of the two chips showing the interconnection between the two chips. [0011]
  • FIG. 3 is a top view of the dual-die integrated circuit package of FIG. 1 showing the two chips being attached to a leadframe. [0012]
  • FIG. 4 is a side view of the dual-die integrated circuit package of FIG. 1. [0013]
  • FIG. 5 is a top view of a second embodiment of the dual-die integrated circuit package of the present invention, with the encapsulant material removed. [0014]
  • FIG. 6 is a side view of a first stacked die IC package, as known in the prior art. [0015]
  • FIG. 7 is a side view of a second stacked die IC package, as known in the prior art. [0016]
  • FIG. 8 is a side view of a die-underneath IC package, as known in the prior art. [0017]
    • BEST MODE FOR CARRYING OUT THE INVENTION
  • With reference to FIG. 1, a first embodiment of the integrated circuit (IC) [0018] package 10 of the present invention is shown to include a top IC chip 16 and a bottom IC chip 14 which are aligned in a 90 degree relation with respect to each other. The chips 14, 16 are arranged on a flat die-attachment surface 12 of a leadframe 18. The leadframe 18 is made of a single piece of metal and extends from the die-attachment surface 12 to a plurality of outer leads 20 that are arranged around the perimeter of the IC package 10 and which extend downward for use in mounting the IC package 10 to an external printed circuit board.
  • With reference to FIG. 2, the [0019] top IC chip 16 is mechanically and electrically connected to the bottom IC chip 14 using a “flip chip” method with standard solder bumping and solder reflow technology. The connections between the chips 16 and 14 are made by solder bumps 22 on each of the chips which can be arranged in a diagonal or in an “x” pattern. The solder bumps 22 can be made as part of the original fabrication process or can be added afterwards using redistribution of electrical traces. FIG. 2 illustrates the case where the process of redistribution is used. On the original fabricated chip layer 23 of each of the chips 14 and 16, there are a plurality of bonding pads 49, shown in dashed lines, arranged around the perimeter of the chips. In FIG. 2, the bonding pads 49 are arranged on the bottom side 17 of the top chip 16 and on the top side 15 of the bottom chip 14. The bonding pads 49 are electrical terminals used for connecting the chips 14, 16 into a chip package. Each of the bonding pads 49 correspond to a particular circuit in the chip, such as power input, ground, memory address, etc. In order to carry out the redistribution process, first, a series of solder pads 22 are arranged in a diagonal pattern on the surface of the chip layer 23. If only a few connections are required, it is preferable that the solder bumps be made at the corners of the chips in order to minimize the number of solder bumps in the middle part of a chip, since that is where the memory array and other sensitive circuitry are located.
  • Next, [0020] routing traces 24 are then provided on the surface of each of the chips 14, 16 in order to connect the circuitry from the bonding pads 49 to the solder bumps 22. Circuits that are common to both chips 14, 16, such as ground, power input, and the clock signal for example, would be routed on each chip from the particular bonding pad corresponding to that circuit to a particular solder bump on each chip, the particular solder bumps on each chip being aligned together for interconnection. Circuits that are not common to each chip, such as chip enable for example, would not be routed to the solder bumps. The solder bumps 22 can also function as jumpers in order to connect circuits on the bottom chip 14 with circuits on the top chip 16 when the two chips are attached. Other routing traces may be added on the surface of the chip in order to connect the solder bumps with particular bonding pads which will be used for connecting the chips into the chip package. Then, a new passivation layer 21 is provided over the surfaces 15, 17 of the chips 14, 16 and the solder bumps 22 are brought through the passivation layer 21 to be exposed for interconnection. Some of the wire bonding pads 49, are also brought through the passivation layer 21, and will constitute the exposed bonding pads 29 used for connection of the chip into the chip package.
  • The two [0021] chips 14, 16 are then aligned at a 90 degree angle such that the solder bumps 22 are lined up for interconnection when the top chip 16 is flipped over on top of the bottom chip 14, as shown by the arrow 11. Generally, it is usually preferable to interconnect the two chips 14, 16 before placing the chips on the die-attachment surface of the chip package. This is because the melting temperature needed to reflow the solder bumps between the chips is generally higher than the temperature needed to attach the chips to the die-attachment surface. Therefore, if the bottom chip were attached to the die-attachment surface first, that attachment might become compromised when the higher temperature required to attach the top chip to the bottom chip is applied to the package. Other methods of connecting the two chips together can include the use of anisotropic (“Z-axis”) epoxy or other conductive solder metalizations.
  • With reference to FIG. 3, the [0022] bottom chip 14 of the attached chips is secured to the die-attachment surface 12 of the leadframe by an epoxy material. Because the two rectangular IC chips 14 and 16 are aligned at a 90 degree angle with respect to each other, the exposed bonding pads 29 on the bottom chip 14 are accessible for wirebond attachment into the chip package 10. Wire bonding leads 26 are used to attach the exposed bonding pads 29 to the inner leads 19 of the leadframe. The inner leads 19 extend outward to form the outer leads 20 which are used to provide connection to other external circuits which provide the power and other input and output signals to the chip package 10.
  • With reference to FIG. 4, the die-[0023] attachment surface 12 of the leadframe 18 supports the bottom IC chip 14 which is wirebonded 26 to the leadframe 18 and leads 20. The top IC chip 16 is connected by the solder bumps 22 to the bottom IC chip 14. Because the chips are rotated 90 degrees with respect to one another the portion on either end of the bottom IC chip is exposed for connection of the wirebond leads 26. An encapsulant material 28 is then used to cover the top of the IC package 10, including the two chips 14, 16 and the top of the die attachment surface 12, such that the leads 20 of the leadframe 18 remain at least partially exposed. In FIG. 4, the encapsulant material 28 has been cut away so that the interior of the IC package 10 can be viewed, but in the production of the chip package the encapsulant material 28 would completely cover the chips 14, 16. The encapsulant material 28 is preferably an epoxy overcoat or plastic molding.
  • With reference to FIG. 5, another embodiment of the present invention is shown. The [0024] IC chip package 30 of the second embodiment shows the top IC chip 36 being aligned with the bottom IC chip 34 at an angle of less than 90 degrees. This configuration is useful for IC chips that are square, but can also be used for rectangular chips. By aligning the top IC chip 36 at an offset angle from the bottom IC chip 34, an area 38 on the bottom chip 34 is exposed for wirebonding of the chip 34 to the leads 40.
  • The present invention can also be implemented with two chips of differing sizes. In another embodiment similar to that shown in FIG. 5, the [0025] top IC chip 36 would be larger than the bottom IC chip. Because the top IC chip 36 is rotated in relation to the bottom IC chip 34, even though the larger IC chip 36 is on top, the bottom chip 34 still has an area 38 exposed to allow accessibility for wirebonding. This would be valuable to a manufacturer who controls the design of the smaller IC chip but purchases the larger IC chip from a second source.
  • Although the dual-die IC package of the present invention has been described above in terms of being a PLCC (Plastic Leadless Chip Carrier) type of package, the dual-die IC chip package of the present invention can also be implemented with other types of package designs known in the art, such as ball grid arrays which use solder bumps on the bottom of the package rather than leads in order to connect the chip package to a printed circuit board. In the case of a ball grid array package and other types of package designs, the method of constructing the chip package is the same as described above, except for the particular manner in which the electrical connections are made between the chip package and an external circuit. The dual-die IC package of the present invention can also be a thin package type, such as a flat pack, or small outline IC (SOIC), by using the same construction techniques described above. [0026]

Claims (22)

1. A dual-die integrated circuit package comprising:
a flat die-attachment surface having a plurality of external electrical contacts for connecting the package to external circuits,
a first IC chip having a first surface and a second surface, and having a plurality of bonding pads on the first surface, the second surface being mounted on the die-attachment surface,
a second IC chip having a first surface and a second surface, and being mechanically and electrically connected by its second surface to the first surface of the first IC chip, wherein the second IC chip is aligned at a specified angle in relation to the first IC chip in a covering relation, with bonding pads on the first surface of the first IC chip remaining uncovered and electrically connected to the external electrical contacts of the die-attachment surface, and
an encapsulant material enclosing the first and second IC chip and covering a portion of the die-attachment surface such that the plurality of electrical contacts remain at least partially uncovered.
2. The integrated circuit package of
claim 1
, wherein the first and second IC chips have identical wafer fabrication constructions.
3. The integrated circuit package of
claim 1
, wherein the first and second IC chips have a rectangular shape.
4. The integrated circuit package of
claim 3
, wherein the specified angle of alignment is 90 degrees.
5. The integrated circuit package of
claim 1
, wherein the specified angle of alignment is less than 90 degrees.
6. The integrated circuit package of
claim 1
, wherein the second surface of the second IC chip and the first surface of the first IC chip include a series of solder bumps to enable electrical and mechanical connection between the second IC chip and the first IC chip.
7. The integrated circuit package of
claim 1
, wherein the die-attachment surface is a part of a leadframe, with a plurality of leads being disposed on a perimeter of the die-attachment surface.
8. The integrated circuit package of
claim 7
, wherein the plurality of leads are electrically connected to the first and second IC chips by wirebond connection between the leads and the plurality of bonding pads on the first surface of the first IC chip.
9. The integrated circuit package of
claim 1
, wherein the first IC chip is mounted to the die-attachment surface by epoxy.
10. The integrated circuit package of
claim 1
, wherein the second IC chip is larger than the first IC chip and is mounted on top of the first IC chip.
11. The integrated circuit package of
claim 1
, wherein the die-attachment surface is a part of a ball grid array type structure and includes a series of solder bumps on a bottom surface of the chip package.
12. The integrated circuit package of
claim 6
, wherein the series of solder bumps are arranged in a diagonal pattern.
13. The integrated circuit package of
claim 6
, wherein the series of solder bumps are arranged in a “X-shaped” pattern.
14. A dual-die integrated circuit package comprising:
a leadframe having a flat die-attachment surface with a plurality of leads disposed on a perimeter thereof,
a pair of IC chips, each having a first surface and a second surface, a first IC chip of the pair of IC chips having a plurality of bonding pads on the first surface and being mounted on its second surface to the flat die-attachment surface of the leadframe, and a second IC chip of the pair of IC chips being mounted on its second surface to the first surface of the first IC chip, wherein the second surface of the second IC chip and the first surface of the first IC chip includes a series of solder bumps, the first and second IC chips being electrically and mechanically coupled by solder bumping and reflow of the solder bumps, wherein the second IC chip is aligned at a specified angle in relation to the first IC chip, with at least one of the plurality bonding pads on the first surface of the first IC chip remaining uncovered,
a plurality of wirebond leads electrically and mechanically coupling the plurality of leads and the plurality of bonding pads on the first surface of the first IC chip, and
an encapsulant material enclosing the first and second IC chips and covering a portion of the die-attachment surface such that the plurality of leads of the leadframe remain at least partially uncovered.
15. The integrated circuit package of
claim 14
, wherein the first IC chip and the second IC chip have identical wafer fabrication constructions.
16. The integrated circuit package of
claim 14
, wherein the first IC chip and the second IC chip have a rectangular shape and wherein the specified angle of alignment is 90 degrees.
17. The integrated circuit package of
claim 14
, wherein the specified angle of alignment is less than 90 degrees.
18. The integrated circuit package of
claim 14
, wherein the second IC chip is larger than the first IC chip and is mounted on top of the second IC chip.
19. A dual-die integrated circuit package comprising:
a flat die-attachment surface with a plurality of electrical contacts disposed thereon,
a first IC chip having a first surface and a second surface wherein a plurality of bonding pads are arranged on the first surface and wherein the second surface is mounted onto the die-attachment surface,
a second IC chip having a first surface and a second surface and having an identical wafer fabrication construction as that of the first IC chip,
wherein the second surface of the second IC chip and the first surface of the first IC chip include a series of solder bumps, the series of solder bumps being connected by solder bumping and reflow to electrically and mechanically couple the first IC chip and the second IC chip, wherein the second IC chip is aligned at a specified angle in relation to the first IC chip leaving a plurality of bonding pads on the first surface of the first IC chip uncovered,
means for electrically coupling the plurality of electrical contacts on the die-attachment surface and the plurality of bonding pads on the first surface of the first IC chip, and
an encapsulant material enclosing the first and second IC chips and covering a portion of the die-attachment surface such that the plurality of electrical contacts remain at least partially exposed.
20. The integrated circuit package of
claim 20
, wherein the die-attachment surface constitutes a part of a leadframe, with a plurality of leads being disposed on a perimeter of the die-attachment surface.
21. A method of forming a dual-die integrated circuit package comprising:
arranging a plurality of solder bumps on a first surface of a first IC chip and on a first surface of a second IC chip, the first and second IC chips having a plurality of bonding traces arranged thereon,
arranging a series of routing traces on the first surfaces of the first and second IC chips, the routing traces interconnecting the solder bumps and the bonding pads,
adding a passivation layer over the first surfaces of each of the first and second chips, the solder bumps and the bonding pads remaining exposed through the passivation layer,
aligning the second chip at a specified angle in relation to the first chip,
connecting the second chip to the first chip through the solder reflow attachment of the solder bumps of each of the chips,
attaching the first chip to a flat die-attachment surface being in mechanical and electrical communication with a plurality of electrical contacts, and
covering the first and second chips and an inner part of the die-attachment surface with an encapsulant material.
22. The method of forming a dual-die integrated circuit package, as in
claim 21
, wherein the step of connecting the second chip to the first chip is carried out by using an anisotropic epoxy.
US09/458,264 1999-12-09 1999-12-09 Dual-die integrated circuit package Expired - Lifetime US6376914B2 (en)

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US09/458,264 US6376914B2 (en) 1999-12-09 1999-12-09 Dual-die integrated circuit package
CA002392975A CA2392975A1 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
JP2001543781A JP2003516637A (en) 1999-12-09 2000-10-23 Dual die integrated circuit package
PCT/US2000/041466 WO2001043193A2 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
CN00816866A CN1408125A (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
EP00986833A EP1238430A2 (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
KR1020027007245A KR20020055603A (en) 1999-12-09 2000-10-23 Dual-die integrated circuit package
TW089124874A TW472327B (en) 1999-12-09 2000-11-23 Dual-die integrated circuit package
MYPI20005650A MY135947A (en) 1999-12-09 2000-12-01 Dual-die integrated circuit package
NO20022736A NO20022736L (en) 1999-12-09 2002-06-07 Circuit enclosure with an integrated double chip

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