TWI847371B - Driving circuits - Google Patents

Abstract

A driving circuit is provided. The driving circuit includes a detection circuit, a control circuit, and a power device. The detection circuit is coupled between a first power terminal and a second power terminal and generates a detection voltage at the detection node according to a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor device having a back-to-back connected structure. The transistor device is coupled between a pad and a first node and controlled by the detection voltage. A driving voltage is generated at the first node. The power device is coupled between the pad and the second power terminal and controlled by the driving voltage. In response to an electrostatic discharge event occurring on the pad, the transistor device is turned on according to the detection voltage, and the power device is triggered by the driving voltage to provide a discharge path between the pad and the second power terminal.

Description

Drive circuit

The present invention relates to a driving circuit, and more particularly to a driving circuit with electrostatic discharge (ESD) protection.

With the development of semiconductor manufacturing processes for integrated circuits, the size of semiconductor components has been reduced to the sub-micron stage to improve the performance and computing speed of integrated circuits. However, the reduction in component size has caused some reliability issues, especially the integrated circuit's protection against electrostatic discharge (ESD). Therefore, it is important to provide a circuit that can effectively provide an ESD path. In particular, in high-voltage applications, the components used to control the ESD path may be damaged by the high voltage, resulting in the inability to effectively provide a discharge path when ESD occurs.

In view of this, the present invention proposes a driving circuit. The driving circuit includes a detection circuit, a control circuit, and a power element. The detection circuit is coupled between a first power terminal and a second power terminal, and generates a detection voltage at a detection node according to a first voltage of the first power terminal and a second voltage of the second power terminal. The control circuit includes a transistor element having a back-to-back connection structure. The transistor element is coupled between a bonding pad and a first node, and is controlled by the detection voltage. A driving voltage is generated at the first node. The power element is coupled between the bonding pad and the two power terminals, and is controlled by the driving voltage. When an electrostatic discharge event occurs on the bonding pad, the transistor element is turned on according to the detection voltage, and the power element is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power terminal.

1: Electronic circuit

10: Core circuit

11: Driving circuit

12:Joint pad

13: Detection circuit

14: Control circuit

15: Power components

16: Voltage tracking circuit

17: Transmission gate circuit

30~32,34~35: PMOS transistor

40:NMOS transistor

41:PMOS transistor

42: Inverter

50_1~50_N: PMOS transistor

60,61: Buck circuit

60_1~60_X,61_1~61_X: diode

130: Resistor

131:Capacitor

140,141:PMOS transistor

142: Transistor components

150:NMOS transistor

GND: Ground terminal

N10: Detection node

N11: Node

N12: Common source node

N30, N31, N33: nodes

N30A, N60A, N61A: Input node

N30B, N60B, N61B: output nodes

S10: Input signal

SW10, SW10B: Switching signal

T10, T11: power supply terminal

T30A, T31A, T32A, T34A, T35A, T36A: Gate

T30B, T31B, T32B, T34B, T35B, T36B: Drain

T30C, T31C, T32C, T34C, T35C, T36C: Source

T30D, T31D, T32D, T34A, T34D, T36D: Base

T40: Power supply

T40A, T41A: Gate

T40B, T41B: Drain

T40C, T41C: Source

T40D, T41D: Base

T140A, T141A, T150A: Gate

T140B, T141B, T150B: Drain

T140C, T141C, T150C: Source

T140D, T141D, T150D: Base

T160: Output terminal

T170, T171: Input terminal

T172: Output terminal

V10: Detect voltage

V11: driving voltage

V12: bias voltage

V16: Tracking voltage

V30: Control voltage

V60: Input voltage

VDD: operating voltage

FIG. 1 shows an electronic circuit having a driving circuit according to an embodiment of the present invention.

Figure 2A is a schematic diagram showing the operation of the electronic circuit in Figure 1 during normal operation.

Figure 2B is a schematic diagram showing the operation of the electronic circuit in Figure 1 when it encounters an electrostatic discharge event.

FIG. 3 shows a voltage tracking circuit of the driving circuit in FIG. 1 according to an embodiment of the present invention.

FIG. 4 shows the transmission gate circuit of the driving circuit in FIG. 1 according to an embodiment of the present invention.

FIG. 5 shows the detection circuit of the driving circuit in FIG. 1 according to an embodiment of the present invention.

FIG. 6 shows an electronic circuit with a driving circuit according to another embodiment of the present invention.

In order to make the above-mentioned purposes, features and advantages of the present invention more clearly understood, a preferred embodiment is given below, and a detailed description is given in conjunction with the attached drawings.

FIG. 1 shows an electronic circuit according to an embodiment of the present invention. Referring to FIG. 1, the electronic circuit 1 includes a core circuit 10 and a driver circuit 11. The driver circuit 11 includes a bonding pad 12, a detection circuit 13, a control circuit 14, a power element 15, a voltage tracking circuit 16, and a transmission gate circuit 17. The power element 15 is coupled between the bonding pad 12 and the power terminal T11. In this embodiment, the power element 15 serves as the output stage of the driver circuit 11, which is driven by a large current. The power element 15 can withstand a large current and therefore has a self-protection capability for electrostatic discharge. In this embodiment, the power element 15 is a large array device (LAD). For example, the power element 15 includes a plurality of parallel-connected N-type metal-oxide-semiconductor (NMOS) transistors. In FIG. 1 , an NMOS transistor 150 is used to represent an equivalent element of a plurality of parallel-connected NMOS transistors. The NMOS transistor 150 has four electrodes, including a gate, a drain, a source, and a bulk. In this embodiment, the NMOS transistor 150 is implemented as a laterally-diffused N-type metal-oxide semiconductor (LDNMOS) transistor. Referring to FIG. 1 , the gate T150A of the NMOS transistor 150 is coupled to the node N11, the drain T150B is coupled to the bonding pad 12, and the source T150C and the base T150D are coupled to the power terminal T11. When an electrostatic discharge event occurs on the bonding pad 12, the NMOS transistor 150 is triggered by the driving voltage V11 generated on the node N11 to provide a discharge path between the bonding pad 12 and the power terminal T11. In this embodiment, the power terminal T11 is a ground terminal (GND), and its voltage is, for example, 0 volts (Volt, V).

The detection circuit 13 is coupled between the power terminal T10 and the power terminal T11, and generates a detection voltage V10 according to the voltage of the power terminal T10 and the voltage of the power terminal T11. Referring to FIG. 1, it includes a resistor 130 and a capacitor 131. The resistor 130 is coupled between the power terminal T10 and the detection node N10. The capacitor 131 is coupled between the detection node N10 and the power terminal T11. The detection voltage V10 is generated at the detection node N10.

The control circuit 14 includes a transistor element 142 having a back-to-back connection structure. The transistor element 142 is coupled between the bonding pad 12 and the node N11, and is controlled by the detection voltage V10. The transistor element 142 has a first electrode terminal coupled to the bonding pad 12, a second electrode terminal coupled to the node N11, and a control electrode terminal coupled to the detection node N10 to receive the detection voltage V10. Referring to FIG. 1, the transistor element 142 is composed of P-type Metal-Oxide-Semiconductor (PMOS) transistors 140 and 141. The PMOS transistors 140 and 141 each have four electrode terminals, including a gate, a drain, a source, and a base. In this embodiment, the PMOS transistors 140 and 141 are implemented by laterally-diffused P-type metal-oxide semiconductor (LDPMOS) transistors. The gate T140A of the PMOS transistor 140 is coupled to the control electrode terminal of the transistor element 142 (i.e., coupled to the detection node N10), the drain T140B thereof is coupled to the first electrode terminal of the transistor element 142 (i.e., coupled to the bonding pad 12), and the source T140C and the base T140D thereof are coupled to the common source node N12. The gate T141A of the PMOS transistor 141 is coupled to the control electrode end of the transistor element 142 (i.e., coupled to the detection node N10), the drain T141B is coupled to the second electrode end of the transistor element 142 (i.e., coupled to the node N11), and the source T141C and the base T141D are coupled to the common source node N12. According to the above connection relationship, the connection relationship between the PMOS transistors 140 and 141 forms a back-to-back connection structure.

As shown in FIG. 1 , the voltage tracking circuit 16 is coupled to the power terminal T10 and the bonding pad 12 and is controlled by the detection voltage V10. The voltage tracking circuit 16 is used to track one of the voltage of the power terminal T10 and the voltage of the bonding pad 12 to generate a tracking voltage V16, and applies the tracking voltage V16 to the common source node N12 of the transistor element 142 as a bias voltage V12. Specifically, the voltage tracking circuit 16 tracks the voltage of the power supply terminal T10 and the voltage of the bonding pad 12, whichever has a higher level, and makes the tracking voltage V16 (as the bias voltage V12) equal to the voltage having the higher level.

The transmission gate circuit 17 includes input terminals T170 and T171 and an output terminal T171. The input terminals T170 and T171 are coupled to the core circuit 10, and the output terminal T172 is coupled to the node N11. When the electronic circuit 1 operates normally, the core circuit 10 provides an input signal S10 to the input terminal T170 and provides a switching signal SW10 to the input terminal T171. The transmission gate circuit 17 is controlled by the switching signal SW10 to transmit the input signal S10 from the input terminal T170 to the output terminal T172. The input signal S10 is provided to the node N11, that is, the level of the driving voltage V11 generated on the node N11 changes with the voltage level of the input signal S10. In this embodiment, the voltage levels of the input signal S10 and the switching signal SW10 are in the range of 0V~5V.

The detailed operation of the drive circuit 11 will be described in Figures 2A and 2B and below.

According to the above, PMOS transistors 140 and 141 and NMOS transistor 150 are LDMOS transistors. The gate-source withstand voltage of the LDMOS transistor is 5V, and the gate-drain withstand voltage of the LDMOS transistor is 12V, 24V, or 40V. In the following embodiments, transistors 140, 141, and 150 are described as LDMOS transistors with a gate-source withstand voltage of 5V and a gate-drain withstand voltage of 40V.

Referring to FIG. 2A , when the electronic circuit 1 operates normally (i.e., in the operating mode), the power terminal T10 receives the operating voltage VDD, the core circuit 10 provides the input signal S10 and the switching signal SW10 to the transmission gate circuit 17, and the voltage of the bonding pad 12 varies within a range. In this embodiment, the operating voltage VDD is, for example, 44V, and the voltage of the bonding pad 12 is in the range of 0V to 44V, but the present invention is not limited thereto, and those skilled in the art can determine it according to the actual circuit application range. The operating voltage VDD charges the capacitor 131 through the resistor 130, so that the detection voltage V10 on the detection node N10 has a high level, such as 44V. According to the above, the voltage tracking circuit 16 tracks the voltage of the power terminal T10 and the voltage of the bonding pad 12, whichever has a higher level. Since the operating voltage VDD (44V) received by the power terminal T10 is greater than or equal to the voltage of the bonding pad 12 (0V~44V), the voltage tracking circuit 16 tracks the operating voltage VDD and generates a tracking voltage V16 of 44V. The tracking voltage V16 of 44V is transmitted to the common source node N12 as a bias voltage V12 (44V). Since the detection voltage V10 is 44V and the common source node N12 is at 44V, the PMOS transistors 140 and 141 are turned off (OFF). The transmission gate circuit 17 performs a signal transmission operation according to the switching signal SW10. In detail, the transmission gate circuit 17 transmits the input signal S10 to the output terminal T172 according to the switching signal SW10, and the input signal S10 is then provided to the node N11. At this time, since the PMOS transistors 140 and 141 are turned off, the level of the driving voltage V11 on the node N11 changes with the voltage level (0V~5V) of the input signal S10. The NMOS transistor 150 operates according to the driving voltage V11 and the voltage of the bonding pad 12 to be in the on state or the off state.

According to the above, the PMOS transistors 140 and 141 constitute a transistor element 142. For the transistor element 142, the terminal coupled to the bonding pad 12 is the drain T140B of the PMOS transistor 140, and the terminal coupled to the node N11 is the drain T141B of the PMOS transistor 141. Therefore, the above two terminals of the transistor element 142 can withstand high voltage. For example, when the NMOS transistor 150 is turned on according to the driving voltage V11 and the voltage of the bonding pad 12, the drain T140B of the PMOS transistor 140 is coupled to the power terminal T11 and is at a low level, such as 0V. In this case, the gate-drain voltage difference of the PMOS transistor 140 is approximately equal to 44V (44V-0V=44V), which does not exceed the gate-drain withstand voltage of 44V. When the driving voltage V11 is 0V as the voltage level of the input signal S10, the gate-drain voltage difference of the PMOS transistor 141 is approximately equal to 44V (44V-0V=44V), which does not exceed the gate-drain withstand voltage of 44V. According to the above, the transistor element 142 is coupled to the bonding pad 12 and the node N11 through the drains T140B and T141B of the PMOS transistors 140 and 141, respectively, so the transistor element 142 can withstand high voltage.

Referring to FIG. 2B , when the electronic circuit 1 is not in the operation mode, the operation voltage VDD is not provided to the power terminal T10, and the core circuit 10 does not provide the input signal S10 and the switching signal SW10. At this time, the power terminal T10 and the input terminals T170 and T171 and the output terminal T172 of the transmission gate circuit 17 are in a floating state. The transmission gate circuit 17 does not perform the signal transmission operation. When an electrostatic discharge event occurs on the bonding pad 12 of the electronic circuit 1, the voltage level of the bonding pad 12 increases instantaneously. Based on the characteristics of the capacitor 131, the detection voltage V10 of the detection node N10 is the same as the voltage of the power terminal T11, that is, the detection voltage V10 is 0V. The voltage of the power terminal T10 in a floating state is less than the high voltage of the bonding pad 12, so the voltage tracking circuit 16 tracks the high voltage of the bonding pad 12, and the generated tracking voltage V16 is equal to the high voltage of the bonding pad 12. The tracking voltage V16 is transmitted to the common source node N12 as a bias voltage V12. Since the detection voltage V10 is 0V and the common source node N12 has a high voltage, the PMOS transistors 140 and 141 are turned on. The driving voltage V11 on the node N11 increases as the voltage on the bonding pad 12 changes to turn on the NMOS transistor 15. The turned-on NMOS transistor 15 provides a discharge path P20. The electrostatic charge on the bonding pad 12 can be conducted to the power terminal T11 via the NMOS transistor 15 and along the discharge path P20.

According to the above, the two terminals of the transistor element 142 for coupling the bonding pad 12 and the node N11 are the drains T140B and T141B of the PMOS transistors 140 and 141, respectively, so the transistor element 142 can withstand high voltage. In the operation mode of the electronic circuit 1, the transistor element 142 is not easily damaged by the driving voltage V11 and the voltage of the bonding pad 12. In addition, in the operation mode of the electronic circuit 1, the transistor element 142 is in the off state, so the setting of the transistor element 142 will not affect the normal operation of the power element 15. When an electrostatic discharge event occurs on the bonding pad 12 of the electronic circuit 1, the transistor element 142 controls the power element 15 to conduct to provide a discharge path, so that the electrostatic charge is conducted to the power terminal T11 through the power element 15.

FIG. 3 shows a voltage tracking circuit 16 of the driving circuit 11. The voltage tracking circuit 16 includes PMOS transistors 30-32 and a buck circuit 33. In this embodiment, the PMOS transistors 30-32 are implemented by LDPMOS transistors. The PMOS transistor 30 includes four electrode terminals T30A-T30D, namely a gate T30A, a drain T30B, a source T30C, and a base T30D. The drain T30B is coupled to the power terminal T10, and its source T30C and base T30D are coupled to the output terminal T160. The buck circuit 33 has an input node N30A and an output node N30B. The input node N30A is coupled to the power terminal T10, and the output node N30B is coupled to the node N33 and the gate T30A of the PMOS transistor 30. Referring to FIG. 3 , the output node N30B and the node N33 can be regarded as the same node. The PMOS transistor 31 includes four electrode terminals T31A~T31D, which are the gate T31A, the drain T31B, the source T31 and the base T31D. The gate T31A is coupled to the node N10, its drain T31B is coupled to the bonding pad 12, and its source T31C and the base T31D are coupled to the output terminal T160. The PMOS transistor 32 includes four electrode terminals T32A~T32D, namely a gate T32A, a drain T32B, a source T32C, and a base T32D. The gate T32A is coupled to the power terminal T10, the drain T32B is coupled to the bonding pad 12, and the source T32C and the base T32D are coupled to the node N33.

The buck circuit 33 includes a plurality of buck elements connected in series between the input node N30A and the output node N30B to implement the buck operation. The actual number of buck elements can be adjusted according to the actual demand for regulating the voltage, and the present invention is not limited thereto. Referring to FIG. 3 , in this embodiment, the buck circuit 33 includes three PMOS transistors 34 to 36 connected in series between the input node N30A and the output node N30B as buck elements. The PMOS transistors 34 to 36 are implemented by LDPMOS transistors. The PMOS transistor 34 has four electrode terminals T34~T34D, which are respectively a gate T34A, a drain T34B, a source T34C, and a base T34D. The drain T34B is coupled to the input node N30A, and the source T34C and the base T34D are coupled to the node N31. The PMOS transistor 35 has four electrode terminals T35A~T35D, which are respectively a gate T35A, a drain T35B, a source T35C, and a base T35D. The drain T35B is coupled to the node N31, and the source T35C and the base T35D are coupled to the node N32. The PMOS transistor 36 has four electrode terminals T36A~T36D, which are respectively a gate T36A, a drain T36B, a source T36C, and a base T36D. The drain T36B is coupled to the node N32, and the source T36C and the base T36D are coupled to the output node N30B and the node N33. The gates T34A, T35A, and T36A of the PMOS transistors 34~36 are all coupled to the output terminal T160.

In this embodiment, transistors 30-32 and 34-36 are described by taking LDMOS transistors with a gate-source withstand voltage of 5V and a gate-drain withstand voltage of 40V as an example. The operation of the voltage tracking circuit 16 is described as follows.

When the electronic circuit 1 operates normally (i.e., in the operating mode), the voltage tracking circuit 16 receives the operating voltage VDD (44V) through the power terminal T10, the detection voltage V10 of the detection node N10 is 44V according to the operating voltage VDD, and the voltage of the bonding pad 12 is in the range of 0V to 44V. Therefore, the PMOS transistors 31 and 32 are turned off. At this time, the PMOS transistors 34 to 36 are in the off state. Since the PMOS transistors 34 to 36 have parasitic diodes, the turned-off PMOS transistors 34 to 36 act as forward diodes. Each of the PMOS transistors 34 to 36 has a cross voltage of 0.7V between the respective drain and source. Therefore, the voltage difference between the input node N30A and the output node N30B is 2.1V (0.7Vx3=2.1V). The voltage difference (2.1V) between the input node N30A and the output node N30B is used as the regulation voltage provided by the buck circuit 33. The control voltage V30 on the output node N30B is 41.9V (44V-2.1V=41.9V), thereby realizing the buck operation, that is, realizing the use of the regulation voltage to reduce the voltage VDD to generate the control voltage V30 at the output node N30B. At this time, the voltage of the gate T30A of the PMOS transistor 30 is equal to the control voltage V30. Since the control voltage V30 is less than the operating voltage VDD, the PMOS transistor 30 is turned on to provide a current path between the power terminal T10 and the output terminal T160. Through this current path, the tracking voltage V16 on the output terminal T160 increases along with the operating voltage VDD and eventually becomes equal to the operating voltage VDD (V16=VDD=44V), thus realizing that the voltage tracking circuit 16 tracks a voltage with a higher level (i.e., the operating voltage VDD on the power terminal T10).

In the operation mode, since the tracking voltage V16 of the output terminal T160 follows the voltage of the power terminal T10 and the voltage of the bonding pad 12, whichever has a higher level, the gates T34A, T35A, and T36A of the PMOS transistors 34-36 have a higher voltage, so that the PMOS transistors 34-36 can stably maintain the off state.

When the electronic circuit 1 is not in the operation mode, the power terminal T10 does not receive any operation voltage and is in a floating state, and the detection voltage V10 is 0 V. When an electrostatic discharge event occurs on the bonding pad 12, the voltage level of the bonding pad 12 increases instantaneously. At this time, according to the detection voltage V10 (0 V) of the detection node N10, the PMOS transistor 31 is turned on to provide a current path between the bonding pad 12 and the output terminal T160. Through this current path, the tracking voltage V16 on the output terminal T160 increases along with the voltage of the bonding pad 12 and eventually becomes equal to the voltage of the bonding pad 12, thereby realizing that the voltage tracking circuit 16 tracks a voltage with a higher level (i.e., the voltage of the bonding pad 12).

In addition, when an electrostatic discharge event occurs on the bonding pad 12, since the power terminal T10 is in a floating state and the voltage level of the bonding pad 12 increases instantaneously, the PMOS transistor 32 is turned on, so that the control voltage V30 is equal to the voltage of the bonding pad 12. At this time, although the buck circuit 33 still performs the above-mentioned buck operation, since the control voltage V30 changes to a high level along with the voltage of the bonding pad 12, the PMOS transistor 30 is in a turned-off state in this case. Based on the turned-off state of the PMOS transistor 30, even if the tracking voltage V16 is greater than the voltage of the power terminal T10, no leakage current will be generated from the output terminal T160 to the power terminal T10. In this way, the tracking voltage V16 can be stably maintained equal to the voltage of the bonding pad 12.

According to the above, when the electronic circuit 1 is operating normally, the power terminal T10 receives an operating voltage VDD of up to 44V, and the voltage of the bonding pad 12 is in the range of 0V to 44V; when the electronic circuit 1 is not in the operating mode, an electrostatic discharge event may occur on the bonding pad 12, causing the voltage level of the bonding pad 12 to increase instantly. In FIG. 3 , the drain T30B of the transistor 30 is coupled to the power terminal T10, and the drain T31B of the transistor 31 and the drain T32B of the transistor 32 are coupled to the bonding pad 12. In the circuit structure of Figure 3, since the gate-drain withstand voltage of transistors 30, 31, and 32 is approximately 40V, the large voltage difference between the power terminal T10 and the bonding pad 12 will not cause damage to transistors 31 and 32.

FIG. 4 shows the transmission gate circuit 17 of the driving circuit 11. In order to clearly explain the structure and operation of the transmission gate circuit 17, FIG. 4 also shows the core circuit 10. Referring to FIG. 4, the transmission gate circuit 17 includes an NMOS transistor 40, a PMOS transistor 41, and an inverter 42. In this embodiment, the operating voltage level of the input signal S10 and the switching signal SW10 provided by the core circuit 10 is within the range of 0V~5V, and the NMOS transistor 40 and the PMOS transistor 41 are implemented with MOS transistors whose gate-drain withstand voltage does not exceed 5V.

Referring to FIG. 4 , the NMOS transistor 40 includes four electrode terminals T40A-T40D, namely a gate T40A, a drain T40B, a source T40C, and a base T40D. The gate T40A is coupled to the input terminal T171 of the transmission gate circuit 17, the drain T40B is coupled to the input terminal T170 of the transmission gate circuit 17, the source T40C is coupled to the output terminal T172 of the transmission gate circuit 17, and the base T40D is coupled to the ground terminal GND. The input terminal of the inverter 42 is coupled to the input terminal T171. The PMOS transistor 41 includes four electrode terminals T41A~T41D, namely a gate T41A, a drain T41B, a source T41C, and a base T41D. The gate T41A is coupled to the output terminal of the inverter 42, the drain T41B is coupled to the input terminal T170, the source T41C is coupled to the output terminal T172, and the base T41D is coupled to the power terminal T40. In this embodiment, the power terminal T40 can receive an operating voltage in the range of 0V~5V.

The operation of the transmission gate circuit 17 is described as follows.

When the electronic circuit 1 operates normally (i.e., in the operating mode), the core circuit 10 provides the input signal S10 and the switching signal SW10 to the input terminals T170 and T171, respectively, and the power terminal T40 receives an operating voltage. In the operating mode, the switching signal SW10 is at a high voltage level (e.g., a 5V level), and the core circuit 10 sets the input signal S10 to a voltage level in the range of 0V to 5V according to the operation of the electronic circuit 1. The inverter 42 receives the switching signal SW10 through the input terminal T171, and generates a switching signal SW10B at a low voltage level (e.g., a 0V level) after inverting it. The gate T40A of the NMOS transistor 40 receives the high voltage level switching signal SW10 through the input terminal T171, and the gate T41A of the PMOS transistor 41 receives the low voltage level switching signal SW10B from the inverter 42. Therefore, both the NMOS transistor 40 and the NMOS transistor 41 are in the on state. The input signal S10 provided by the core circuit 10 is transmitted to the output terminal T172 through the turned-on NMOS transistor 40 and the NMOS transistor 41, thereby realizing the signal transmission operation of the transmission gate circuit 17. The input signal S10 is then transmitted to the node N10. In this way, the level of the driving voltage V11 on the node N11 changes with the voltage level of the input signal S10. The NMOS transistor 150 operates according to the driving voltage V11 and the voltage of the bonding pad 12.

When the electronic circuit 1 is not in the operating mode, the core circuit 10 does not provide the input signal S10 and the switching signal SW10, and the power terminal T40 does not receive any operating voltage. At this time, the power terminal T40, the input terminals T170 and T171, and the output terminal T172 of the transmission gate circuit 17 are in a floating state. Therefore, the transmission gate circuit 17 does not perform a signal transmission operation. In other words, the signal or voltage on the input terminal T170 of the transmission gate circuit 17 will not affect the level of the driving voltage V11 on the node N11.

FIG. 5 shows the detection circuit 13 of the drive circuit 11. The capacitor 131 of the detection circuit 13 is implemented by a plurality of transistors connected in series. As shown in FIG. 5, the capacitor 131 includes a plurality of PMOS transistors 50_1 to 50_N, wherein N is an integer greater than or equal to 2. In this embodiment, the PMOS transistors 50_1 to 50_N can be implemented by MOS transistors with a gate-drain withstand voltage of 5V. In an example where the NMOS transistors 140, 141, and 150 are LDMOS transistors and the operating voltage VDD is 44V, for example, N can be equal to 9, that is, the capacitor 131 includes 9 PMOS transistors 50_1 to 50_9, but the present invention is not limited thereto.

Referring to FIG. 5, PMOS transistors 50_1~50_N are sequentially connected in series between the detection node N10 and the power terminal T11. For each of the PMOS transistors 50_1~50_N, its drain, source, and base are coupled to each other, so that the PMOS transistor is equivalent to a capacitor. The drain, source, and base of the PMOS transistor 50_1 are coupled to the detection node N10. The drain, source, and base of each of the PMOS transistors 50_2~50_N are coupled to the gate of the previous PMOS transistor. The gate of the PMOS transistor 50_N is coupled to the power terminal T11.

FIG. 6 shows an electronic circuit with a driving circuit according to another embodiment of the present invention. Referring to FIG. 6, it further includes step-down circuits 60 and 61. Step-down circuit 60 is coupled between bonding pad 12 and transistor element 142, and provides a regulated voltage. Step-down circuit 60 uses the regulated voltage to reduce the voltage of bonding pad 12 to generate input voltage V60, and provides input voltage V60 to transistor element 142.

The buck circuit 60 includes an input node N60A, an output node N60B, and a plurality of buck elements connected in series between the input node N60A and the output node N60B. The input node N60A is coupled to the bonding pad 12, and the output node N60B is coupled to the drain T140B of the PMOS transistor 140 of the transistor element 142. In this embodiment, the buck circuit 60 includes diodes 60_1 to 60_X connected in series between the input node N60A and the output node N60B in sequence as buck elements, where X is an integer greater than or equal to 1. The actual number of buck elements can be adjusted according to the actual demand for regulating voltage. The anode of diode 60_1 is coupled to input node N60A. The anode of each of diodes 60_2 to 60_X is coupled to the cathode of the previous diode. The cathode of diode 60_X is coupled to output node N60B.

Each of the diodes 60_1~60_X provides a 0.7V voltage across its anode and cathode. Therefore, the voltage difference between the input node N60A and the output node N60B of the buck circuit 60 is equal to 0.7×X. The voltage difference between the input node N60A and the output node N60B is used as the regulated voltage provided by the buck circuit 60. The buck circuit 60 uses this regulated voltage to reduce the voltage of the bonding pad 12 to generate the input voltage V60.

According to the above, the buck circuit 60 is coupled between the bonding pad 12 and the transistor element 142, and it can perform a buck operation. When there is a large voltage on the bonding pad 12, the input voltage V60 generated based on this buck operation can be smaller than the voltage of the bonding pad 12, thereby preventing the transistor element 142 from being damaged by the large voltage of the bonding pad 12.

The buck circuit 61 is coupled between the voltage tracking circuit 16 and the common source node N12, and provides a regulated voltage. In the embodiment of FIG. 1, the tracking voltage V16 is applied to the common source node N12 as the bias voltage V12. In other words, the bias voltage V12 is equal to the tracking voltage V16. In this embodiment, the buck circuit 61 reduces the tracking voltage V16 by the regulated voltage to generate the bias voltage V12, and provides the bias voltage V12 to the common source node N12.

The buck circuit 61 includes an input node N61A, an output node N61B, and a plurality of buck elements connected in series between the input node N61A and the output node N61B. The input node N61A is coupled to the voltage tracking circuit 16 to receive the tracking voltage V16, and the output node N61B is coupled to the common source node N12. In this embodiment, the buck circuit 61 includes diodes 61_1 to 61_Y connected in series between the input node N61A and the output node N61B in sequence as buck elements, wherein Y is an integer greater than or equal to 1. The actual number of buck elements can be adjusted according to the actual demand for regulating voltage. The anode of diode 61_1 is coupled to input node N61A. The anode of each of diodes 61_2 to 61_Y is coupled to the cathode of the previous diode. The cathode of diode 61_Y is coupled to output node N61B.

Each of the diodes 61_1~61_Y provides a 0.7V voltage across its anode and cathode. Therefore, the voltage difference between the input node N61A and the output node N61B of the buck circuit 61 is equal to 0.7×Y. The voltage difference between the input node N61A and the output node N61B serves as the regulated voltage provided by the buck circuit 61. The buck circuit 61 uses this regulated voltage to reduce the tracking voltage V16 to generate the bias voltage V12.

According to the above, the buck circuit 61 is coupled between the voltage tracking circuit 16 and the common source node N12, and it can perform a buck operation. When the tracking voltage V16 generated by the tracking operation of the voltage tracking circuit 16 is a large voltage, the bias voltage V12 generated based on this buck operation can be smaller than the tracking voltage V16, so as to prevent the common source node N12 of the transistor element 142 from being damaged due to the large voltage.

In this embodiment, the number of diodes 60_1 to 60_X of the step-down circuit 60 is equal to the number of diodes 61_1 to 61_Y of the step-down circuit 61, that is, X=Y. In other embodiments, according to the requirements of the electronic circuit 1, the number of diodes 60_1 to 60_X is not equal to the number of diodes 61_1 to 61_Y. For example, the number of diodes 60_1 to 60_X is greater than the number of diodes 61_1 to 61_Y, that is, X>Y.

Although the present invention has been disclosed as above with the preferred embodiment, it is not intended to limit the present invention. Anyone familiar with this technology can make changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be subject to the scope of the patent application attached hereto.

1: Electronic circuit 10: Core circuit 11: Driver circuit 12: Bonding pad 13: Detection circuit 14: Control circuit 15: Power element 16: Voltage tracking circuit 17: Transmission gate circuit 130: Resistor 131: Capacitor 140, 141: PMOS transistor 142: Transistor element 150: NMOS transistor GND: Ground terminal N10: Detection node N11: Node N12: Common source node S10: Input signal SW10: Switching signal T10, T11: Power terminal T140A, T141A, T150A: Gate T140B, T141B, T150B: Drain T140C, T141C, T150C: Source T140D, T141D, T150D: Base T160: Output T170, T171: Input T172: Output V10: Detection voltage V11: Drive voltage V12: Bias voltage V16: Tracking voltage

Claims (20)

A driving circuit includes: a detection circuit coupled between a first power terminal and a second power terminal, and generating a detection voltage at a detection node according to a first voltage of the first power terminal and a second voltage of the second power terminal; a control circuit including a transistor element having a back-to-back connection structure, wherein the transistor element is coupled between a bonding pad and a first node and is controlled by the detection voltage, wherein a driving voltage is generated at The first node; and a power element coupled between the bonding pad and the second power supply terminal and controlled by the driving voltage; wherein, when an electrostatic discharge event occurs on the bonding pad, the transistor element is turned on according to the detection voltage, and the power element is triggered by the driving voltage to provide a discharge path between the bonding pad and the second power supply terminal; wherein, the transistor element having the back-to-back connection structure includes two P-type transistors connected in series. The driving circuit of claim 1, wherein the P-type transistors connected in series include: a first P-type transistor having a gate coupled to the detection node, a drain coupled to the bonding pad, and a source; and a second P-type transistor having a gate coupled to the detection node, a source coupled to the source of the first P-type transistor, and a drain coupled to the first node. A driving circuit as claimed in claim 2, wherein the first P-type transistor and the second P-type transistor are laterally-diffused metal-oxide semiconductor (LDMOS) transistors. A driver circuit as claimed in claim 1, wherein the power device is a large array device (LAD). A driving circuit as claimed in claim 4, wherein the large array element is composed of a plurality of laterally-diffused N-type metal-oxide semiconductor (LDNMOS) transistors. The driving circuit of claim 1, wherein the control circuit further comprises: a step-down circuit coupled between the bonding pad and the transistor element and providing a regulated voltage, wherein the step-down circuit uses the regulated voltage to reduce the voltage of the bonding pad to generate an input voltage, and provides the input voltage to the transistor element. A driving circuit as claimed in claim 6, wherein the buck circuit comprises: an input node coupled to the bonding pad; an output node coupled to the transistor element; and a plurality of buck elements connected in series between the input node and the output node; wherein the regulated voltage is the voltage difference between the input node and the output node. The driving circuit of claim 1, wherein the control circuit further comprises: a first buck circuit coupled to a common source node of the back-to-back connection structure, receiving a tracking voltage, and providing a first regulating voltage, wherein the first buck circuit reduces the tracking voltage with the first regulating voltage to generate a bias voltage, and provides the bias voltage to the common source node; wherein the tracking voltage is equal to the first voltage of the first power terminal or the voltage of the bonding pad. The driving circuit of claim 8, wherein the first buck circuit comprises: a first input node receiving the tracking voltage; a first output node coupled to the common source node of the back-to-back connection structure; and a plurality of first buck elements connected in series between the first input node and the first output node; wherein the first regulated voltage is the voltage difference between the first input node and the first output node. The driving circuit of claim 8 further includes: a voltage tracking circuit, coupling the first power terminal and the bonding pad, for tracking one of the first voltage of the first power terminal and the voltage of the bonding pad to generate the tracking voltage, and applying the tracking voltage to the first step-down circuit. The driving circuit of claim 10, wherein the voltage tracking circuit includes: a first P-type transistor having a gate, a drain coupled to the first power terminal, and a source; a second P-type transistor having a gate coupled to the detection node, a drain coupled to the bonding pad, and a source; a third P-type transistor having a gate coupled to the first power terminal, a drain coupled to the bonding pad, and a source. Source, wherein the source of the third P-type transistor is coupled to the gate of the first P-type transistor at a second node; and A second step-down circuit is coupled between the first power terminal and the second node and provides a second regulated voltage; wherein the source of the first P-type transistor and the source of the second P-type transistor are coupled to an output terminal of the voltage tracking circuit, and the tracking voltage is generated at the output terminal. The driving circuit of claim 11, wherein when the first voltage of the first power supply terminal is greater than or equal to the voltage of the bonding pad, the second step-down circuit reduces the first voltage of the first power supply terminal by the second regulating voltage to determine a control voltage on the second node, and the first P-type transistor is turned on according to the control voltage, so that the tracking voltage is equal to the first voltage. A driving circuit as claimed in claim 11, wherein when the first voltage at the first power supply terminal is less than the voltage of the bonding pad, the second P-type transistor is turned on and the tracking voltage is equal to the voltage of the bonding pad. A driving circuit as claimed in claim 13, wherein when the first voltage at the first power supply terminal is less than the voltage of the bonding pad, the third P-type transistor is turned on, and a control voltage at the second node is determined according to the voltage of the bonding pad to turn off the first P-type transistor. The driving circuit of claim 11, wherein the second buck circuit comprises: a first input node coupled to the first power supply terminal; a first output node coupled to the first P-type transistor at the second node; and a plurality of first buck elements connected in series between the first input node and the first output node; wherein the second regulated voltage is the voltage difference between the first input node and the first output node. The driving circuit of claim 11, wherein the first P-type transistor, the second P-type transistor, and the third P-type transistor are lateral diffused metal oxide semiconductor (LDMOS) transistors. The driving circuit of claim 1 further includes: a voltage tracking circuit, coupling the first power terminal and the bonding pad, for tracking one of the first voltage of the first power terminal or the voltage of the bonding pad to generate a tracking voltage, and providing the tracking voltage to a common source node of the back-to-back connection structure. The driving circuit of claim 1 further includes: a transmission gate circuit having an input terminal and an output terminal coupled to the first node and controlled by a first switching signal; wherein, when the first power terminal receives an operating voltage as the first voltage, the input terminal of the transmission gate circuit receives an input signal, and transmits the input signal to the output terminal according to the first switching signal. The driving circuit of claim 18, wherein the transmission gate circuit comprises: an N-type transistor having a gate for receiving the first switching signal, a drain coupled to the input end, and a source coupled to the output end; and a P-type transistor having a gate for receiving a second switching signal, a source coupled to the input end, and a drain coupled to the output end; wherein the first switching signal and the second switching signal are inverted. A driving circuit as claimed in claim 1, wherein the detection circuit comprises: a resistor coupled between the first power supply terminal and the detection node; and a capacitor coupled between the detection node and the second power supply terminal.

Images