TWI846185B - Charger - Google Patents

Abstract

A charger includes a thermal conductive plate for heat dissipation, and a transistor. The transistor includes a drain terminal of a first pulsating voltage level, and a source terminal of a second pulsating voltage level. The second pulsating voltage level is lower than the first pulsating voltage level. The source terminal is connected to the thermal conductive plate. The thermal conductive plate is disposed on a first surface of a mother board. The mother board comprises one or more thermal conductive layers embedded in the mother board between the first surface and a second surface opposite the first surface. The one or more thermal conductive layers are connected to the thermal conductive plate.

Description

Charger

The present disclosure relates to a power charging device. More particularly, the present disclosure relates to a charger for charging an electronic device.

Chargers such as mobile phone chargers are already known. As there are more and more applications, especially multimedia applications running on mobile phones, the battery power of the mobile phone can be consumed very quickly. The same may happen with other consumer electronic devices such as MP3 players, game consoles, cameras and mobile phone Bluetooth headsets. These electronic devices may need to be charged frequently. In order to meet this power demand, portable power supplies have been developed.

Some embodiments of the present disclosure provide a charger. The charger includes a heat-conducting plate for heat dissipation and a transistor. The transistor includes a drain terminal with a first pulse voltage level and a source terminal with a second pulse voltage level. The second pulse voltage level is lower than the first pulse voltage level. The source terminal is connected to the heat-conducting plate, which is located on a first surface of a motherboard, and the motherboard includes one or more heat-conducting layers, which are embedded in the motherboard between the first surface and a second surface opposite to the first surface, and the one or more heat-conducting layers are connected to the heat-conducting plate.

In one embodiment, the source terminal is attached to a carrier, and the drain terminal is wire bonded and connected to a plurality of first pins of the carrier.

In another embodiment, the carrier includes a plurality of second pins attached to the thermally conductive plate.

In another embodiment, the thermally conductive plate includes a copper clad.

In another embodiment, the one or more thermally conductive layers include one or more copper claddings.

In another embodiment, the charger further includes a controller configured to control the conduction time of the transistor.

In another embodiment, the controller includes one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller.

In another embodiment, the controller and the transistor are packaged together in a semiconductor device.

In another embodiment, the charger further comprises a transformer, wherein the drain terminal of the transistor is coupled to a dotted terminal of a primary winding of the transformer.

Some embodiments of the present disclosure also provide a charger. The charger includes a heat conductive plate for heat dissipation, and a semiconductor device. The semiconductor device includes a carrier, which includes a die pad, a first pin and a second pin, and includes a transistor attached to the carrier. The transistor includes a drain terminal with a first pulse voltage level and a source terminal with a second pulse voltage level, and the second pulse voltage level is lower than the first pulse voltage level. The drain terminal is wire bonded and connected to the first pins of the carrier. The source terminal is attached to the die pad of the carrier. The second pins are exposed from the semiconductor device and attached to the heat conducting plate.

10: Charger

11: Controller

12: Transistor

14: Transformer

15: Input level

16: Filter

17: Buffer

18: Output stage

25: Molding plastic

30:Semiconductor devices

35: Molding plastic

40: Motherboard

42: Heat sink

50: Charger

60: Motherboard

61: First surface

62: Second surface

68: Transduction pathway

71: Copper cladding layer

72: Copper cladding layer

120: Die pad

128: Active layer

155: Bridge rectifier

S: Source

D: Drain

G: Gate

BW: Bonding wire

BW1: First bonding line

BW2: Second bonding line

LF:Lead frame

LF1: First carrier

LF2: Second carrier

GND: Ground

CS: Current flow measurement pin

Source: Source

Controller: Controller

CTRL: control signal

MOSFET: Metal Oxide Semiconductor Field Effect Transistor

Drain: Drain

VCC: power supply

Vac: alternating current voltage

Vin: Input voltage

C1: Capacitor element

C2: Capacitor element

C3: Capacitor element

D1: diode

D2: diode

R1: resistor element

R2: resistance element

Vout: output voltage

Load: Load

Please note that, in accordance with industry standards, various features are not drawn to scale. In fact, the size of various features may be exaggerated or reduced for clarity of illustration.

Figure 1 is a circuit diagram illustrating a charger according to an embodiment of the present disclosure.

FIG2A is a schematic diagram illustrating the transistor of the charger shown in FIG1 of the disclosed embodiment.

FIG2B is a cross-sectional view showing the transistor shown along line AA in FIG2A.

FIG. 3A is a schematic top view illustrating a semiconductor device including a transistor and a controller of the charger shown in FIG. 1 according to an embodiment of the present disclosure.

FIG3B is a bottom view illustrating the semiconductor device shown in FIG3A.

FIG4 is a schematic diagram illustrating the charger shown in FIG1 of the disclosed embodiment.

Figure 5 is a cross-sectional view illustrating a charger according to an embodiment of the present disclosure.

The following disclosure provides many different embodiments or examples for implementing different features of the subject matter provided. Specific examples of components and configurations are described below to simplify the disclosure. Of course, these are only examples and are not intended to limit the disclosure. For example, in the description, a first feature formed above or on a second feature may include an embodiment in which the first and second features are directly in contact, and may also include an embodiment in which other features are formed between the first and second features, so that the first and second features may not be in direct contact. In addition, the disclosure may repeat component symbols and/or text in different examples. This repetition is for the purpose of simplification and clarification, and does not itself determine the relationship between the various embodiments and/or architectures discussed.

According to some embodiments of the present disclosure, FIG1 is a circuit diagram of a charger 10. The charger 10 may include a portable charger for instantly charging a mobile phone or other portable electronic devices.

Referring to FIG. 1 , the charger 10 includes a controller 11, a transistor 12, and a transformer 14. The controller 11 is configured to generate a control signal CTRL, which controls the on-time and off-time of the transistor 12. In one embodiment, the controller 11 includes a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. The controller 11 detects the current intensity flowing through the source pin of the transistor 12 at the current sensing pin CS, and determines the duty cycle of the control signal CTRL. By changing the duty cycle of the control signal CTRL provided to the transistor 12, the controller 11 causes the transformer 14 to generate a desired output voltage Vout for the electronic device, i.e., the load in FIG. 1 . In this embodiment, the controller 11 and the transistor 12 act as an AC to DC converter.

Transistor 12 may include a metal-oxide-semiconductor field-effect transistor (MOSFET). The drain terminal of transistor 12 is connected to the dotted terminal (indicating polarity) of the primary winding of transformer 14. The source terminal of transistor 12 (described in detail below) is attached to a heat conductive plate, such as a heat sink for heat dissipation. The gate of transistor 12 is connected to controller 11 to receive a control signal CTRL. In operation, the drain pulse voltage can be at least as high as several hundred volts (V), while the source pulse voltage can be as low as 1V. The drain voltage is significantly greater than the source voltage, and can be at least two orders of magnitude (one hundred times) greater. Transistor 12 acts as a switch operating in a high voltage environment.

In this embodiment, the charger 10 also includes an input stage 15, a filter 16, a snubber 17, and an output stage 18. In response to an alternating current (ac) voltage Vac (which may be a main supply voltage), the input stage 15 is configured to provide an input voltage Vin. In some Asian countries, Vac may be 110V, and in the range of 220V to 240V in the United States or Europe. The input stage 15 includes a bridge rectifier 155 for converting Vac into a direct current (dc) voltage. The voltage Vin is filtered in the filter 16 to remove AC ripples, and processed in the snubber 17 to suppress voltage transients. In the exemplary embodiment, the filter 16 includes a capacitor C1 connected between the bridge rectifier 155 and a reference voltage (e.g., ground voltage). Furthermore, the snubber 17 includes a capacitor C2 and a resistor R1 connected in parallel, and then connected in series with a diode D1 between the terminals of the primary winding of the transformer 14. The anode of the diode D1 is connected to the same terminal of the primary winding of the transformer 14.

The transformer 14 is configured to convert a relatively large input voltage Vin into a relatively small output voltage Vout. The relationship between Vout and Vin can be expressed by the following equation.

Where D represents the duty cycle of the control signal CRTL, and N1 and N2 represent the number of turns of the primary winding and the secondary winding of the transformer 14, respectively.

Vac，而Vout取決於應用而通常範圍可自約5至12V，或是在一些情況下可達到接近20V。在輸出級18提供輸出電壓Vout。在例示實施例中，輸出級18包含電阻元件R2與電容元件C3，串聯連接於二極體D2的陰極與變壓器14的次級繞組的非同位端之間。電阻元件R2功能作為等效串聯電阻(equivalent series resistor，ESR)。二極體D2的陽極連接至變壓器14的次級繞組的同位端。 In one embodiment, Vin is close to

Vac , and Vout depends on the application and can generally range from about 5 to 12V, or in some cases can reach nearly 20V. The output voltage Vout is provided at the output stage 18. In the exemplary embodiment, the output stage 18 includes a resistor element R2 and a capacitor element C3, which are connected in series between the cathode of the diode D2 and the non-in-phase end of the secondary winding of the transformer 14. The resistor element R2 functions as an equivalent series resistor (ESR). The anode of the diode D2 is connected to the in-phase end of the secondary winding of the transformer 14.

FIG. 2A is a schematic diagram illustrating the transistor 12 of the charger 10 shown in FIG. 1 of the disclosed embodiment.

Referring to FIG. 2A , transistor 12 is attached at its source terminal to a supporting substrate or carrier, such as a lead frame LF. Lead frame LF includes a die pad 120, a first pin D, and a second pin S. Gate and drain terminals of transistor 12 are wire bonded to corresponding pins G and D of lead frame LF via bonding wires BW. The source terminal of the transistor is attached to die pad 120 of lead frame LF. Transistor 12 is packaged in molding compound 25 (as shown in the dashed rectangular box) together with bonding wires BW. It is understood by those skilled in the art that the drain and source terminals of a MOS transistor can be interchangeable depending on the voltage level applied thereto. For example, in operation, the drain voltage is typically higher than the source voltage in an n-type MOS (NMOS) transistor and lower than the source voltage in a p-type MOS (PMOS) transistor.

FIG2B is a cross-sectional view showing the transistor shown along line AA in FIG2A.

2B , the transistor 12 includes a gate terminal G, a drain terminal D, a source terminal S, and an active layer 128 between the drain terminal D and the source terminal S. The active layer 128 may include a semiconductor layer and an interconnect structure to enable transistor function. The source terminal S and the drain terminal D are located on opposite sides of the active layer 128. The source terminal S of the transistor 12 is attached to a lead frame LF, which is attached to a heat sink on a motherboard (e.g., a printed circuit board). Therefore, it can be said that the transistor 12 has a bottom source structure in which the source terminal S is closer to the heat sink than the drain terminal D. The advantages of transistor 12 are discussed below, in which the source S is coupled to a heat sink.

In existing chargers, compared to the top drain bottom source transistor structure in the charger 10 of the present disclosure, the drain terminal of the transistor is attached to a carrier and then attached to a heat sink on a printed circuit board. As mentioned above, in ACDC applications, the drain voltage is higher than hundreds of volts. In order to dissipate heat, a relatively large copper package is required as a heat sink to cool the transistor. However, in the bottom drain transistor structure, the drain pin pulse voltage is the emitter of electromagnetic interference (EMI). Although a large copper package is used to obtain better thermal performance, stronger radiation may occur and worsen the EMI problem. Therefore, an efficient EMI filter is needed to mitigate EMI radiation, which may inevitably complicate the circuit design and increase the cost of the charger.

Unlike existing chargers, the bottom source transistor structure has a relatively low source pulse voltage, which can be as low as 1V as mentioned above, significantly lower than the drain pulse voltage. Compared to existing methods based on the bottom drain transistor structure, the charger 10 of the present disclosure enjoys a relatively large heat sink, which enhances thermal performance while avoiding EMI problems caused by the high pulse voltage as an emission source.

The bottom source structure can be found in U.S. Patent No. 7,394,151 (the '151 patent) (titled "Semiconductor package with Plated Connection") or U.S. Patent No. 8,008,716 (the '716 patent) (titled "Inverted-Trench Grounded-Source FET Structure with Trenched Source Body Short Electrode"), both of which are issued to the same assignee. In particular, the bottom source structure is disclosed in, for example, FIGS. 7A and 7B and related descriptions in the '151 patent, or in, for example, FIGS. 2 and 3 and related descriptions in the '716 patent. The relevant descriptions of the '151 and '716 patents are incorporated herein by reference.

Existing transistors with bottom drain structures (such as planar MOSFETs and trench MOSFETs) can also be used in the present embodiment without modification. In some embodiments, the transistor is "flipped" with its source terminal facing the lead frame and attached to the lead frame at the source terminal, forming a bottom source structure as shown in Figures 2A and 2B.

FIG3A is a schematic top view illustrating a semiconductor device 30 of the disclosed embodiment, which includes a controller 11 and a transistor 12 of the charger 10 shown in FIG1 .

Referring to FIG. 3A , the controller 11 and the transistor 12 of the charger 10 are packaged together in the semiconductor device 30. Specifically, the controller 11 attached to the first carrier LF1 and the transistor 12 attached to the second carrier LF2 are packaged in a molding compound 35. To control the transistor 12, the controller 11 transmits a control signal CTRL to the gate of the transistor 12 via the first bonding wire BW1. The drain terminal of the transistor 12 is electrically connected to the first pin (drain pin D) of the second carrier LF2 via the second bonding wire BW2. Considering the relatively large drain voltage, the second carrier LF2 includes a plurality of drain pins.

FIG3B is a bottom view illustrating the semiconductor device 30 shown in FIG3A. Referring to FIG3B, some second pins (source pins S) of the second carrier LF2 are exposed from the semiconductor device 30. These exposed source pins S work together with the heat sink to help dissipate heat.

FIG. 4 is a schematic diagram illustrating the charger 10 shown in FIG. 1 of the disclosed embodiment.

Referring to FIG. 4 , the second carrier LF2 is attached to the heat sink 42 on the motherboard 40 by, for example, solder paste. In the present embodiment, the die pad 120 where the source terminal of the transistor 12 is located is attached to the heat sink 42. The heat generated by the semiconductor device 30 (particularly the transistor 12) can be dissipated to the heat sink 42 via the bottom source terminal and can also be dissipated to the heat sink 42 via the exposed source pin S. Therefore, the exposed source pin S provides an additional heat dissipation path.

FIG5 is a cross-sectional view illustrating a charger 50 of the disclosed embodiment.

Referring to FIG. 5 , the charger 50 includes a transistor 12 and a transformer 14, which are located on a first surface 61 of a motherboard 60. In the present embodiment, the transistor 12 is packaged as a single semiconductor device. Alternatively, as shown in FIG. 3A , the transistor 12 may be packaged together with the controller 11 in a semiconductor device. The source terminal of the transistor 12 is attached to a carrier, which is attached to a copper cladding 42 located on the first surface 61. The copper cladding 42 acts as a heat sink. The motherboard 60 includes at least one thermally conductive layer for heat dissipation. In the present embodiment, the at least one thermally conductive layer includes copper claddings 71 and 72 embedded in the motherboard 60. In other embodiments, the number of copper cladding layers is not limited to two layers. The additional copper cladding layers 71 and 72 are coupled to the copper cladding 42 via the conductive path 68, so that heat is dissipated from the transistor 12 toward the second surface 62 of the motherboard 60 via the copper cladding 42 and the copper cladding layers 71 and 72 on the first surface 61.

Those skilled in the art will appreciate that modifications may be made to the embodiments disclosed herein. For example, the total number of pins may be changed. Other modifications may be made by those skilled in the art, and all such modifications fall within the scope of the present disclosure as defined by the scope of the patent application.

10: Charger

11: Controller

12: Transistor

14: Transformer

15: Input level

16: Filter

17: Buffer

18: Output stage

155: Bridge rectifier

GND: Ground

CS: Current flow measurement pin

Source: Source

Controller: Controller

CTRL: control signal

MOSFET: Metal Oxide Semiconductor Field Effect Transistor

Drain: Drain

VCC: power supply

Vac: alternating current voltage

Vin: Input voltage

C1: Capacitor element

C2: Capacitor element

C3: Capacitor element

D1: diode

D2: diode

R1: resistor element

R2: resistance element

Vout: output voltage

Load: Load

Claims (18)

A charger comprises: a heat-conducting plate for heat dissipation; and a transistor, comprising: a drain terminal of a first pulse voltage level; and a source terminal of a second pulse voltage level, the second pulse voltage level being lower than the first pulse voltage level; wherein the source terminal is connected to the heat-conducting plate; wherein the heat-conducting plate is located on a first surface of a motherboard; wherein the motherboard comprises one or more heat-conducting layers, the one or a plurality of heat-conducting layers are embedded in the motherboard between the first surface and a second surface opposite to the first surface; and wherein the source terminal having the second pulse voltage level is attached to a carrier located at a first side of the transistor, and the drain terminal having the first pulse voltage level higher than the second pulse voltage level is located at a second side of the transistor opposite to the first side and facing away from the carrier. A charger as described in claim 1, wherein a gate terminal of the transistor is located on the second side of the transistor opposite to the first side. A charger as described in claim 1, wherein the carrier includes a plurality of pins attached to the thermally conductive plate. A charger as described in claim 1, wherein the heat conductive plate comprises a copper clad. A charger as described in claim 1, wherein the one or more thermally conductive layers include one or more copper coatings. The charger as described in claim 1 further comprises: a controller configured to control the conduction time of the transistor. A charger as described in claim 6, wherein the controller includes one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. A charger as described in claim 7, wherein the controller and the transistor are packaged together in a semiconductor device. The charger as described in claim 1 further comprises a transformer, wherein the drain terminal of the transistor is coupled to the dotted terminal of the primary winding of the transformer. A charger comprises: a heat conducting plate for heat dissipation; and a semiconductor device comprising: a carrier attached to the heat conducting plate, the carrier comprising a die pad and a plurality of first pins; and a transistor attached to the carrier, the transistor comprising: a drain terminal of a first pulse voltage level; and a source terminal of a second pulse voltage level, the second pulse voltage level The pulsating voltage level is lower than the first pulsating voltage level, the source terminal is attached to the die pad of the carrier, wherein the carrier and the drain terminal are respectively located on opposite sides of the source terminal, and the source terminal is closer to the heat conducting plate to which the carrier is attached than the drain terminal; wherein the plurality of first pins are connected to the die pad, exposed from the semiconductor device and attached to the heat conducting plate. A charger as described in claim 10, wherein the die pad of the carrier is attached to the heat conductive plate. A charger as described in claim 10, wherein the heat conductive plate comprises a copper coating. A charger as described in claim 10, wherein the heat conductive plate is located on a motherboard; wherein the motherboard includes: a heat conductive layer embedded in the motherboard; and wherein the heat conductive layer is connected to the heat conductive plate. A charger as described in claim 13, wherein the thermally conductive layer comprises a copper coating. The charger as described in claim 10 further comprises: a controller configured to control the conduction time of the transistor. A charger as described in claim 15, wherein the controller includes one of a pulse-width modulation (PWM) controller or a constant on-time (COT) controller. A charger as described in claim 16, wherein the controller and the transistor are packaged together in the semiconductor device. The charger as described in claim 10 further includes a transformer, wherein the drain terminal of the transistor is coupled to the dotted terminal of the primary winding of the transformer.