TWI713039B - Semiconductor storing apparatus and flash memory operation method - Google Patents

Abstract

A flash memory capable of releasing a deep power-down mode automatically is provided. The flash memory includes: a standard command I/F circuit and a DPD controller operating through an external power voltage; and an internal circuit operating through internal voltages supplied from voltage supply nodes. The DPD controller detects if it is the deep power-down mode or not when a standard command is inputted to the standard command I/F circuit and recovers the internal circuit from the DPD mode when the deep power-down mode is detected. Performing the standard command after the internal circuit is recovered.

Description

Semiconductor storage device and flash memory operation method

The invention relates to a semiconductor storage device such as a flash memory, in particular to operation in a standby mode or a deep power saving mode.

NAND (Not AND, NAND) flash memory can be read or programmed in units of pages, and erased in units of blocks. The flash memory shown in Patent Document 1 discloses a technique of supplying different power supply voltages to the page buffer/readout circuit in a standby mode (stand-by mode) and a normal operation mode, thereby Reduce power consumption in standby mode. [Prior Art Literature] [Patent Literature]

[Patent Document 1] Japanese Patent Laid-Open No. 2006-252748

[The problem to be solved by the invention]

The flash memory has an active mode and a standby mode. The active mode performs reading, programming, erasing, etc. in response to commands from the user, and the standby mode can accept commands from the user. In the standby mode, the operation of the internal circuit is restricted so that the power consumption becomes less than a certain level. However, when a command is input from the user, the command must be responded to immediately. Therefore, even in the standby mode, off-leak current is generated in volatile circuits such as logic circuits or registers. The off-leak current increases with the reduction of component size, and it is in use In the case of internal power supply voltage, the internal power supply voltage detection circuit must be operated, which consumes a certain amount of power. That is, it is difficult to reduce the current consumption in the standby mode.

In order to further reduce the power consumption in standby mode, depending on the flash memory, a deep power-down mode (hereinafter referred to as DPD mode) is sometimes equipped. In the DPD mode, the internal power supply to a part of the internal circuit used in the standby mode is shut down to reduce the power leakage current. The DPD mode is entered into the mode by a DPD start command, for example, and is restored from the mode by a DPD release command. Regarding the recovery from the DPD mode, a certain amount of time is required for the shut down circuit to operate normally, but on the other hand, it has the advantage of greatly reducing power consumption.

Fig. 1A shows an example of the operating waveform when a NAND-type flash memory equipped with a serial peripheral interface (Serial Peripheral interface, SPI) function transitions to the DPD mode. In the standby mode, the flash memory is selected by setting the chip selection signal /CS to low level, and the DPDDPD command (B9h) is input from the data registration terminal DI in synchronization with the clock signal during this period. The flash memory transitions to the DPD mode at a time T _DPD when a certain period of tDP has elapsed since the input of the DPD command, and blocks the internal supply of voltage to a specific internal circuit. In the period before the time T _DPD , the current in the standby mode is consumed, and in the period after the time T _DPD , the current in the DPD mode is consumed.

In addition, FIG. 1B shows an example of the operating waveform when recovering from the DPD mode. In the standby mode, the flash memory is selected by setting the chip selection signal /CS to low level. During this period, the DPD release command (ABh) to release the DPD mode is input from the data registration terminal DI in synchronization with the clock signal. After the DPD release command is input, the flash memory supplies power to the shut down internal circuit during the period of tRES, and returns to the state where the internal circuit is operating normally at time T _ST . Before the time T _ST , the current in the DPD mode is consumed, and after the time T _ST , the current in the standby mode is consumed.

Figure 2 is an internal block diagram of a NAND flash memory supporting DPD mode. The flash memory 10 includes a DPD controller 20, a memory cell array 30, a row decoder 40, a page buffer/readout circuit 50, a peripheral circuit 60, a high voltage circuit 70, etc. An external power supply voltage (for example, 3.3V) VCC is supplied to the flash memory 10, and the DPD controller 20 directly uses the external power supply voltage VCC to operate. A P-channel metal oxide semiconductor (Positive channel Metal Oxide Semiconductor, PMOS) transistor P is connected between the external power supply voltage VCC and the internal circuit, and a DPD enable signal DPDEN is applied to the gate of the transistor P. In the active mode and the standby mode, the DPD controller 20 generates an L-level DPD enable signal DPDEN to turn on the transistor P. Thereby, the internal voltage VDD is supplied to each internal circuit via the voltage supply node INTVDD. In the DPD mode, the DPD controller 20 generates an H-level DPD enable signal DPDEN, and sets the transistor P to be non-conductive. As a result, the supply of the external power supply voltage VCC is shut down, and the operation of the internal circuit is stopped.

In the case of releasing the DPD mode, as shown in FIG. 1B, the user inputs a DPD release command (ABh) from the outside. The DPD controller 20 responds to the input of the DPD release command, causes the DPD enable signal DPDEN to transition to the L level, turns on the transistor P, and starts to supply power from the external power supply voltage VCC to the internal circuit. As a result, the internal circuit is restored to an operable state after the period tRES.

In this way, for the existing flash memory, in order to use the DPD mode, the user must not only input the DPD command, but also the DPD release command. For the flash memory controller that does not support the DPD command and the DPD release command , There are problems such as inability to use DPD mode.

The present invention solves such existing problems, and its object is to provide a semiconductor storage device that can release the deep power saving mode without a dedicated command for releasing the deep power saving mode. [Technical means to solve the problem]

The operating method of the flash memory of the present invention includes: when a standard command including read, program, or erase is input, the step of detecting whether it is a deep power saving mode that blocks power supply to a specific circuit; In the case of the deep power saving mode, the step of canceling the deep power saving mode; and the step of executing the standard command after the specific circuit is restored.

In one embodiment of the flash memory of the present invention, if the deep power saving mode is not detected, the input standard command is executed without releasing the deep power saving mode. In one embodiment of the flash memory of the present invention, the releasing step restores the specific circuit selected according to the type of the standard command. In an embodiment of the flash memory of the present invention, the step of releasing includes: turning on a switching transistor connected between the power supply voltage and the specific circuit. In an embodiment of the flash memory of the present invention, the deep power saving mode jumps from the standby mode, and the power consumption of the standby mode is further reduced.

The semiconductor memory device of the present invention includes: a peripheral circuit; a detection unit, when a standard command including read, program, or erase is input from the outside, detects whether it is blocking one or more specific circuits to the peripheral circuit A deep power saving mode of power supply; a release component that releases the deep power saving mode if the deep power saving mode is detected; and an execution component that executes the standard command after the specific circuit is restored.

In one embodiment of the semiconductor memory device of the present invention, if the deep power saving mode is not detected, the standard command is executed without releasing the deep power saving mode by the release means. In an embodiment of the semiconductor storage device of the present invention, the cancellation means restores the specific circuit selected according to the type of the standard command. In one embodiment of the semiconductor memory device of the present invention, the releasing means includes a plurality of switching transistors respectively connected between an external power supply voltage and a plurality of specific circuits, and the releasing means makes any of the plurality of transistors One is on. In an embodiment of the semiconductor storage device of the present invention, the semiconductor storage device is a flash memory. [Effects of the invention]

According to the present invention, there is no need for a dedicated command for releasing the deep power saving mode, but the input of the standard command can be responded to to release the deep power saving mode, and the input standard command can be executed quickly.

The semiconductor storage device of the present invention is not particularly limited, and is implemented in, for example, a NAND type or NOR (Not OR, NOR) type flash memory. [Example]

Next, the embodiments of the present invention will be described in detail with reference to the drawings. 3 is a diagram showing a schematic internal structure of a NAND flash memory according to an embodiment of the present invention. The flash memory 100 includes: a standard command interface (interface, I/F) circuit 110 that accepts standard commands, a DPD controller 120 that controls the jump to the DPD mode and the release of the DPD mode, etc., a memory cell array 130, and row decoding Internal circuits such as the processor 140, the page buffer/readout circuit 150, the peripheral circuit 160, the peripheral circuit 170, and the high voltage circuit 180.

The flash memory 100 of this embodiment can operate in multiple power consumption modes. The active mode does not limit power consumption and executes standard commands (such as read, program, erase) with full specifications. In the standby mode, when it is not in the active mode, the internal circuit is operated in accordance with the prescribed power consumption requirements, and the operation is performed in a manner that can respond to the input of standard commands and the like. In the standby mode, for example, the charge pump of the high-voltage circuit is stopped, or the internal supply voltage is reduced. In the DPD mode, in order to further reduce the power consumption in the standby mode, the power supply to a specific circuit is blocked in the standby mode.

The standard command I/F circuit 110 and the DPD controller 120 directly use the external power supply voltage VCC (for example, 3.3V) to operate, that is, they can operate in the standby mode and the DPD mode. The standard command I/F circuit 110 is an interface circuit for externally accepting standard commands prepared in advance for standard operation of the flash memory. The standard commands are, for example, commands for reading, programming, erasing, etc. The standard command I/F circuit 110 includes a complementary metal oxide semiconductor (Complementary Metal Oxide Semiconductor, CMOS) logic device for decoding the input standard command, and the decoded result DEC is provided to the DPD controller 120 and the peripheral circuit 160 (including A controller or state machine used to control the operation of standard commands).

The DPD controller 120 controls the transition from the standby mode to the DPD mode and the release of the DPD mode. A PMOS transistor P1 is connected between the external power supply voltage VCC and the voltage supply node INTVDD1, and a PMOS transistor P2 is connected between the external power supply voltage VCC and the voltage supply node INTVDD2. The voltage supply node INTVDD1 is connected to the row decoder 140, the page buffer/read circuit 150, the peripheral circuit 160, and the high voltage circuit 180, and the voltage supply node INTVDD2 is connected to the peripheral circuit 170.

In the active mode and standby mode, the DPD controller 120 generates L-level DPD enable signals DPDEN1 and DPD enable signals DPDEN2, turns on transistors P1 and P2, and supplies them to voltage supply node INTVDD1 and voltage supply node INTVDD2 External power supply voltage VCC. In addition, when the DPD controller 120 is in the DPD mode, the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 are transitioned to H level, the transistor P1 and the transistor P2 are set to non-conduction, and the supply to the voltage supply nodes INTVDD1 is blocked. The voltage supply node INTVDD2 is powered by the external power supply voltage VCC. The DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 may, for example, transition to the H level at different timings according to the elapsed time from the point of transition to the standby mode.

The method of jumping from the standby mode to the DPD mode is not particularly limited. In a certain form, the DPD controller 120 does not input a command for jumping to the DPD mode from the user, but responds from the peripheral circuit 160 (including the control flash The signal of the running controller of the memory automatically jumps to DPD mode. For example, if a signal indicating a transition to the standby mode is provided from the peripheral circuit 160 to the DPD controller 120, the DPD controller 120 measures the time from the point in time indicating the transition to the standby mode, and the transition occurs when the duration of the standby mode exceeds a certain time. To the DPD mode, the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 are transitioned to H level, blocking the power supply from the external power supply voltage VCC. In addition, in another form, the DPD controller 120 may also jump to the DPD mode in response to the input of a command for jumping to the DPD mode from the user.

Regarding the method of releasing the DPD mode, in the existing flash memory, a dedicated command for releasing the DPD mode needs to be input from the outside. However, this embodiment has a function of automatically releasing the DPD mode without inputting such a dedicated command. The details of the release function will be described later, but if in the DPD mode, the standard command I/F circuit 110 receives a standard command, the DPD controller 120 responds to the standard command to release the DPD mode, which is required for the restoration of the DPD mode After the time has passed, the standard commands are executed seamlessly.

The DPD controller 120 of this embodiment may be constructed using hardware and/or software, and may include, for example, a microcomputer, a state machine, and a logic device.

The memory cell array 130 includes a plurality of blocks, and each block includes a plurality of NAND strings. The NAND string can be formed two-dimensionally on the substrate, or three-dimensionally formed in the vertical direction from the main surface of the substrate. In addition, the memory unit can store binary data or multi-value data.

The peripheral circuit 160 and the peripheral circuit 170 include, for example, the following parts: a controller or a state machine that controls the operation of the flash memory 100 based on the standard commands received by the standard command I/F circuit 110; or error checking and correction (Error Checking and Correction, ECC) circuit, column selection circuit, error detection and correction of data. The high voltage circuit 180 includes a charge pump circuit for generating high voltages required for reading, programming, and erasing. In addition, the flash memory 100 can be equipped with SPI (Serial Peripheral Interface). In SPI, instead of control signals (allowing address latching, allowing command latching, etc.), the input commands and bits are recognized in synchronization with the serial clock signal. Address and information.

Next, the method for releasing the DPD mode of the flash memory of this embodiment will be described with reference to the flow of FIG. 4. If a standard command is input to the standard command I/F circuit 110 (S100 ), the standard command I/F circuit 110 decodes the standard command, and provides the decoded result DEC to the DPD controller 120 and the peripheral circuit 160. If the DPD controller 120 receives the decoding result DEC, it determines whether it is the DPD mode (S110). When it is determined to be the DPD mode, the DPD controller 120 releases the DPD mode (S120). That is, the DPD controller 120 causes the DPD enable signal DPDEN1 and DPD enable signal DPDEN2 to transition from the H level to the L level, sets the transistor P1 and the transistor P2 to the conductive state, and transfers the external power supply voltage VCC to the voltage supply node INTVDD1 and voltage supply node INTVDD2 supply power. Thus, the internal voltage VDD1 is supplied from the voltage supply node INTVDD1 to the row decoder 140, the page buffer/read circuit 150, and the peripheral circuit 160, and the internal voltage VDD2 is supplied from the voltage supply node INTVDD2 to the peripheral circuit 170. These peripheral circuits 140 to 180 are restored to an operable state at the time T _ST when the tRES period has elapsed as shown in FIG. 1B.

When the restoration of the peripheral circuit 140 to the peripheral circuit 180 is completed, the peripheral circuit 160 executes the operation of the standard command based on the decoding result DEC from the standard command I/F circuit 110 (S130). The period (tRES) during which the peripheral circuit is restored by releasing the DPD mode is a busy period during which access to the flash memory is prohibited. In this embodiment, the standard command is executed seamlessly after the tRES period has elapsed.

On the other hand, if the DPD controller 120 determines that it is not in the DPD mode when the standard command is input (S110), the DPD is not released (that is, the DPD enable signal DPDEN1 and the DPD enable signal DPDEN2 are already at L level), The operation of the standard command is immediately executed through the peripheral circuit 160 (S130).

As a specific operation example, if a read, program, or erase command is input to the standard command I/F circuit 110 in the DPD mode, the DPD controller 120 causes the DPD enable signals DPDEN1 and DPD to enable the DPD mode to cancel the DPD mode. The energy signal DPDEN2 transitions to the L level to turn on the transistor P1 and the transistor P2. Next, in the tRES period shown in FIG. 1B, the internal circuit is restored, and then read, program, or erase is performed immediately.

In this way, according to this embodiment, the DPD mode is automatically released in response to the input of the standard command, so there is no need to input a dedicated command to release the DPD mode. Even the flash memory that does not support the release command of the DPD mode can release the DPD mode. . Furthermore, if it is a flash memory that automatically controls the transition from the standby mode to the DPD mode (that is, there is no need for a dedicated command for the transition to the DPD mode), the user input of all commands related to the DPD mode can be automatically performed. Jump to and release from DPD mode.

Next, another embodiment of the present invention will be described. In the above embodiment, the DPD controller 120 responds to the input of the standard command to restore the internal circuits from the DPD mode. However, in this embodiment, the restored internal circuit is selected according to the type of the standard command. The table shown in FIG. 5 shows the relationship between the standard command of this embodiment [this embodiment], the restored voltage supply node, and the restoration (recovery) time. Among the standard commands, in addition to reading, programming, and erasing, there are Status Read or Identifier (ID) reading. Status read is to read whether the flash memory is in a ready state, whether it is in write-protected mode, whether it is a command in program/erase operation, and ID read is a command to read out manufacturer or product identification.

When the standard command is equivalent to status reading or ID reading, the DPD controller 120 only transitions the DPD enable signal DPDEN1 to the L level, turns on the transistor P1, and only restores the voltage supply node INTVDD1. At this time, only the voltage supply node INTVDD1 can be restored, so the restoration time can be accelerated. On the other hand, when the standard command corresponds to programming, reading, and erasing, the DPD controller 120 makes the DPD enable signal DPDEN1 and DPD enable signal DPDEN2 transition to the L level, so that the transistor P1 and the electrical The crystal P2 is turned on, and both the voltage supply node INTVDD1 and the voltage supply node INTVDD2 are restored. Here, the recovery time is the standard time.

In this way, according to this embodiment, the DPD mode can be released with an appropriate recovery time according to the running content of the standard command, and the standard command can be executed.

In the above embodiment, an example in which the external power supply voltage VCC is supplied to the voltage supply node INTVDD1 and the voltage supply node INTVDD2 is shown, but this is just an example, and other internal voltages may also be supplied to the voltage supply node INTVDD1 and the voltage supply node INTVDD2. It is directly supplied from the external power supply voltage VCC.

The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments, and various modifications and changes can be made within the scope of the gist of the invention described in the claims.

10.100: Flash memory 20, 120: DPD controller 30, 130: Memory cell array 40: Row decoder 50: Page buffer/readout circuit 60, 160, 170: Peripheral circuit 70: High voltage circuit 110: Standard command I/F circuit 140: Row decoder (peripheral circuit) 150: Page buffer/readout circuit (peripheral circuit) 180: High voltage circuit (peripheral circuit) ABh: DPD release command B9h: DPDDPD command DEC: Decoding result DI: data registration terminals DPDEN, DPDEN1, DPDEN2: DPD enable signals INTVDD, INTVDD1, INTVDD2: voltage supply node P: PMOS transistors P1, P2: transistors S100～S130: steps T _DPD , T _ST : time tDP : A certain period of time tRES: Period of VCC: External power supply voltage / CS: Chip select signal

FIG. 1A is a diagram showing an example of operating waveforms when a conventional flash memory jumps to the DPD mode. FIG. 1B is a diagram showing an example of operating waveforms when the DPD mode of the conventional flash memory is released. Fig. 2 is a diagram showing the internal structure of a conventional flash memory. Fig. 3 is a diagram showing the internal structure of a flash memory according to an embodiment of the present invention. Fig. 4 is a flowchart showing a procedure for releasing the DPD mode according to the embodiment of the present invention. FIG. 5 is a table showing the relationship between the standard command and the restored voltage supply node and the restoration time according to another embodiment of the present invention.

100: Flash memory

110: Standard command I/F circuit

120: DPD controller

130: memory cell array

140: Line decoder (peripheral circuit)

150: Page buffer/readout circuit (peripheral circuit)

160: Peripheral circuit

170: Peripheral circuit

180: High voltage circuit (peripheral circuit)

DEC: Decoding result

DPDEN1, DPDEN2: DPD enable signal

INTVDD1, INTVDD2: voltage supply node

P1, P2: Transistor

VCC: External power supply voltage

Claims (8)

A flash memory operation method includes: when a standard command including read, program, or erase is input, the step of detecting whether it is a deep power saving mode that blocks power supply to a specific circuit; In the case of the power mode, the step of canceling the deep power saving mode; and the step of executing the standard command after the specific circuit is restored, wherein the step of canceling includes: connecting the power supply voltage and the The switching transistor between specific circuits is turned on, and the level of the enable signal of the switching transistor is determined according to the type of the standard command. The flash memory operating method according to claim 1, wherein, if the deep power saving mode is not detected, the input standard command is executed without releasing the deep power saving mode. The flash memory operating method according to claim 1, wherein the releasing step restores the specific circuit selected according to the type of the standard command. The flash memory operating method according to claim 1, wherein the deep power saving mode jumps from the standby mode, and the power consumption of the standby mode is further reduced. A semiconductor storage device includes: a peripheral circuit; The detection component detects whether it is a deep power saving mode that blocks power supply to one or more specific circuits of the peripheral circuit when a standard command including read, program or erase is input from the outside; the release component, In a case where the deep power saving mode is detected, the deep power saving mode is cancelled; and an execution component that executes the standard command after the specific circuit is restored, wherein the cancellation component includes the components connected to the external power supply voltage respectively And a plurality of switching transistors between a plurality of specific circuits, the release component turns on any one of the plurality of transistors, and the level of the enable signal of the plurality of transistors is based on the standard command It depends on the type. The semiconductor storage device according to claim 5, wherein, in a case where the deep power saving mode is not detected, the standard command is executed without releasing the deep power saving mode by the release means. The semiconductor storage device according to claim 5, wherein the release means restores the specific circuit selected according to the type of the standard command. The semiconductor storage device according to any one of claims 5 to 7, wherein the semiconductor storage device is a flash memory.

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