TWI767320B - Method and apparatus for determining a characteistic of a defect in an electrical line of an electronic system - Google Patents

Abstract

A method for determining a characteristic of a defect in an electrical line of an electronic system, the method comprising: (i) selecting a first clock signal among a plurality of selectable clock signals; (ii) selecting a first reference voltage among a plurality of selectable reference voltages; (iii) obtaining a signal by: producing a first signal transition onto the electrical line; and receiving a second signal transition arising in response to a reflection of the first signal transition from the defect;(iv) producing a plurality of numerical values by sampling the signal using the selected clock signal; (v) producing a plurality of output values by comparing the plurality of numerical values with the selected reference voltage; and (vi) determining the characteristic of the defect based on the plurality of output values.

Description

Method and apparatus for characterizing defects in electrical wiring of electronic systems

The present application relates generally to electronic systems, and more particularly, to methods and apparatus for characterizing defects in electrical wiring of electronic systems.

Electronic systems are inevitably affected by defective parts, such as incomplete solder, broken wires, wrong connections, defective sockets, etc. These defective parts can negatively affect or even destroy the operation of electronic systems. Detecting these defective parts is tedious because it involves disassembling the entire system and then probing all its parts until the defect is found. This process is particularly troublesome in data center applications, where the number of wires and connections can be in the thousands or more.

The following summary is illustrative only and is not intended to be limiting in any way. That is, the following summary is provided to introduce the concepts, gist, benefits and advantages of the novel and non-obvious techniques described herein. Selected implementations are further described below in the detailed description. Thus, the following summary is not intended to identify essential features of the claimed subject matter, nor is it intended for use in determining the scope of the claimed subject matter.

The present invention provides a method of characterizing a defect in an electrical wire of an electronic system, comprising: (i) selecting a clock signal from a plurality of selectable clock signals; (ii) selecting a reference voltage from a plurality of selectable reference voltages (iii) obtaining a signal by: producing a first signal transition on the wire; and receiving a second signal transition that occurs in response to a reflection of the first signal transition by a defect; (iv) by using the a selected clock signal samples the signal to generate a plurality of values; (v) generates a plurality of output values by comparing the plurality of values to the selected reference voltage; and (vi) is based on the plurality of outputs The value determines the characteristics of the defect.

The present invention provides an apparatus for characterizing defects in electrical wiring of an electronic system, comprising: an integrated circuit (IC) configured to: (i) select a clock signal from a plurality of selectable clock signals; (ii) ) selecting a reference voltage from a plurality of selectable reference voltages; (iii) obtaining a signal by: generating a first signal transition on the wire; and receiving the occurrence of a reflection of the first signal transition in response to a defect a second signal transition of ; (iv) generating a plurality of values by sampling the signal using the selected clock signal; (v) generating by comparing the plurality of values with the selected reference voltage a plurality of output values; and (vi) determining a characteristic of the defect based on the plurality of output values.

The present invention provides another apparatus for characterizing defects in wires of an electronic system, comprising: an integrated circuit comprising: a transmitter; a signal driver coupled to the transmitter and the wire; an analog a digital converter (ADC) coupled to the wires; a clock selection circuit coupled to a clock input of the ADC, the clock selection circuit configured to select a clock signal from a plurality of selectable clock signals; refer to a voltage generator configured to select a reference voltage among a plurality of selectable reference voltages; a comparator including a first input coupled to the ADC and a second input coupled to the reference voltage generator; and a time A Domain Reflectometry (TDR) circuit is coupled to the comparator.

Embodiments of the invention may be implemented to determine various characteristics of defects.

Certain terms are used throughout the specification and claims to refer to particular elements. It should be understood by those skilled in the art that hardware manufacturers may use different terms to refer to the same element. This specification and the scope of the patent application do not use the difference in name as a way to distinguish elements, but use the difference in function of the elements as a criterion for distinguishing. The "comprising" and "including" mentioned in the entire specification and the scope of the patent application are open-ended terms, so they should be interpreted as "including but not limited to". "Substantially" means that within an acceptable error range, a person with ordinary knowledge in the technical field can solve the technical problem within a certain error range, and basically achieve the technical effect. Furthermore, the term "coupled" herein includes any direct and indirect means of electrical connection. Therefore, if a first device is described as being coupled to a second device, it means that the first device can be directly electrically connected to the second device, or indirectly electrically connected to the second device through other devices or connecting means device. The following descriptions are preferred modes of implementing the present invention, and are intended to illustrate the spirit of the present invention rather than limit the protection scope of the present invention.

The following description is the preferred embodiment contemplated by the present invention. These descriptions serve to illustrate the general principles of the invention and should not be used to limit the invention. The protection scope of the present invention should be determined on the basis of referring to the scope of the patent application of the present invention. I. Overview

The inventors have developed to significantly reduce the presence and/or detection of defects (eg, incomplete solder, broken cables, misconnections, defective sockets, opens, shorts, etc.) in large electronic systems (eg, data centers) method for the time required for the location. The method developed by the present inventors is based on Time-Domain Reflectometry (TDR), a measurement technique used to determine electrical wire properties by observing reflected waveforms.

Traditional techniques rely on dedicated hardware to perform time-domain reflectometry. As a result, performing time domain reflectometry on a system may require performing a number of steps before the system can be tested. Some of these steps include, for example, powering down the system, disconnecting cables or other connectors from the system, moving the system to a suitable test location, and connecting the system to be tested to a dedicated TDR instrument. The result is that the normal operation of the system needs to be disrupted in order to perform the test.

The TDR circuit developed by the inventor is directly integrated with the system for testing. This means that the system can be tested for the presence of defects or other characteristics without disrupting the operation of the system. In some embodiments, through integration, the TDR circuit can share hardware with other electronic circuits. For example, the same transmitter hardware can be used as both a data transmitter and a TDR transmitter. Having shared hardware is particularly suitable for large circuits (such as in data centers, which may contain thousands of transmitters). In this case, designers of TDR systems, in effect, do not have to design dedicated TDR transmitters, but can utilize existing transmitter hardware, thereby reducing design and manufacturing costs.

The inventors have realised that different methods can be used for performing TDR depending on which defect features the user wishes to determine. In some cases, the user may want to determine the location of the defect, but may not want to know other characteristics of the defect. In these cases, the user may be able to perform appropriate measurements based on the location of the defect, but does not have to know the other characteristics of the defect. Some embodiments of the present application are directed to methods and circuits for determining defect locations. Such an embodiment may use threshold voltages to determine the timing of certain signal transitions and determine the location of defects based on the timing of these transitions. Such methods are referred to herein as "non-digitalized methods for time domain reflectometry" or simply "non-digitalized TDR methods."

However, in other cases, in addition to or instead of the location, the user may wish to determine other characteristics of the defect. For example, a user may wish to determine the impedance of a defect, which in turn can indicate the nature of the defect. Users can use information about the nature of the defect to distinguish between serious defects (eg, defects requiring repair) and non-critical defects (eg, defects not requiring repair). Some embodiments of the present application are directed to methods and circuits for characterizing defects in addition to or instead of locations. Such an embodiment may rely on the use of an analog-to-digital converter to profile the TDR signal waveform, and may include circuitry to characterize the defect from the profile. This method is referred to herein as "digitized method for time domain reflectometry" or simply "digitized TDR method". II. Non-digitized method for time domain reflectometry

FIG. 1 illustrates an example of an electronic system including a plurality of wires, according to some non-limiting embodiments. This particular example shows an integrated circuit (IC) 104 disposed on a package 102 , which in turn is disposed on a printed circuit board (PCB) 100 . IC 104 may include various types of analog and/or digital circuits, micromechanical (MEMS) devices, sensors, and/or other electronic components. IC 104 may include processors, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), memory cells, and/or any other suitable components. IC 104 may be programmed with instructions that, when executed, perform various tasks, such as sending, receiving and/or processing signals in any suitable manner.

In this example, the IC 104 is connected to several wires, where opposite ends of the wires can be connected to other electronic devices. In some embodiments, IC 104 may be connected to hundreds or even thousands of wires. Each wire can include a different physical transmission medium, such as cables, wires, metal traces, pins, contacts, solder, connectors, sockets, etc. For example, the wires may include metal wires 110 (which may in turn include metal traces formed on package 102 , metal traces formed on PCB 100 , and connectors connecting the metal traces), contacts 114 of connector 112 and Cable 116 . The other end of the cable 116 (not shown in FIG. 1 ) may be connected to some other element or conductive path. Another electrical wire may include wires 120, contacts 124 of connectors 122, cables 126, contacts on backplane 125, metal traces 128 on backplane 125, connectors 129, and the like.

In theory at least, each wire connected to IC 104 may be prone to defects. For example, solder may only be partially formed, a cable may be defective, a pair of contacts may not mate with each other properly, a misconnection may occur between pins, a socket may be defective, and so on. These defects can alter the electrical properties of the wire. For example, an open circuit or a short circuit may occur. Additionally or alternatively, the impedance (eg, resistance, capacitance, and/or inductance) of the wires may increase or deviate from expected values. Often, defects in wires are undesirable because they negatively alter the behavior of electronic systems.

The identification of defects is often a challenging task. First, it can be difficult to identify which electronic components share a defective wire. Second, it can be difficult to identify which particular wire is defective. Third, it can be difficult to identify which particular component or location along the wire is defective. These tasks can be particularly challenging in complex electronic systems, where thousands of wires may exist. The techniques described herein provide a practical method for identifying the presence and location of defects in complex systems.

FIG. 2A shows a schematic diagram of wire 203 and signal driver 202 in electrical communication with wire 203 . Signal driver 202 may be part of IC 104 . Signal driver 202 may include circuitry for generating signals to be transmitted over wires 203 . For example, the signal driver 202 may include amplifiers, buffers, digital-to-analog converters, and the like. In this example, wire 203 includes defect 204 . Defect 204 may be due to incorrect connections, poorly manufactured solder, damaged cables, and other possible causes. The existence and location of defect 204 may be unknown to the user/operator of the electronic system. By their nature, a defect may cause an open circuit, a short to ground, or may simply cause the impedance of the line to deviate from the expected value. In some embodiments, for example, the expected impedance of the line is 50Ω, but the presence of the defect raises the impedance above 50Ω, or reduces the impedance below 50Ω.

FIG. 2B shows a diagram of how the signal output by the signal driver 202 onto the wire 203 is transmitted along the wire. In this example, the signal driver 202 outputs a signal transition at t= _t0 . In this example, for illustration, it will be assumed that the signal driver is configured to output a transition from 0 to 1V (referred to as the "desired transition"), and will further assume that the output impedance of the signal driver, the characteristic impedance of the wire and the load's The input impedance is all 50Ω. In this case, the magnitude of the transition at the actual output at t = t ₀ is half the magnitude of the expected transition (ie, 0 to 0.5V). It should be understood that if the impedances do not match, the magnitude of the actual transition will not be half the magnitude of the desired transition.

At time t = t ₁ , the 0 to 0.5V transition has moved along wire 203 to position P1 , which is between signal driver 202 and defect 204 . At time t = t ₂ , the transition reaches the P2 location where defect 204 (in this case an open circuit) is located. When the transition reaches the defect, the amplitude of the transition increases to the amplitude (0 to 1V) of the output that the signal driver is configured to. This is because the signal actually reaches its expected voltage only when there is a reflection. In scenarios where no reflections are assumed to occur (such as in an infinitely long flawless cable), the magnitude of the transition will never reach the expected value.

Reflection at location P2 may occur because defect 204 causes discontinuities in wire impedance. The reflected transition may then return towards the signal driver 202 and may eventually reach the signal driver. Figure 2C shows a graph of the output of the signal driver 202, also referred to herein as the "TDR signal." In this embodiment, the defect is an open circuit. As mentioned above, the first transition (0 to 0.5V) occurs at t = t ₀ . At t = t ₂ , the transition reaches the circuit discontinuity and a reflection occurs. However, nothing happens at the output of the signal driver at this time. At time t = _t3 , the reflection reaches the signal driver and, as a result, a second transition (0.5V to 1V) occurs in the output of the signal driver.

Figure 2D shows an example where a defect causes the impedance of the line to rise above the characteristic impedance of the line. For example, if the characteristic impedance is 50Ω, the defect may raise the impedance above 50Ω, such as 70Ω or 80Ω. As shown, at t = t ₃ , the reflection from the defect reaches the signal driver. However, unlike the case where the defect is an open circuit, the second transition only reaches 0.6V instead of 1V. This is because defects have finite impedance.

Figure 2E shows an example with no defects along the line. As a result, no reflections occur and the signal remains at 0.5V even after t= _t3 .

Figure 2F shows an example where a defect causes the impedance of the line to drop below the characteristic impedance of the line. For example, if the characteristic impedance is 50Ω, the defect may reduce the impedance to less than 50Ω, such as 20Ω or 30Ω. As shown, at t = _t3 , the reflection from the defect reaches the signal driver. Because the impedance is less than the characteristic impedance, the amplitude of the signal after t= _t3 is less than 0.5V (0.3V in this example).

FIG. 2G shows an example where a defect causes a short circuit along the line. This can happen, for example, if the line is unintentionally coupled to the ground plane. In this case the impedance is zero and at t= _t3 the signal returns to zero.

Some embodiments are configured to determine the location of defect 204 based on the time it takes for the reflected waveform to return to the signal driver. For example, some embodiments are configured to determine the location of the defect 204 by determining the duration of the time interval Δt = t ₃ -t ₀ . In some embodiments, the defect-to-signal driver distance Δx can be determined by calculating Δx=vΔt, where v is the speed of the electrical signal traveling along the circuit path. The velocity v can be measured using different techniques known in the art. Additionally or alternatively, some embodiments are configured to determine (eg, measure or estimate) the impedance of the line, including the impedance of the defect or the defect itself. The value of the impedance can inform the user if the part needs to be replaced. For example, if a defect causes the impedance to deviate from the expected value by 5% (or another threshold) or less, the user can conclude that the part does not need to be replaced. On the other hand, if the defect causes the impedance to rise or fall by more than 5%, the user can conclude that the part may need to be replaced.

3 is a diagram illustrating a method of determining the location of a defect, according to some non-limiting embodiments. The figure shows the output of the signal driver 202 . As described above, the output of the signal driver includes a first transition at t=t ₀ and a second transition at t=t ₃ resulting from the reflection of the first transition at defect 204 . The location of the defect can be inferred by determining the occurrence of two events. The first event occurs when the first signal transition crosses (eg, upward in this embodiment, but also downward in other embodiments) the threshold V _th1 ; the second event occurs when the second transition crosses the threshold V th1 . exceeds the threshold V _th2 . In this specific example, V _th1 = 0.2V and V _th2 = 0.8V; however, any other suitable values for the thresholds may be used.

These events can trigger circuitry configured to measure the duration of the time interval. For example, the occurrence of a first event can trigger the output of the comparator to switch from one value to another (see Comparator Output 1); the occurrence of a second event can trigger the output of the comparator to switch from one value to another ( See comparator output 2). The location of the defect can be determined based on the duration of the interval between the time comparator output 1 toggles and the time comparator output 2 toggles. In at least some embodiments, this can be accomplished by counting clock cycles. It should be understood that while the methods described herein use two separate comparators to determine when a signal transition crosses respective thresholds, in other embodiments a single comparator may be used. For example, a single comparator may first receive a first threshold as a first input, and then receive a second threshold as a first input. The output of the signal driver may be provided to the second input of the comparator. Of course, other methods for measuring the duration of time intervals can be used. In some embodiments, the counter may count clock cycles, and the control circuit may be configured to determine which clock count the first and second events occurred on. In this example, the control circuit may determine that the first event occurred at clock cycle 3 and the second event occurred at clock cycle 9 . In some embodiments, the location of the defect can be calculated using the following equation: Δx=vΔt=vP(count2 - count1), where v is the velocity of the waveform, P is the period of the clock, and count1 (3 in this example) is the clock count when the first event occurred and count2 (9 in this case) is the clock count when the second event occurred. III. Non-digitized circuits for time domain reflectometry

FIG. 3, in conjunction with FIG. 4, illustrates an example of a system for implementing the method described in conjunction with FIG. 1, according to some non-limiting embodiments. Control circuit 302 may be connected to load 320 via wire 203 . As in the previous example, wire 203 includes defect 204 . The control circuit 302 may be configured to determine the location of the defect 204 along the wire. In some embodiments, the control circuit 302 may also include a digital word processor and a memory unit (not shown in FIG. 4 ).

Switch 312 can be closed in TDR mode and open in normal mode. In TDR mode, TDR measurements of the type described herein can be performed. In the normal mode, the signal driver 202 can transmit/receive data to/from the load 320 . For example, the signal "input" may be transmitted to the load 320 .

Control circuit 302 may also include comparator 304 , gates 305 and 306 and counter 308 . In this example, a single comparator is used to compare the first signal transition and the first threshold and the second signal transition and the second threshold. However, as described above, separate comparators can be used to perform both comparisons. The input of the comparator is labeled " _Vth " for receiving the threshold. A control circuit coupled to the input V _th of the comparator may be configured to set the value of the threshold. For example, the control circuit may first set _Vth to a first threshold, and after a certain period of time, may set _Vth to a second threshold. The time to set _Vth to the second threshold may be such that when a second signal transition is received, the transition is compared to the second threshold instead of the first threshold. Of course, the control circuit may not know in advance when the second signal transition will arrive, so it is difficult to estimate when to set _Vth to the second threshold. Nonetheless, this challenge can be overcome, for example, by determining that the first signal transition has crossed the first threshold (eg, 1 clock cycle, 2 clock cycles, or 3 clock cycles after crossing the first threshold) cycle, etc.) set _Vth to the second threshold.

The output of the comparator 304 may switch when the first signal transition 310 crosses a first threshold (referred to as a first event), and when the second signal transition 311 crosses a second threshold (referred to as a second event). For example, the output of the comparator may enable gate 306 between the first event and the second event, so that the counter only increments its clock cycle count between the first event and the second event. Although gate 306 is an AND gate (AND) in this example, other logic gates may be used to control the operation of the counter. In another example, the counter 308 may begin counting clock cycles at any point in time (eg, at t=0, as shown in FIG. 3 ) and reset when a reset signal (reset) is received. When the first signal transitions across the first threshold, a control circuit (not shown in FIG. 4 ) coupled to the counter 308 can determine which clock cycle the first event occurred to count. Then, when the second signal transitions across the second threshold, the control circuit may determine which clock cycle count the second event occurred on. The duration of the interval between the first and second events can then be determined based on these counts. For example, the duration of the interval can be determined by calculating the difference between the count of the second event and the count of the first event multiplied by the period of the clock.

A gate 305, in this example an exclusive-or gate (XOR), may be used to set the mode of operation. In some embodiments, eg, for the circuits described herein, two modes of operation are possible (of course, in other embodiments, there may be more than two modes). One mode of operation may be aimed at determining the location of a defect whose impedance is greater than the expected value (as in the case described in connection with Figure 3), and optionally determining the value of the impedance, this mode is referred to as the "high impedance mode". Another mode of operation may be aimed at determining the location of a defect whose impedance is less than the expected value, and optionally determining the value of the impedance, this mode is referred to as the "low impedance mode".

Because it may not be known in advance whether a defect has an impedance greater or less than an expected value, in some embodiments, the circuit may operate first in one mode and then in another. In this example, when the "mode" control signal is equal to zero, the circuit operates in high impedance mode. Vice versa, when the "mode" control signal is equal to 1, the circuit operates in low impedance mode. In high impedance mode, if gate 306 is active (eg, outputs a 1), counter 308 may count clock cycles. In the low impedance mode, if gate 306 is not active (eg, outputs a 0), counter 308 may count clock cycles. Examples of different modes of operation are described in Section IV of this application.

In some embodiments, the control circuit 302 may suffer from glitches. Because signal transitions may occur asynchronously with respect to clock edges, glitches may occur. As a result, the glitch may erroneously cause the counter 308 to count up. This situation is illustrated in Figure 5A, where the comparator's output toggles in response to crossing events are asynchronous compared to the occurrence of clock edges. This may falsely enable gate 306 for a short period of time, which in turn may cause counter 308 to falsely increment its count.

In some embodiments, one or more flip-flops may be used to avoid this problem, as shown in FIG. 5C according to some non-limiting embodiments. As shown in FIG. 5C , a pair of flip-flops (FFs) are inserted between the comparator 304 and the gate 306 . The flip-flop can be triggered by clkb, which is the inversion of clk. FIG. 5B is a diagram illustrating the output of gate 306 when the flip-flop shown in FIG. 5C is used. In this case, the output of gate 306 will not toggle until the edge of clkb is received, even if the crossover event does not occur synchronously with respect to the clock edge. As a result, the formation of burrs is prevented. Figure 5C shows two flip-flops between comparator 304 and gate 306, any other suitable number of flip-flops may be used. Flip-flops may additionally or alternatively be used to reset signals.

In some embodiments, IC 104 may include control circuitry 302 for each (or at least some) wires to which the IC is connected. In this way, multiple TDR measurements can be performed concurrently. IV. Operation Mode

As mentioned above, some of the circuits described herein can operate in two different modes: a high impedance mode or a low impedance mode. In the high impedance mode, the circuit can be laid out to determine the location and optional impedance value of the defect whose impedance (eg, the characteristic impedance of the wire) is greater than the expected value. Figure 3 is an example of operation in high impedance mode. Other examples are described below, and in some embodiments the fact that the threshold can be set differently depending on whether the impedance of the defect is higher or lower than the expected value may warrant two separate modes. a. High impedance mode

An example of the method of operation in the high impedance mode described herein in accordance with some non-limiting embodiments is shown in Figures 6A-6F. Specifically, Figure 6A shows an example where the defect is an open circuit (infinite resistance); Figure 6C shows an example where the defect's impedance (80Ω in this case) is greater than the expected 50Ω impedance; Figure 6E shows the defect's impedance ( 20Ω in this case) is less than the expected 50Ω impedance example. Figure 6B shows the output of the counter in clock cycles in the case of Figure 6A. Fig. 6D shows the output of the counter in the case of Fig. 6C. Fig. 6F shows the output of the counter in the case of Fig. 6E. It should be noted that while 50Ω is considered the expected impedance in these examples, other values are possible, as the invention is not limited to any particular value.

Referring first to Figures 6A-6B, the signal driver outputs a ₀ to 0.5V transition at t = t0 (ie, the first signal transition), and the signal driver outputs a 0.5 to 1V transition at t = _t3 (ie, the second signal transition). signal transition). In this case it is assumed that the counter has already started counting clock cycles at some time t= ₀ before t0. The circuit can be arranged such that when a 0 to 0.5V transition of the signal driver output crosses V _th2 , the counter is disabled and the clock cycle count (ie, the counter output) is registered (eg, stored in memory). In this embodiment, when the transition of the signal driver output 0 to 0.5V crosses V _th2 , the counter output is X1 (eg, 3 clock cycles). When the 0.5 to 1V transition of the signal driver output crosses V _th3 , the counter is disabled (the same counter or another counter, where, when the same counter, after the signal driver output crosses V _th2 , the counter is disabled from The count position of the count followed by the count), and the clock cycle count (i.e. the counter output) is registered (eg, stored in memory). In this embodiment, when the transition of the signal driver output 0.5 to 1V crosses V _th3 , the counter output is X2 (eg, 9 clock cycles). As discussed in connection with Figure 3, the location of the open circuit can be determined based on the difference between X2 and X1.

Referring now to Figures 6C-6D, in this embodiment the defect has an 80Ω impedance and the signal driver outputs a ₀ to 0.5V transition (ie, the first signal transition) at t=t0, the signal at t= _t3 The driver outputs a transition of 0.5 to 0.615V (ie, the second signal transition). When the 0 to 0.5V transition crosses V _th2 , the counter is disabled and the counter output is X1. Then, when the 0.5 to 0.615V transition crosses Vt _h3 , the counter is disabled and the counter output is X2. As in the previous case, the location of the defect can be inferred based on the difference between X2 and X1. It should be noted that, unlike the previous case, the voltage of the signal output by the signal driver after _t3 is less than 1V (0.615V in this example). The reason the voltage is less than 1V is that the impedance of the defect is limited. In fact, the voltage of the signal after _t3 depends on the impedance of the defect. Infinite impedance results in 1V. In contrast, a 50Ω impedance results in 0.5V. Any value in between produces a voltage between 0.5V and 1V.

The inventors have realized that the impedance value due to the defect can be determined by determining the magnitude of the signal driven output reflected at the defect. In the example of 6C, an additional threshold V _th4 is introduced. As an example, assume that V _th4 is set to 0.7V and V _th3 is set to 0.6V. Since the signal output by the signal driver never exceeds V _th4 , the counter is never disabled and continues to count after X2 is output. However, at some point the counter reaches its maximum value. For example, when the counter counts 1024 clock cycles, the 10-bit counter reaches its maximum value. When the counter reaches its maximum value, it is said to have overflowed.

Because the counter overflowed due to setting V _th4 to 0.7V, it can be deduced that the signal is less than 0.7V. At the same time, it can also be deduced that the signal is greater than V _th3 = 0.6V, since the transition from 0.5 to 0.615V crossed this threshold to trigger the counter output X2. As a result, it can be deduced that the signal output by the signal driver is between 0.6V and 0.7V after _t3 , and the impedance of the final defect is between 75Ω and 116Ω. It should be understood that the resolution with which the impedance value is determined can be increased by increasing the number of thresholds. In one example, ten different thresholds can be introduced between 0 and 1V in 0.1V steps.

The embodiments of Figures 6E-6F illustrate why high impedance mode may not be suitable for defects with impedances less than 50Ω (or other expected impedance values). In this embodiment, the impedance of the defect is 20Ω. As in the previous case, when the 0 to 0.5V transition of the signal driver output crosses V _th2 , the counter outputs X1. However, since the signal driver next outputs a 0.5 to 0.286V transition, Vth1 (less than _0.286V ) in the figure is never crossed. As a result, the counter overflows when it reaches its maximum value. Therefore, the second counter output is never generated and the location of the defect may not be determined. b. Low impedance mode

To determine the location of a defect whose impedance is less than the expected impedance, and optionally to determine the value of the impedance, the logic of the counter can be reversed. This can be accomplished, for example, by setting the mode input of gate 305 to 1. In high-impedance mode, the counter is enabled before the measurement starts, whereas in low-impedance mode, unlike in high-impedance mode, the counter is enabled by a specific event, such as a signal driver output crossing a predefined threshold. Examples of operation in the low impedance mode are shown in Figures 6G-6L according to some non-limiting embodiments. In particular, Figures 6G-6H refer to the case where the defect is a short circuit (zero impedance).

In Figures 6G-6H, the signal driver outputs a ₀ to 0.5V transition at t = t0 (ie, the first signal transition), and the signal driver outputs a 0.5 to 0 transition at t = _t3 (ie, the second signal transition). signal transition), the counter is disabled until t = t ₀ . When the 0 to 0.5V transition of the signal driver output crosses V _th1 , the counter is enabled and as a result begins to count clock cycles. At = t ₃ , the signal driver outputs a 0.5 to 0 transition that crosses V _th2 due to a shorted connection, the counter is disabled and as a result stops counting. In this case, the output Y1 of the counter represents the time elapsed between _t0 and _t3 , which is based on the position of the short-circuit connection. Essentially, in the low impedance mode, the counter can be seen as being configured to measure the width of the signal pulses.

In the example of Figures 6I-6J, the impedance of the defect is 20Ω. In Figures 6I-6J, the signal driver outputs a ₀ to 0.5V transition at t = t0 (ie, the first signal transition), and the signal driver outputs a 0.5 to 0.286V transition at t = _t3 (ie, the first signal transition). two signal transitions). As in the previous case, when the transition of the signal driver output 0 to 0.5V crosses V _th1 , the counter is enabled. The counter is then disabled when the transition of the signal driver output 0.5 to 0.286V crosses V _th2 , resulting in Y1. In some embodiments, if the value of V _th2 is set too low, the signal output by the signal driver may never fall below the threshold V _th2 , for example, in this embodiment, if V _th2 is set to 0.25V, However, the signal output by the signal driver will only reach 0.286V at a minimum, and the final counter overflows. In this case, it can be inferred that after _t3 , the signal output by the signal driver is between 0.5V and _Vth2 (eg, 0.25V), and the impedance is between 50Ω and 16.7Ω.

The embodiments of FIGS. 6K-6L illustrate why the low impedance mode may not be suitable for defects with impedances greater than 50Ω (or other expected impedance values). In this embodiment, the impedance of the defect is infinite (open circuit). As in the previous case, the counter is enabled when the first signal transition (eg, a 0 to 0.5V transition) of the signal driver output crosses V _th1 . However, the second signal transition of the signal driver output (eg, a 0.5V to 1V transition) never crosses _Vth2 (eg, 0.3V), and the resulting counter overflows, thus providing no useful information. V. Iterative operation method of time domain reflectometry

The embodiment of Figure 3 shows the case where the first and second transitions have the same amplitude (0.5V). This may be because the output impedance of the signal driver matches the characteristic impedance of the wire and the input impedance of the load. In this case, setting the thresholds to 0.2V and 0.8V, respectively, will ensure the correct operation of the above method and circuit. However, in other cases, the impedances may not be matched, which may cause the first and second signal transitions to have different amplitudes. Unfortunately, due to the unpredictable nature of impedance values, the extent to which the magnitude of the first signal transition differs from the magnitude of the second transition may not be known in advance. As a result, it may be difficult to set thresholds suitable for all situations.

To avoid this problem, an iterative TDR method can be used, in which the value of the threshold varies with time, and in which the location of the defect is determined statistically. This method is illustrated in Figures 7A-7C. Method 600 (FIG. 7A) may begin at act 602, where a first threshold is set to a particular value and a second threshold is set to another value. As shown in FIG. 7B, the first threshold may be initially set to a value of 1A, and the second threshold may be set to a value of 2A. Although the method is described in connection with a circuit operating in a high impedance mode, it should be understood that a similar method can be used in a low impedance mode.

At act 604, a first signal transition (eg, signal transition 310 in FIG. 4) can be generated and output on a wire for monitoring. At act 606, a second signal transition (eg, signal transition 311 in FIG. 4) may be received in response to a reflection of the first signal transition along the wire defect. At act 608, the occurrence of a first event may be determined based on the first signal transition crossing a first threshold. At act 610, the occurrence of a second event may be determined based on the second signal transition crossing a second threshold. At act 612, the value of the first threshold and/or the value of the second threshold may be changed. For example, as shown in FIG. 7B, the first threshold may be set to a value of 1B, and the second threshold may be set to a value of 2B. Then, actions 604-612 may be repeated N times, where N>0. In some embodiments, the values of the two thresholds are varied in the same iteration. In other embodiments, only the value of one threshold is changed during iterations, and the value of the other threshold may be changed independently during subsequent iterations.

7C is a bar graph showing the occurrence of a first event (a first signal transition across a first threshold) and a second event (a second signal transition across a second threshold) in high impedance mode, where the first The first and second thresholds are shown in Figure 7B. The histogram is plotted as a function of time in clock cycles.

At act 614, a first representative measure (eg, a majority vote or average) may be calculated based on the occurrence of the first crossover event, and a second representative measure may be calculated based on the occurrence of the second crossover event. These representative measurements may represent the average clock counts when the stride event occurred. For example, a representative measure can be calculated by calculating a majority vote or the mean of the distribution shown in Figure 7C (eg, arithmetic mean, geometric mean, median, etc.). In this example, the first and second representative measurements are equal to 10 and 115, respectively.

At act 616, the location of the defect may be determined based on the first and second representative measurements. For example, the location of the defect can be determined by calculating the difference between the second representative measurement and the first representative measurement. As shown in Figure 7C, this difference is equal to 105 clock cycles in this example. The location of the defect can be calculated using the following equation: Δx = vP(Δcount), where v is the velocity of the waveform, P is the periodicity of the clock, and Δcount is the difference between the first representative measurement and the second representative measurement Poor (105 in this example).

Figure 7D shows a representative set of thresholds for the low impedance mode, and Figure 7E shows the corresponding histogram. As shown, the histogram shows the occurrence of two consecutive events (the signal crossing the first threshold in a positive direction and the signal crossing the same threshold in a negative direction) and the absence of such an event (corresponding to threshold 2A). Based on the statistics of these events, the location of the defect can be determined (regardless of counter overflow). VI. Digitization Method and Circuit for Time Domain Reflectometry

When a user wishes to locate a defect along one or more wires of an electronic system, the TDR method described above may be sufficient. But in other cases, in addition to or as an alternative to location, the user may wish to determine other characteristics of the defect, including, for example, the electrical impedance of the defect and/or the nature of the defect (e.g. whether the defect is a short, open, poorly soldered connection , unusually high impedance pins, etc.).

The inventors have realised that in this case it may be desirable to profile the waveform of the TDR signal, which may include sampling and digitizing the TDR signal. A representative circuit for performing time domain reflectometry in this manner is shown in Figure 8A, according to some embodiments. IC 802 can be designed to operate in at least two modes. In transmit mode, IC 802 is configured to generate data (eg, in bits) representing information and transmit the data to a receiver. The data may represent, for example, textual information, visual information (eg, video or images), audio information, location information, numerical information, financial information, and the like. In TDR mode, IC 802 is configured to perform time domain reflectometry. Thus, the same hardware of IC 802 can be used for two purposes - to transmit data to another electronic device circuit and to perform time domain reflectometry - allowing testing without disrupting the operation of the IC.

IC 802 includes transmitter 804 , signal driver 202 , switch 312 , analog-to-digital converter (ADC) 808 , clock selection circuit 810 , reference voltage generator 812 , comparator 814 and time domain reflectometry (TDR) circuit 820 . In transmit mode, the transmitter 804 generates data representing information to be transmitted to the receiver. Transmitter 804 may be designed to operate according to any communication protocol, including, for example, the "56G" standard (operating at 56Gb/s) and the "112G" standard (operating at 112Gb/s). Other communication standards are also possible. In some embodiments, the transmitter is designed to transmit data at speeds in excess of 1Gb/s. In transmit mode, switch 312 may be open.

As described above in connection with FIG. 2A , signal driver 202 may include amplifiers, buffers, digital-to-analog converters, or other circuitry for outputting signals to wires 203 . The output of the signal driver 202 to the wire 203 is received from the transmitter 804 . The data receiver 830 is located at the other end of the wire 203 relative to the signal driver 202 . Data receiver 830 may be part of any electronic circuit, and may include amplifiers, filters, analog-to-digital converters, processors, memory, and the like.

In TDR mode, transmitter 804 generates signal transitions for performing time domain reflectometry. For example, transmitter 804 outputs signal transitions similar to those described above in connection with Figure 2B. Signal driver 202 outputs a first signal transition 310 onto wire 203 . When a defect 204 is present on the wire, a second signal transition 311 occurs in response to the reflection of the first signal transition 310 at the defect 204 . Among other factors, the magnitude of the second signal transition 311 may depend on the nature of the signal, as described above in connection with Figures 2C-2G.

In TDR mode, switch 312 is closed. As a result, the signal present on wire 203 is coupled to ADC 808 , said signal including first signal transition 310 and second signal transition 311 . ADC 808 is configured to sample and digitize a received signal comprising signal transitions 310 and 311, or at least a portion of the signal.

In some embodiments, ADC 808 is configured to operate at a relatively low frequency, thereby reducing ADC circuit complexity and power consumption. For example, ADC 808 may sample at a frequency of less than 1/(t ₃ -t ₀ ) (see FIGS. 2D-2G ). However, the ADC 808 can be controlled to sample the signal at a resolution high enough to analyze the portion of the signal that transitions. In some embodiments, this may be done by generating multiple instances of the first signal transition 310 (thereby generating multiple instances of the second signal transition 311 ), and for each instance a different clock signal may be used Sample the signal. In some embodiments, the clock signal used for the different instances of the sampled signal may be a delayed replica of the master clock signal. The delay between clock signals may be small enough to obtain a high overall sampling resolution.

The timing at which the ADC 808 samples the signal is controlled by the clock selection circuit 810 . Clock selection circuit 810 is configured to select one of a plurality of selectable clock signals. For example, clock selection circuit 810 may receive a master clock signal from clock generator 811 and may output one of a plurality of clock signals Φ ₀ . . . Φ _N , each such clock signal having a different delay relative to the master clock signal. For example, the clock signal Φ ₀ can be obtained by introducing no delay, the clock signal Φ ₁ can be obtained by delaying the master clock signal by δt, the clock signal Φ ₂ can be obtained by delaying the master clock signal by 2δt, and the clock signal Φ _N can be obtained by Obtained by delaying the master clock signal by Nδt, where N is an integer greater than one. In some embodiments, the delay δt is less than t ₃ -t ₀ .

Therefore, the clock selection circuit 810 can select one of the following optional delays: 0, δt, 2δt . . . Nδt, and output the clock signal according to the selected delay. It should be understood that although the delay increases in a linear fashion in this example, not all embodiments are so limited, as the delay may be increased in any other suitable manner.

According to some non-limiting embodiments, FIG. 8B shows an example of an output clock signal according to a selected delay. Clock signals Φ ₀ , Φ ₁ and Φ _N are copies of the same master clock, but delayed by different times. In this example, the rising edge of clock signal Φ ₀ occurs at t = t ₀ , t = T + t ₀ , 2T + t ₀ , etc. (where T represents the period of the clock signal), the rising edge of clock signal Φ ₁ occurs at Now t = t ₁ , t = T + t ₁ , 2T + t ₁ , etc., and the rising edge of the clock signal Φ _N occurs at t = t _N , t = T + t _N , 2T + t _N , etc.

The ADC 808 samples the signal at a timing determined by the selected clock signal (eg, on the rising or falling edge of the selected clock signal). The output of ADC 808 is a plurality of values representing the voltage of the signal at the time of sampling. For example, when clock signal Φ0 is selected, ADC 808 produces a first value at t _{= t0} , a second value at t=T+ _t0 , a third value at t=2T+ _t0 , and so on.

Comparator 814 compares the value produced by ADC 808 to a reference voltage. The output of the comparator 814 is a 1 if the output of the ADC 808 exceeds the reference voltage, and a 0 otherwise (reverse logic may optionally be used).

Reference voltage generator 812 selects a reference voltage to be compared with the output of ADC 808 . In some embodiments, the reference voltage generator 812 selects a reference voltage from a plurality of selectable voltages V ₀ . . . V _M , where M is an integer greater than one. The larger the value of M, the higher the resolution of the circuit's determination of the voltage of the signal. The comparator 814 outputs a plurality of output values. The first output value is obtained by comparing the value sampled at t = t ₀ with the selected reference voltage, and the second output value is obtained by comparing the value sampled at t = T + t ₀ with the selected reference voltage. The second output value is obtained by comparing the value sampled at t=2T+ _t0 with the selected reference voltage, and so on. The output value essentially represents a digitized version of the signal received by ADC 808 .

The output of the comparator is provided as the input of TDR circuit 820 . The TDR circuit 820 may be programmed to characterize the defect based on the output value. For example, the TDR circuit 820 may be programmed to determine the location of the defect based on the difference between the time of the second signal transition 311 and the time of the first signal transition 310 . Additionally or alternatively, the TDR circuit 820 may be programmed to determine the magnitude of the impedance of the defect based on the voltage of the signal following the second signal transition 311 . Additionally or alternatively, the TDR circuit 820 may be programmed to determine from the voltage of the signal following the second signal transition 311 whether the defect is a short circuit, an open circuit, a poorly soldered connection, an abnormally high impedance pin.

8C illustrates a flowchart of an exemplary method for characterizing a defect, according to some non-limiting embodiments. The method of FIG. 8C may be performed using the integrated circuit of FIG. 8A, although any other suitable circuit may be used. The actions of method 850 may be performed in the order shown in Figure 8C, or in any other order. Method 850 begins at act 852 in which a clock signal is selected from a plurality of selectable clock signals. The plurality of clock signals may be delayed versions of the master clock, wherein each clock signal is delayed by a different amount. In some embodiments, selecting the clock signal includes selecting a delay and delaying the master clock signal by an amount corresponding to the selected delay.

At act 854, a reference voltage is selected from the M selectable voltages. The selectable voltage may be, for example, between 0 and V _DD or between -V _DD and V _DD .

At act 856, a signal is obtained by generating a first signal transition on the wire and receiving a second signal transition in response to a reflection of the first signal by the defect. Thus, the signal includes a first signal transition and a second signal transition.

At act 858, a plurality of values are generated by sampling the selected clock signal using the signal. For example, a first value is generated at or after the first edge (rising or falling) of the selected clock signal, a second value is generated at or after the second edge of the selected clock signal, at A third value is generated at or after the third edge of the selected clock signal, and so on.

At act 860, a plurality of output values are generated by comparing the plurality of values to the selected reference voltage. For example, the first output value is generated by comparing the first value of act 858 to the selected reference voltage, the second output value is generated by comparing the second value of act 858 to the selected reference voltage, and the second output value is generated by comparing the second value of act 858 to the selected reference voltage. The third value of act 858 is compared to the selected reference voltage to generate a third output value, and so on.

Method 850 may be performed iteratively. For example, the method 850 can loop an optional reference voltage, and can loop an optional clock signal. In some embodiments, as shown in the example of FIG. 8C , the loop-selectable reference voltage is an inner loop and the loop-selectable clock signal is an outer loop, in other embodiments, the loop may be The selected reference voltage can be the outer loop, and the loop-selectable clock signal is the inner loop.

Action 862 represents cycling the reference voltage. At act 862, a reference voltage that is different from the reference voltage selected in the previous iteration is selected. Subsequently, another signal is obtained (act 856), a plurality of values are generated (act 858), and a plurality of output values are generated (act 860). The cycle of the reference voltage is repeated M times, where M is the number of selectable reference voltages. Optionally, cycling on the reference voltage may not include act 856, as shown by the dashed line in Figure 8C.

Action 864 represents cycling of the clock signal. At act 864, a different clock signal than the one selected at the previous iteration is selected. Subsequently, a reference voltage is selected (act 854), another signal is obtained (act 856), a plurality of values are generated (act 858), a plurality of output values are generated (act 860), and the cycle of the reference voltage is repeated M times again. The cycle of the clock signal repeats N times, where N is the number of optional clock signals. Thus, method 850 includes MxN iterations.

At act 866, a feature of the defect is determined based on the plurality of output values obtained through the MxN iterations. Examples of characteristics that may be determined at act 866 include the location of the defect, the impedance of the defect, and the nature of the defect. In some embodiments, the location of the defect may be determined based on the elapsed time between the first signal transition and the second signal transition. In some embodiments, the impedance of the defect may be determined based on the relationship of the voltage level after the second signal transition relative to the voltage level before the second signal transition.

8D is a diagram illustrating how a signal is sampled over a plurality of clock cycles, over a plurality of cycles of a selectable clock signal, and over a plurality of cycles of a reference voltage, according to some embodiments. Tables 8E-8H represent the outputs of comparator 814. In this non-limiting example, the optional clock signals are Φ ₀ , Φ ₁ , Φ ₂ and Φ ₃ , and the optional reference voltages are V ₀ , V ₁ , V ₂ and V ₃ , although any other can be used Appropriate clock signal and reference voltage.

Referring to FIG. 8D and Table 8E, the control circuit first selects the clock signal Φ ₀ and the reference voltage V ₀ . In this cycle, the ADC 808 obtains the value A ₀ from the first instance of the signal on the first clock cycle, the value B ₀ on the second clock cycle, and the value C ₀ on the third clock cycle. A value greater than the selected reference voltage causes the comparator to generate a 1, while a value less than the selected reference voltage causes the comparator to generate a 0 (the opposite logic is also possible). Thus, as shown in the first row of the table of Figure 8E, when compared to the reference voltage _V0 , the comparator 814 produces the following output values: 1 (at the first clock cycle), 1 (at the second clock cycle) ) and 1 (on the third clock cycle).

Subsequently, a different reference voltage is selected: V ₁ . This time, as shown in the second column of the table of Figure 8E, the output values are: 0 (at the first clock cycle), 1 (at the second clock cycle), and 1 (at the third clock cycle). The control circuit continues to cycle through the optional reference voltage. Subsequent output values are reflected in the last two columns of the table of Figure 8E.

Subsequently, the control circuit selects a different clock signal Φ ₁ and cycles the reference voltage. The output values when this clock signal is selected are shown in the table of Fig. 8F. Subsequently, the control circuit selects a different clock signal Φ ₂ and cycles the reference voltage. _The output values when the clock signal Φ2 is selected are shown in the table of Fig. 8G. Finally, the control circuit selects a different clock signal Φ ₃ and cycles the reference voltage. _The output values when the clock signal Φ3 is selected are shown in the table of Fig. 8H.

The output values of the tables of Figures 8E-8H are stored in the memory of the control circuit and used to reconstruct the shape of the signal in the digital domain. The reconstructed signal can be post-processed to determine any features of interest to the user, such as the location, impedance or nature of the defect.

As described above, some embodiments are directed to methods that include loop settings to select different clock signals with different delays at each loop iteration. In this way, the portion of interest of the signal can be scanned at a relatively high resolution despite the use of a relatively low speed clock. However, in other embodiments, a plurality of replicas of the signal may be scanned, where each replica includes a single clock signal and each replica has a different delay. Thus, instead of iterating over multiple selectable clock cycles, such a method iterates over multiple selectable TDR signals.

Nonetheless, the inventors have realized that iterating alternative clock signals with different delays can reduce costs associated with integrated circuit design and manufacturing, as compared to methods of iterating TDR signals with different delays. This is especially noticeable in systems where the transmitter hardware acts as both a data transmitter and a TDR transmitter. Indeed, in these cases, enabling the integrated circuit to iterate over TDR signals with different delays involves redesigning at least a portion of the transmitter hardware that has been designed to perform the data transfer. Vice versa, enabling an IC to iterate over clock signals with different delays may simply include stamping a transmitter hardware template on the IC and adding circuitry next to it for selecting different clock signals. This approach is more cost-effective because its implementation may rely on the pre-existence of no transmitter hardware templates.

Although the present invention is disclosed above with preferred embodiments, it is not intended to limit the scope of the present invention. Anyone with ordinary knowledge in the technical field can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope of the patent application.

100: Printed Circuit Board 102: Package 104,802: Integrated Circuits 110,120: Metal Wire 112, 122, 129: Connectors 114,124: Contacts 116, 126: Cable 125: Bottom plate 128: Metal traces 202: Signal Driver 204: Defect 203: Wire 302: Control circuit 308: Counter 306, 305: Doors 304,814: Comparator 312: switch 310, 311: Signal Transition 320: load 602,604,606,608,610,614,616,612,852,854,856,858,860,866,862,864: Action 804: Transmitter 820: Time Domain Reflectometry Circuit 812: Reference Voltage Generator 808: Analog to Digital Converter 810: Clock selection circuit 811: Clock Generator 830: Data Receiver 850: Method

1 illustrates an example of an electronic system including a plurality of electronic components interconnected by electrical wires, according to some non-limiting embodiments. 2A shows a schematic diagram of a signal driver 202 and a wire 203 including a defect, according to some non-limiting embodiments. 2B shows a schematic diagram of how the signal transitions output by the signal driver of FIG. 2A travel along a wire in accordance with some non-limiting embodiments. 2C shows an example of the output of the signal driver 202 in the event of an open circuit in the wire, according to some non-limiting embodiments. 2D illustrates an example of the output of a signal driver when a defect exists with an impedance higher than the characteristic impedance of the wire, according to some non-limiting embodiments. FIG. 2E shows an example with no defects along a wire, according to some non-limiting embodiments. 2F illustrates an example of the output of a signal driver when a defect exists with an impedance less than the characteristic impedance of the wire, according to some non-limiting embodiments. 2G shows an example of the output of the signal driver when there is a short circuit in the wires, according to some non-limiting embodiments. 3 illustrates a diagram of a method for determining defect locations, according to some non-limiting embodiments. 4 illustrates a circuit diagram of an example of a control circuit implementing the technique shown in FIG. 3, according to some non-limiting embodiments. 5A shows a graph of the output of a gate in the presence of a glitch, according to some non-limiting embodiments. 5B shows a graph of the output of a gate that has been deburred, according to some non-limiting embodiments. FIG. 5C shows a circuit diagram of another example of a control circuit implementing the technique shown in FIG. 3 in accordance with some non-limiting embodiments. 6A shows a graph of a signal driver output in the presence of an open circuit, according to some non-limiting embodiments. 6B shows a graph of the output of the counter when the output of the signal driver of FIG. 6A is generated, according to some non-limiting embodiments. 6C shows a graph of the output of a signal driver in the presence of a defect with 80Ω impedance, according to some non-limiting embodiments. 6D shows a graph of the output of the counter when the output of the signal driver of FIG. 6C is generated, according to some non-limiting embodiments. 6E shows a graph of the signal driver output in the presence of a defect with a 20Ω impedance, according to some non-limiting embodiments. 6F shows a graph of the output of the counter when the output of the signal driver of FIG. 6E is generated, according to some non-limiting embodiments. 6G shows a graph of the output of a signal driver in the presence of a short circuit, according to some non-limiting embodiments. 6H shows a graph of the output of the counter when the output of the signal driver of FIG. 6G is generated, according to some non-limiting embodiments. 6I shows a graph of the output of another signal driver in the presence of a defect with 20Ω impedance, according to some non-limiting embodiments. 6J shows a graph of the output of the counter when the output of the signal driver of FIG. 6I is generated, according to some non-limiting embodiments. 6K shows a graph of the output of a signal driver in the presence of an open circuit, according to some non-limiting embodiments. 6L shows a graph of the output of the counter when the output of the signal driver of FIG. 6K is generated, according to some non-limiting embodiments. 7A illustrates a flowchart of a representative method of determining the location of a defect along a wire, according to some non-limiting embodiments. 7B shows a graph of the output of a representative signal driver and a plurality of thresholds in accordance with some non-limiting embodiments. 7C shows a histogram across the occurrence of events, according to some non-limiting embodiments. 7D shows a graph of the output of another representative signal driver and a plurality of thresholds in accordance with some non-limiting embodiments. 7E illustrates another histogram across the occurrence of events, according to some non-limiting embodiments. 8A illustrates an example of a control circuit including an analog-to-digital converter, according to some non-limiting embodiments. 8B illustrates an example of a set of selectable clock signals in accordance with some non-limiting embodiments. 8C illustrates a flowchart of an exemplary method for characterizing a defect, according to some non-limiting embodiments. 8D shows a diagram of how a signal is sampled over a plurality of clock cycles, over a plurality of cycles of an optional clock signal, and over a plurality of cycles of a reference voltage, according to some non-limiting embodiments. 8E-8H illustrate a table of a plurality of output values according to some non-limiting embodiments.

850: Method

852,854,856,858,860,866,862,864: Action

Claims (18)

A method of characterizing a defect in an electrical wire of an electronic system, comprising: (i) selecting a clock signal from a plurality of selectable clock signals, wherein the plurality of selectable clock signals represent delayed versions of a master clock signal; (ii) selecting a reference voltage from a plurality of selectable reference voltages; (iii) obtaining a signal by: generating a first signal transition on the wire; and receiving a reflection of the first signal transition in response to a defect while a second signal transition occurs; (iv) by sampling said signal comprising said first signal transition and said second signal transition using said selected clock signal to generate a plurality of values; (v) by The plurality of values are compared with the selected reference voltages to generate a plurality of output values; and (vi) determining a characteristic of the defect based on the plurality of output values. The method for characterizing a defect in an electrical wire of an electronic system as claimed in claim 1, wherein the selected reference voltage is a first reference voltage, the method further comprising: (vii) selecting a reference voltage different from the first reference a second reference voltage for the voltage; and (viii) repeats (iii)-(vi). The method of characterizing a defect in an electrical wire of an electronic system of claim 2, wherein the selected clock signal is a first clock signal, the method further comprising: (ix) selecting a different clock than the first clock a second clock signal of the signal; and (x) repeats (ii)-(vi). The method of characterizing a defect in an electrical wire of an electronic system as recited in claim 1, wherein said selecting a clock signal from a plurality of selectable clock signals comprises: selecting a delay from a plurality of selectable delays, and combining The master clock signal delay is relative to the selected delay appropriate amount. The method of determining a characteristic of a defect in an electrical wire of an electronic system of claim 1, wherein the determining the characteristic of the defect based on the plurality of output values comprises: determining the characteristic of the defect based on the plurality of output values Location. The method of determining a characteristic of a defect in an electrical wire of an electronic system of claim 1, wherein the determining the characteristic of the defect based on the plurality of output values comprises: determining the characteristic of the defect based on the plurality of output values impedance. The method for characterizing a defect in an electrical wire of an electronic system as recited in claim 1, wherein the determining the characterizing of the defect based on the plurality of output values comprises: determining whether the defect is a short circuit or an open circuit. A method of characterizing a defect in an electrical wire of an electronic system, said generating a first signal transition on said electrical wire being performed by using a signal driver, and wherein said method further comprises: generating a bits of data representing information to be sent to a data receiver; and outputting the data onto the wire using the signal driver. An apparatus for characterizing defects in electrical wiring of an electronic system, comprising: an integrated circuit configured to: (i) select a clock signal from a plurality of optional clock signals, wherein the plurality of optional clock signals the clock signal represents a delayed version of the master clock signal; (ii) select a reference voltage from a plurality of selectable reference voltages; (iii) obtain the signal by generating a first signal transition on the wire; and receiving a second signal transition that occurs in response to a reflection of the first signal transition by a defect; (iv) pairing the signal including the first signal transition and the second signal transition by using the selected clock signal sampling to generate a plurality of values; (v) generating a plurality of output values by comparing the plurality of values with the selected reference voltages; and (vi) determining a magnitude of the defect based on the plurality of output values feature. The apparatus for characterizing defects in electrical wiring of an electronic system as recited in claim 9, wherein the selected reference voltage is a first reference voltage, and wherein the integrated circuit is further configured to: (vii) select a second reference voltage different from the first reference voltage; and (viii) repeating (iii)-(vi). The apparatus for characterizing defects in electrical wiring of an electronic system of claim 10, wherein the selected clock signal is a first clock signal, wherein the integrated circuit is further configured to: (ix) select a second clock signal different from the first clock signal; and (x) repeating (ii)-(vi). The apparatus for characterizing defects in electrical wires of an electronic system as recited in claim 9, wherein said selecting a clock signal from a plurality of selectable clock signals comprises: selecting one delay from a plurality of selectable delays , and delays the master clock signal by an amount corresponding to the selected delay. The apparatus for characterizing a defect in an electrical wire of an electronic system as recited in claim 9, wherein the determining the characterizing of the defect based on a plurality of output values comprises: determining a characteristic of the defect based on the plurality of output values impedance. A feature for determining defects in electrical wiring of an electronic system as claimed in claim 9 The apparatus of , wherein the integrated circuit is further configured to: generate data comprising a plurality of bits, the data representing information to be sent to a data receiver; and output the data onto the wire. An apparatus for characterizing defects in wires of an electronic system, comprising: an integrated circuit comprising: a transmitter; a signal driver coupled to the transmitter and the wire; an analog-to-digital converter, coupled to the wire; a clock selection circuit, coupled to the analog-to-digital converter, the clock selection circuit is configured to select a clock signal from a plurality of selectable clock signals; a reference voltage generator, configured as selecting a reference voltage from a plurality of selectable reference voltages; a comparator including a first input coupled to the analog-to-digital converter and a second input coupled to the reference voltage generator; and time domain reflectometry The circuit is coupled to the comparator. The apparatus for characterizing defects in electrical wiring of an electronic system as recited in claim 15, wherein the clock selection circuit is configured to select a delay from a plurality of selectable delays, and to select the selected delay based on the selected delay the clock signal. The apparatus for characterizing defects in electrical wiring of an electronic system as recited in claim 15, further comprising a switch coupling the analog-to-digital converter to the electrical wiring. The apparatus for characterizing defects in electrical wiring of an electronic system as recited in claim 15, wherein the transmitter is configured to output a plurality of bits of information.

Images