TWI766061B - switching regulator - Google Patents

Abstract

A switching regulator that generates a predetermined output voltage by a switching element connected between a power supply terminal and one end of an inductor, and includes an error amplifier circuit that measures a difference between a voltage based on the output voltage and a first reference voltage Amplify, and output the error voltage; PFM comparison circuit, compare the error voltage with the second reference voltage, and output the comparison result signal of the first level or the second level; The oscillation circuit, when the comparison result signal is the first level outputting a clock signal of a predetermined frequency, and stopping the output of the clock signal when the comparison result signal is the second level; and a PWM conversion circuit for turning on the switching element with a desired pulse width based on the error voltage and the output of the oscillation circuit, the switch The regulator sets an offset for a predetermined period to the input of the PFM comparison circuit in response to the comparison result signal being switched from the second level to the first level.

Description

switching regulator

The present invention relates to a switching regulator.

FIG. 5 shows a circuit diagram of a conventional switching regulator 500 .

The conventional switching regulator 500 includes: a power terminal 501 , a ground terminal 502 , a reference voltage source 510 , an error amplifier circuit 511 , a reference voltage source 512 , a pulse frequency modulation (PFM) comparison circuit 513 , and an oscillator circuit 514 , P-channel Metal Oxide Semiconductor (P-channel Metal Oxide Semiconductor, PMOS) transistor 530, N-channel Metal Oxide Semiconductor (NMOS) transistor 531, inductor 540, capacitor 541, Resistor 543 and resistor 544 , output terminal 542 , and include a current-voltage conversion circuit 520 , a slope voltage generation circuit 521 , a pulse width modulation (PWM) comparison circuit 522 , a control circuit 523 and a reverse current detection circuit The PWM conversion circuit 550 of 524 is formed by these connections as shown.

The error amplifier circuit 511 compares the voltage VFB obtained by dividing the output voltage VOUT of the output terminal 542 by the resistor 543 and the resistor 544 with the reference voltage VREF1 of the reference voltage source 510, and outputs the error voltage VERR.

The current-voltage conversion circuit 520 converts the source current of the PMOS transistor 530 into a voltage, and outputs the voltage to the ramp voltage generation circuit 521 . The ramp voltage generating circuit 521 adds a sawtooth wave to the output of the current-voltage converting circuit 520 and outputs the voltage VCS. The PWM comparison circuit 522 compares the error voltage VERR with the voltage VCS, and outputs the comparison result signal CMPW to the control circuit 523 .

The PFM comparison circuit 513 compares the reference voltage VREF2 of the reference voltage source 512 with the error voltage VERR, and outputs the comparison result signal CMPF to the oscillation circuit 514 . The oscillation circuit 514 oscillates (is enabled) at a predetermined frequency when the comparison result signal CMPF is at a low level, and outputs a clock signal as the output signal CLK. Furthermore, the oscillation circuit 514 stops oscillation (disables) when the comparison result signal CMPF is at a high level, and fixes the output signal CLK at a low level.

The reverse current detection circuit 524 compares the drain voltage and the source voltage of the NMOS transistor 531 , and if the drain voltage is higher than the source voltage, outputs a reverse current detection signal to the control circuit 523 .

The control circuit 523 controls the on/off of the PMOS transistor 530 and the NMOS transistor 531 according to each input signal.

The inductor 540 and the capacitor 541 smooth the voltage VSW output from the drain of the PMOS transistor 530 .

With such a configuration, a negative feedback loop functions, and the switching regulator 500 operates so that the voltage VFB becomes equal to the reference voltage VREF1 to generate the output voltage VOUT to the output terminal 542 .

In the switching regulator 500 , the PWM (Pulse Width Modulation) operation and the PFM (Pulse Frequency Modulation) operation are switched as follows according to the magnitude of the current (load current) flowing in the load connected to the output terminal 542 .

When the load current is large, the error voltage VERR rises to compensate for the drop of the output voltage VOUT. Therefore, the error voltage VERR becomes stably larger than the reference voltage VREF2, and the oscillation circuit 514 continues to output a clock signal of a predetermined frequency as the output signal CLK. In synchronization with the rise of the clock signal, the PWM conversion circuit 550 turns on the PMOS transistor 530 and turns off the NMOS transistor 531 . At this time, the pulse width of the signal for controlling the on-time of the PMOS transistor 530 is determined by the PWM conversion circuit 550 . In this way, when the load current is large, the switching regulator 500 becomes the PWM operation.

After that, when the load current becomes smaller from the above state, the state in which the error voltage VERR is stably larger than the reference voltage VREF2 continues at the time point just after the load current becomes smaller. However, since the load current has become smaller, the drop of the output voltage VOUT due to the load current is small, and the increase of the output voltage VOUT due to turning on the PMOS transistor 530 becomes larger. Therefore, the error voltage VERR falls so as to compensate for the rise of the output voltage VOUT, and becomes a voltage value lower than the reference voltage VREF2. As a result, the PMOS transistor 530 is turned off, and the output voltage VOUT gradually decreases.

And, when the error voltage VERR gradually rises and becomes larger than the reference voltage VREF2, the oscillation circuit 514 outputs the clock signal as the output signal CLK. In synchronization with the rise of the clock signal, the PWM conversion circuit 550 turns on the PMOS transistor 530 and turns off the NMOS transistor 531 . At this time, since the load current is small, since the PMOS transistor 530 is turned on, the output voltage VOUT immediately exceeds the desired voltage value, so the error voltage VERR decreases. Then, the PWM conversion circuit 550 turns off the PMOS transistor 530 and turns on the NMOS transistor 531. Furthermore, the oscillation circuit 514 fixes the output signal CLK to a low level. In this way, when the load current is small, the oscillation circuit 514 oscillates and stops repeatedly. That is, the switching regulator 500 becomes the PFM operation.

As described above, the conventional switching regulator 500 compares the error voltage VERR with the reference voltage VREF2 to switch between the PWM operation and the PFM operation, thereby switching to the PFM operation when the load current is small, thereby improving the power conversion efficiency (For example, refer to Patent Document 1). [Prior Art Document] [Patent Document]

[Patent Document 1] Japanese Patent Laid-Open No. 2010-68671 [Problems to be Solved by the Invention]

However, the conventional switching regulator 500 has the following problem: during the PFM operation, the switching operations of the PMOS transistor 530 are continuously generated for many times, so that the ripple voltage of the output voltage VOUT increases. .

The reason for this is that the timing of disabling the oscillation circuit 514 is delayed due to the response delay of the PFM comparison circuit 513 , so that the output of the oscillation circuit 514 outputs the clock signal multiple times.

The reason for this will be described in detail below with reference to FIG. 6 .

6 shows the waveforms of the inductor current IL, the output voltage VOUT, the voltage VFB, the error voltage VERR, the comparison result signal CMPF, and the output signal CLK of the oscillation circuit 514 flowing in the inductor 540 of the conventional switching regulator 500 .

At time t0, the comparison result signal CMPF is at a high level, and the PMOS transistor 530 stops switching. Along with the decrease of the output voltage VOUT, the voltage VFB also gradually decreases. When the voltage VFB is lower than the reference voltage VREF1, the error voltage VERR gradually increases. When the error voltage VERR exceeds the reference voltage VREF2 at time t1 and the comparison result signal CMPF switches to a low level, the clock signal is output as the signal CLK, the PMOS transistor 530 is turned on, and the inductor current IL flows. Thus, when the output voltage VOUT gradually rises and exceeds the desired voltage value VTG, the error voltage VERR gradually decreases. And, at time t2, the error voltage VERR is lower than the reference voltage VREF2. Here, the comparison result signal CMPF is not switched to the high level immediately due to the response delay of the PFM comparison circuit 513, but is switched to the high level at time t3 after the delay time td has elapsed from time t2. As a result, between the time t2 and the time t3, the redundant clock signal is output from the signal CLK, and the PMOS transistor 530 performs the switching operation redundantly. Therefore, the ripple voltage of the output voltage VOUT becomes large.

In addition, if the inductor 540, the capacitor 541, etc. are set in advance so that the rising method when the output voltage VOUT rises is steep, the time when the error voltage VERR rises and exceeds the reference voltage VREF2 and starts to fall becomes earlier. Therefore, the timing at which the comparison result signal CMPF is switched to the high level is advanced, so that the output of an unnecessary clock signal can be prevented. However, when the method of increasing the output voltage VOUT is made steeper, the rising width of the output voltage VOUT due to the first switching operation of the PMOS transistor 530 increases, and as a result, the ripple voltage increases.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a switching regulator capable of reducing the ripple voltage of the output voltage during PFM operation. [Means of Solving Problems]

In the switching regulator of the present invention, a switching element connected between a power supply terminal and one end of the inductor generates a regulation from the power supply voltage supplied to the power supply terminal to the output terminal to which the other end of the inductor is connected. The switching regulator includes: an error amplifying circuit that amplifies the difference between the voltage based on the output voltage and the first reference voltage, and outputs an error voltage; a PFM comparison circuit that compares the error voltage with the second reference voltage The reference voltage is compared, and a comparison result signal of the first level or the second level is output; the oscillator circuit outputs a clock signal of a predetermined frequency when the comparison result signal is the first level, and the comparison result signal Stopping the output of the clock signal on time for the second bit; and a PWM conversion circuit that turns on the switching element with a desired pulse width based on the error voltage and the output of the oscillation circuit, the switching regulator In response to the comparison result signal being switched from the second level to the first level, an offset for a predetermined period is set to the input of the PFM comparison circuit. [Effect of invention]

According to the switching regulator of the present invention, by providing an offset of a predetermined period to the input of the PFM comparison circuit, an effect of compensating for the response delay of the PFM comparison circuit is obtained, and unnecessary switching operations of the switching elements during the PFM operation can be suppressed. Thereby, the ripple voltage of the output voltage can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a switching regulator 100 according to the first embodiment of the present invention.

The switching regulator 100 of the present embodiment includes a power supply terminal 101, a ground terminal 102, a reference voltage source 110, an error amplifier circuit 111, a reference voltage source 112, a PFM comparison circuit 113, an oscillation circuit 114, and a PMOS transistor 130 (also referred to as a PMOS transistor 130). "Switching element"), NMOS transistor 131 (also referred to as "synchronous rectification element"), inductor 140, capacitor 141, resistor 143 and resistor 144, output terminal 142, and including current-voltage conversion circuit 120, ramp voltage generation circuit 121 , PWM comparison circuit 122, control circuit 123 and PWM conversion circuit 150 of reverse current detection circuit 124, constant voltage source or offset voltage source 161, a terminal 162o, a first terminal 162 ₁ , a second terminal 162 ₂ and a control terminal 162c switch 162.

One end of the reference voltage source 110 is connected to the non-inverting input terminal of the error amplifier circuit 111 , and the other end is connected to the ground terminal 102 . The inverting input terminal of the error amplifier circuit 111 is connected to the connection point of the resistors 143 and 144 , and the output is connected to the inverting input terminal of the PWM comparator circuit 122 , one end of the offset voltage source 161 , and the second terminal 162 ₂ of the switch 162 . . The first terminal 162 ₁ of the switch 162 is connected to the other end of the offset voltage source 161 , the terminal 162 o is connected to the inverting input terminal of the PFM comparison circuit 113 , and the control terminal 162 c is connected to the output of the control circuit 123 . One end of the reference voltage source 112 is connected to the non-inverting input terminal of the PFM comparison circuit 113 , and the other end is connected to the ground terminal 102 . The output of the PFM comparison circuit 113 is connected to the input of the oscillation circuit 114 and the input of the control circuit 123 . The output of the oscillation circuit 114 is connected to the input of the control circuit 123 .

The input of the ramp voltage generation circuit 121 is connected to the output of the current-voltage conversion circuit 120 , and the output is connected to the non-inverting input terminal of the PWM comparison circuit 122 . The output of the PWM comparison circuit 122 is connected to the input of the control circuit 123 . The source of the PMOS transistor 130 is connected to the power supply terminal 101 and the input of the current-voltage conversion circuit 120 , the gate is connected to the output of the control circuit 123 , the drain is connected to one end of the inductor 140 , and the non-inverting phase of the reverse current detection circuit 124 The input terminal and the drain of the NMOS transistor 131 . The gate of the NMOS transistor 131 is connected to the output of the control circuit 123 , and the source is connected to the ground terminal 102 . The inverting input terminal of the reverse current detection circuit 124 is connected to the ground terminal 102 , and the output is connected to the input of the control circuit 123 .

The other end of the inductor 140 is connected to one end of the capacitor 141 , one end of the resistor 143 and the output terminal 142 . The other end of the capacitor 141 is connected to the ground terminal 102 . The other end of the resistor 144 is connected to the ground terminal 102 .

Hereinafter, the operation of the switching regulator 100 configured as described above will be described.

The error amplifier circuit 111 compares the voltage VFB obtained by dividing the output voltage VOUT of the output terminal 142 by the resistor 143 and the resistor 144 with the reference voltage VREF1 of the reference voltage source 110, and outputs the error voltage VERR1.

The current-voltage converting circuit 120 converts the source current of the PMOS transistor 130 into a voltage, and outputs the voltage to the ramp voltage generating circuit 121 . The ramp voltage generating circuit 121 applies a sawtooth wave to the output of the current-voltage converting circuit 120, and outputs the voltage VCS. The PWM comparison circuit 122 compares the error voltage VERR1 with the voltage VCS, and outputs the comparison result signal CMPW to the control circuit 123 .

The switch 162 connects the terminal _162o to any _one of the first terminal 1621 and the second terminal 1622 in accordance with the control signal CONT from the control circuit 123 input to the control terminal 162c. When the terminal 162o of the switch 162 is connected to the _first terminal 1621, the voltage VERR2 input to the inverting input terminal of the PFM comparison circuit 113 becomes the offset voltage VOS (negative voltage) obtained by adding the error voltage VERR1 to the offset voltage source 161 When the obtained voltage is connected to the _second terminal 1622, the voltage VERR2 input to the inverting input terminal of the PFM comparison circuit 113 becomes the error voltage VERR1. The terminal 162o of the switch 162 is normally connected to the second terminal 162 ₂ , so that the error voltage VERR1 and the voltage VERR2 become the same voltage.

The PFM comparison circuit 113 compares the reference voltage VREF2 of the reference voltage source 112 with the voltage VERR2 , and outputs the comparison result signal CMPF to the oscillation circuit 114 . The oscillation circuit 114 oscillates (is enabled) at a predetermined frequency when the comparison result signal CMPF is at a low level, and outputs a clock signal as the output signal CLK. Moreover, when the comparison result signal CMPF is at a high level, the oscillation circuit 114 stops oscillation (is disabled), and fixes the output signal CLK at a low level.

The reverse current detection circuit 124 compares the drain voltage and the source voltage of the NMOS transistor 131 , and if the drain voltage is higher than the source voltage, outputs a reverse current detection signal to the control circuit 123 .

The control circuit 123 controls the on/off of the PMOS transistor 130 and the NMOS transistor 131 according to each input signal.

The inductor 140 and the capacitor 141 smooth the voltage VSW output from the drain of the PMOS transistor 130 .

With such a circuit configuration, the negative feedback loop functions, and the switching regulator 100 operates so that the voltage VFB becomes equal to the reference voltage VREF1 to generate the output voltage VOUT to the output terminal 142 .

In the switching regulator 100 , the PWM (Pulse Width Modulation) operation and the PFM (Pulse Frequency Modulation) operation are switched as follows according to the magnitude of the current (load current) flowing in the load (not shown) connected to the output terminal 142 .

When the load current is large, the error voltage VERR1 (ie, the voltage VERR2 ) rises to compensate for the drop of the output voltage VOUT. Therefore, the error voltage VERR1 is stably larger than the reference voltage VREF2, and the oscillation circuit 114 continues to output a clock signal of a predetermined frequency as the output signal CLK. In synchronization with the rise of the clock signal, the PWM conversion circuit 150 turns on the PMOS transistor 130 and turns off the NMOS transistor 131 . At this time, the pulse width of the signal for controlling the on-time of the PMOS transistor 130 is determined by the PWM conversion circuit 150 . In this way, when the load current is large, the switching regulator 100 becomes the PWM operation.

After that, when the load current becomes smaller from the above state, the state in which the error voltage VERR1 is stably larger than the reference voltage VREF2 continues at the time point just after the load current becomes smaller. However, since the load current has become smaller, the drop of the output voltage VOUT due to the load current is small, and the increase of the output voltage VOUT due to turning on the PMOS transistor 130 becomes larger. Therefore, the error voltage VERR1 decreases so as to compensate for the increase in the output voltage VOUT, and becomes a voltage value lower than the reference voltage VREF2. As a result, the PMOS transistor 130 is turned off, and the output voltage VOUT gradually decreases.

And, when the error voltage VERR1 gradually rises and becomes larger than the reference voltage VREF2, the oscillation circuit 114 outputs the clock signal as the output signal CLK. In synchronization with the rise of the clock signal, the PWM conversion circuit 150 turns on the PMOS transistor 130 and turns off the NMOS transistor 131 . At this time, since the load current is small, the PMOS transistor 130 is turned on, and the output voltage VOUT immediately exceeds the desired voltage value, so the error voltage VERR1 decreases. Then, the PWM conversion circuit 150 turns off the PMOS transistor 130 and turns on the NMOS transistor 131 . Furthermore, the oscillation circuit 114 fixes the output signal CLK to a low level. In this way, when the load current is small, the oscillation circuit 114 repeatedly oscillates and stops. That is, the switching regulator 100 becomes the PFM operation.

In this way, the switching regulator 100 of the present embodiment switches to the PFM operation when the load current is small, so that the power conversion efficiency can be improved.

Hereinafter, in order to explain the characteristic configuration of the switching regulator 100 of the present embodiment, the circuit operation during the PFM operation of the switching regulator 100 will be described in detail.

2 shows waveforms of inductor current IL, output voltage VOUT, voltage VFB, error voltage VERR1, voltage VERR2, comparison result signal CMPF, and output signal CLK of oscillation circuit 114 of the switching regulator 100 of the present embodiment.

At time t0, the comparison result signal CMPF is at a high level, and the PMOS transistor 130 stops switching and is turned off. Furthermore, since the comparison result signal CMPF is at a high level, the switch 162 connects the terminal 162o to the second terminal 162 ₂ in accordance with the control signal CONT from the control circuit 123 input to the control terminal 162c. Since the PMOS transistor 130 has been turned off, the output voltage VOUT drops, and the voltage VFB gradually drops along with this. And, when the voltage VFB is lower than the reference voltage VREF1, the error voltage VERR1 gradually increases.

When the error voltage VERR1 exceeds the reference voltage VREF2 at time t1, the comparison result signal CMPF is inverted to a low level, and the oscillator circuit 114 outputs a clock signal as the output signal CLK along with this. The control circuit 123 receives the clock signal to turn on the PMOS transistor 130, whereby the inductance circuit IL flows. Meanwhile, in response to the comparison result signal CMPF becoming the low level, the control circuit 123 inverts the control signal CONT. Accordingly, the switch 162 switches the terminal 162o from being connected to the second terminal 162 ₂ to being connected to the first terminal 162 ₁ . Therefore, the voltage VERR2 is lower than the error voltage VERR1 by the voltage VOS.

Then, at time t2, the PFM comparison circuit 113 detects a drop in the voltage VERR2 and inverts the comparison result signal CMPF to a high level.

After that, at time t3 when a predetermined period has elapsed since time t1 when the comparison result signal CMPF was inverted to the low level, the control circuit 123 inverts the control signal CONT again. Upon receipt of this signal, the switch 162 switches the terminal 162o from being connected to the first terminal 162 ₁ to being connected to the second terminal 162 ₂ . Thereby, the voltage VERR2 becomes equal to the error voltage VERR1 again.

In this way, by reducing the voltage VERR2 by the voltage VOS at the time t1, that is, setting an offset to the inverting input terminal of the PFM comparison circuit 113, the PFM comparison circuit 113 can reduce the error voltage VERR1 to the reference voltage VREF2 earlier than the time when the error voltage VERR1 is lower than the reference voltage VREF2. The dot makes the comparison result signal CMPF high. This is equivalent to compensating for the response delay of the PFM comparison circuit 113 . As a result, after the clock signal is output from the oscillation circuit 114 at the time t1, it is possible to prevent an unnecessary clock signal from being output in the signal CLK. Therefore, since the PMOS transistor 130 does not perform the switching operation unnecessarily, it is possible to suppress the increase in the ripple voltage of the output voltage VOUT.

In this embodiment, a constant voltage source is used as the offset voltage source 161, but a resistor and a current source may be used instead of the constant voltage source. The configuration of the offset voltage source 161 is not particularly limited as long as a constant voltage can be generated.

Next, a switching regulator 200 according to a second embodiment of the present invention will be described with reference to FIG. 3 .

The switching regulator 200 of the present embodiment is configured such that the offset voltage source 161 and the switch 162 are removed from the switching regulator 100 of the first embodiment, and the PFM comparator circuit 113 is replaced with a PFM comparator circuit 170 with hysteresis.

Since other configurations are the same as those of the switching regulator 100 in FIG. 1 , the same components are denoted by the same reference numerals, and overlapping descriptions are appropriately omitted.

The inverting input terminal of the PFM comparator circuit 170 is connected to the output of the error amplifying circuit 111 and the inverting input terminal of the PWM comparator circuit 122 , the non-inverting input terminal is connected to one end of the reference voltage source 112 , and the output is connected to the oscillating circuit 114 . The input, the hysteresis enable terminal 170e is connected to the output of the control circuit 123 .

Hereinafter, the operation of the switching regulator 200 of the present embodiment will be described focusing on differences from the switching regulator 100 of the first embodiment.

The difference in operation is that the operation implemented by the offset voltage source 161 and the switch 162 in the switching regulator 100 of the first embodiment is implemented by the hysteresis inside the PFM comparison circuit 170 .

That is, the PFM comparison circuit 170 includes a hysteresis enable terminal 170e, and the presence or absence of hysteresis can be controlled based on the control signal CONT from the control circuit 123 input to the terminal. The hysteresis is equivalent to adding an external offset to the input of the PFM comparison circuit 170, and the operation is performed to compensate for the response delay of the PFM comparison circuit 170 as in the first embodiment.

Therefore, the ripple voltage of the output voltage VOUT can be suppressed in the switching regulator 200 of the present embodiment as in the first embodiment.

Furthermore, in the switching regulator 200 of the present embodiment, the PFM comparison circuit 170 is configured to be able to control the presence or absence of hysteresis, thereby realizing the addition of an external offset to the input of the PFM comparison circuit 170 . The hysteresis of the PFM comparison circuit 170 can be relatively easily generated by adjusting the size of the differential elements constituting the PFM comparison circuit 170 , or the like. Therefore, as compared with the case where a constant voltage source, a resistor, a current source, etc. are added as the offset voltage source 161 as in the switching regulator 100 of the first embodiment, there is an advantage that an additional element or the like is hardly required, and the circuit scale is not increased. .

However, since the switching regulator 100 of the first embodiment using the offset voltage source has higher precision than the switching regulator 200 of the second embodiment, it is preferable to use it according to the allowable precision.

Next, a switching regulator 300 according to a third embodiment of the present invention will be described with reference to FIG. 4 . The switching regulator 300 of the present embodiment is configured by removing the offset voltage source 161 and the switch 162 from the switching regulator 100 of the first embodiment, and replacing the reference voltage source 112 with the variable reference voltage source 180 .

Since other configurations are the same as those of the switching regulator 100 in FIG. 1 , the same components are denoted by the same reference numerals, and overlapping descriptions are appropriately omitted.

The inverting input terminal of the PFM comparator circuit 113 is connected to the output of the error amplifier circuit 111 and the inverting input terminal of the PWM comparator circuit 122 , and the non-inverting input terminal is connected to one end of the variable reference voltage source 180 . The other end of the variable reference voltage source 180 is connected to the ground terminal 102 , and the control input terminal 180 c is connected to the output of the control circuit 123 .

Hereinafter, the operation of the switching regulator 300 of the present embodiment will be described focusing on differences from the switching regulator 100 of the first embodiment.

The difference in operation is that it is realized by switching the reference voltage generated by the variable reference voltage source 180 into two voltage values, which is realized by the offset voltage source 161 and the switch 162 in the switching regulator 100 of the first embodiment. Actions.

Specifically, the variable reference voltage source 180 includes a control input terminal 180c, and the reference voltage VREF2' can be changed to any two based on the control signal CONT from the control circuit 123 input to the terminal. The voltage value, that is, the reference voltage VREF2 ′ is switched from the first voltage value to the second voltage value higher than the first voltage value in response to the comparison result signal CMPF becoming the low level. Changing the reference voltage VREF2' to any two values in accordance with the output of the control circuit 123 in this way is equivalent to adding an external offset to the input of the PFM comparison circuit 113, and the PFM comparison circuit is compensated in the same way as in the first embodiment. 113 to operate in a delayed manner.

Therefore, the ripple voltage of the output voltage VOUT can be suppressed in the switching regulator 300 of the present embodiment as in the first embodiment.

Furthermore, in the switching regulator 300 of the present embodiment, by using the variable reference voltage source 180 , it is possible to add an external offset to the input of the PFM comparison circuit 113 . When the variable reference voltage source 180 is configured as a reference voltage source connected to the non-inverting input terminal of the PFM comparison circuit 113 by a voltage dividing resistor, the variable reference voltage source 180 can be simply configured by switching the resistance ratio with a switch. Therefore, when the reference voltage source connected to the non-inverting input terminal of the PFM comparison circuit 113 is constituted by a voltage dividing resistor, the switching regulator 300 of the present embodiment can be used, and the non-inverting input terminal connected to the PFM comparison circuit 113 can be used without When a voltage dividing resistor is used as the reference voltage source of the inverting input terminal, the switching regulator 100 of the first embodiment is used.

As mentioned above, although embodiment of this invention was described, it is needless to say that this invention is not limited to the said embodiment, Various changes are possible in the range which does not deviate from the summary of this invention.

For example, in the above-described embodiments, the switching regulator of the current mode control system has been described as an example, but the present invention can also be applied to the switching regulator of the voltage mode control system.

Furthermore, in the above-described embodiment, the example in which a MOS transistor is used as the switching element and the synchronous rectifier element has been described, but a bipolar transistor or the like may also be used.

In addition, in the above-mentioned embodiment, the switching regulator of the synchronous rectification system has been described as an example, but the present invention can also be applied to a switching regulator of the diode rectification system. In addition, in the case of the diode rectification method, a reverse current detection circuit is not required.

100, 200, 300, 500‧‧‧Switching regulator 101, 501‧‧‧Power supply terminal 102, 502‧‧‧Grounding terminal 110, 112, 510, 512‧‧‧Reference voltage source 111, 511‧‧‧Error amplification Circuits 113, 513‧‧‧PFM comparison circuit 114, 514‧‧‧oscillation circuit 120, 520‧‧‧Current voltage conversion circuit 121, 521‧‧‧Slope voltage generating circuit 122, 522‧‧‧PWM comparison circuit 123, 523 ‧‧‧Control circuit 124, 524‧‧‧Reverse current detection circuit 130, 530‧‧‧PMOS transistor 131, 531‧‧‧NMOS transistor 140, 540‧‧‧Inductor 141, 541‧‧‧Capacitor 142, 542 ‧‧‧Output terminals 143, 144, 543, 544‧‧‧Resistor 150, 550‧‧‧PWM conversion circuit 161‧‧‧Offset voltage source 162‧‧‧Switch 162o‧‧‧Terminal 162 ₁ ‧‧‧First Terminal 162 ₂ ‧‧‧Second terminal 162c‧‧‧Control terminal 170‧‧‧PFM comparator circuit with hysteresis (PFM comparator circuit) 170e‧‧‧Hysteresis enable terminal 180‧‧‧Variable reference voltage source 180c‧‧ ‧Control input terminal CLK‧‧‧Output signal (signal) CMPF, CMPW‧‧‧Comparison result signal CONT‧‧‧Control signal IL‧‧‧Inductor current Td‧‧‧Delay time VCS, VERR2, VFB, VSW‧‧‧ Voltage VERR, VERR1‧‧‧Error voltage VOS‧‧‧Offset voltage (voltage) VOUT‧‧‧Output voltage VREF1, VREF2, VREF2'‧‧‧Reference voltage VTG‧‧‧desired voltage value

FIG. 1 is a circuit diagram showing a switching regulator according to a first embodiment of the present invention. FIG. 2 is a diagram showing signal waveforms of each node of the switching regulator of FIG. 1 . 3 is a circuit diagram showing a switching regulator according to a second embodiment of the present invention. 4 is a circuit diagram showing a switching regulator according to a third embodiment of the present invention. FIG. 5 is a circuit diagram of a conventional switching regulator. FIG. 6 is a diagram showing signal waveforms of each node of the switching regulator of FIG. 5 .

100‧‧‧Switching regulator

101‧‧‧Power terminal

102‧‧‧Ground Terminal

110, 112‧‧‧reference voltage source

111‧‧‧Error amplifier circuit

113‧‧‧PFM comparator circuit

114‧‧‧Oscillation circuit

120‧‧‧Current-Voltage Conversion Circuit

121‧‧‧Ramp Voltage Generation Circuit

122‧‧‧PWM comparator circuit

123‧‧‧Control circuit

124‧‧‧Reverse current detection circuit

130‧‧‧PMOS transistor

131‧‧‧NMOS transistor

140‧‧‧Inductors

141‧‧‧Capacitors

142‧‧‧Output terminal

143, 144‧‧‧Resistor

150‧‧‧PWM conversion circuit

161‧‧‧Offset Voltage Source

162‧‧‧Switch

162o‧‧‧Terminal

162 ₁ ‧‧‧Terminal 1

162 ₂ ‧‧‧Terminal 2

162c‧‧‧Control terminal

CLK‧‧‧output signal (signal)

CMPF, CMPW‧‧‧Comparison result signal

CONT‧‧‧Control Signal

IL‧‧‧Inductor current

VCS, VERR2, VFB, VSW‧‧‧Voltage

VERR1‧‧‧Error Voltage

VOS‧‧‧Offset Voltage (Voltage)

VOUT‧‧‧output voltage

VREF1, VREF2‧‧‧reference voltage

Claims (5)

A switching regulator that generates a predetermined output from a power supply voltage supplied to the power supply terminal to an output terminal connected to the other end of the inductor by a switching element connected between a power supply terminal and one end of an inductor voltage, the switching regulator includes: an error amplifying circuit that amplifies the difference between the voltage based on the output voltage and the first reference voltage, and outputs an error voltage; a pulse frequency modulation comparison circuit that compares the inputted error The voltage is compared with the second reference voltage, and a comparison result signal of the first level or the second level is output; the oscillator circuit outputs a clock signal of a predetermined frequency when the comparison result signal is the first level, and the clock signal is When the comparison result signal is the second level, the output of the clock signal is stopped; and the pulse width modulation conversion circuit, based on the error voltage and the output of the oscillation circuit, that is, the clock signal, through The evolution of the clock signal turns on the switching element, and on the other hand turns off the switching element corresponding to the error voltage, and controls the switching element to turn on or off with a desired pulse width, and the switch adjusts A controller sets an offset in response to the comparison result signal switching from the second level to the first level, and the offset makes the error voltage input to the PWM comparator circuit to be Within a predetermined period, the voltage is lower than the error voltage output from the error amplifier circuit by a predetermined value. The switching regulator according to claim 1, wherein the offset is set so that the comparison result signal is switched to the second level. The switching regulator according to claim 1 or claim 2, wherein the PWM comparison circuit switches from the second level to the first level in response to the comparison result signal It switches from the state of comparing the error voltage with the second reference voltage to the state of comparing the voltage obtained by adding the offset voltage to the error voltage and the second reference voltage. A switching regulator that generates a predetermined output from a power supply voltage supplied to the power supply terminal to an output terminal connected to the other end of the inductor by a switching element connected between a power supply terminal and one end of an inductor voltage, the switching regulator includes: an error amplifying circuit that amplifies the difference between the voltage based on the output voltage and the first reference voltage, and outputs an error voltage; a pulse frequency modulation comparison circuit that compares the inputted error The voltage is compared with the second reference voltage, and a comparison result signal of the first level or the second level is output; the oscillation circuit outputs a clock signal of a predetermined frequency when the comparison result signal is the first level, and the clock signal is When the comparison result signal is the second level, the output of the clock signal is stopped; and the pulse width modulation conversion circuit, based on the error voltage and the output of the oscillation circuit, that is, the clock signal, by The evolution of the clock signal turns on the switching element, and on the other hand turns off the switching element corresponding to the error voltage, and controls the switching element to turn on or off with a desired pulse width, and the pulse frequency The modulation comparison circuit is capable of switching the presence or absence of hysteresis, and in response to the comparison result signal switching from the second level to the first level, and in a specified During the period, it becomes a state with hysteresis. A switching regulator that generates a predetermined output from a power supply voltage supplied to the power supply terminal to an output terminal connected to the other end of the inductor by a switching element connected between a power supply terminal and one end of an inductor voltage, the switching regulator includes: an error amplifying circuit that amplifies the difference between the voltage based on the output voltage and the first reference voltage, and outputs an error voltage; a pulse frequency modulation comparison circuit that compares the inputted error The voltage is compared with the second reference voltage, and a comparison result signal of the first level or the second level is output; the oscillator circuit outputs a clock signal of a predetermined frequency when the comparison result signal is the first level, and the clock signal is When the comparison result signal is the second level, the output of the clock signal is stopped; and the pulse width modulation conversion circuit, based on the error voltage and the output of the oscillation circuit, that is, the clock signal, through The evolution of the clock signal turns the switching element on, and on the other hand, the switching element is turned off corresponding to the error voltage, and the switching element is controlled to be turned on or off with a desired pulse width, and the pulse frequency The modulation comparison circuit switches from the second level to the first level in response to the comparison result signal, and switches to a predetermined state in which the error voltage is compared with the second reference voltage freely. A state in which the error voltage is compared with a third reference voltage higher than the second reference voltage by a predetermined value during the period.

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