TWI450365B - Method for manufacturing a cmos device having dual metal gate - Google Patents

Description

Complementary MOS device with bimetal gate manufacturing method

The present invention relates to a method for fabricating a complementary metal-oxide semiconductor (hereinafter referred to as CMOS) device having a dual metal gate, and more particularly to a gate last. A manufacturing method for a bimetal gate CMOS device.

As CMOS components continue to shrink in size, conventional methods have used a method of reducing the thickness of the gate dielectric layer, such as reducing the thickness of the yttria layer, for optimization purposes, due to the tunneling effect of electrons. A physical limitation that causes excessive leakage current. In order to effectively extend the evolution of logic components, high dielectric constant (hereinafter referred to as High-K) materials have an effective reduction in physical limit thickness and are under the same equivalent oxide thickness (EOT). It effectively reduces the leakage current and achieves the equivalent capacitance to control the channel switch. It is used to replace the traditional germanium dioxide layer or the yttria layer as the gate dielectric layer.

However, the conventional polysilicon gate has problems due to boron penetration, which leads to a decrease in device performance. Moreover, the polysilicon gate encounters an inevitable depletion effect, resulting in an equivalent gate dielectric thickness. Increased, the gate capacitance value decreased, which led to the decline of component drive capability. Therefore, new gate materials have been developed and produced, which use a double work function metal to replace the conventional polysilicon gate as a control electrode for matching the High-K gate dielectric layer.

The dual function metal gate is matched with the NMOS component and the PMOS component is matched with the PMOS component, which makes the integration technology and process control of the related component more complicated, and the thickness and composition control requirements of each material are more stringent. For example, in the gate first process of a conventional bi-function metal gate, a process of forming a metal gate and a source/drain ultra-shallow junction activation tempering and forming a metal telluride are performed. Under such a severe thermal budget environment, it is often found that the flat voltage of the component (hereinafter referred to as V _fb ) does not rise or fall linearly as the EOT of the high-k dielectric layer decreases. Please refer to FIG. 1. FIG. 1 is a diagram showing the relationship between the High-K gate dielectric layers EOT and _Vfb of a PMOS device. As shown in Figure 1, the V _fb and EOT of the component do not exhibit the expected linear relationship, but instead a sudden decrease occurs when the EOT decreases, and this V _fb roll-off situation is particularly noticeable on the PMOS device.

Therefore, how to effectively solve the problem of the drop of the above-mentioned components V _fb without increasing the complexity of the process is a problem worthy of discussion.

SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a complementary _MOS device having a bimetal gate which can effectively solve the problem of a drop in the component _Vfb .

According to the scope of the invention provided by the present invention, a method of fabricating a complementary metal oxide semiconductor (CMOS) device having a bimetal gate is provided. The method includes providing a substrate, the surface of the substrate defining a first active region, a second active region, and a shallow trench isolation for electrically isolating the first active region from the second active region , STI). Then, a first conductive type transistor and a second conductive type transistor are respectively formed in the first active region and the second active region, and a self-aligned metal salicide process is performed. An inter-level dielectric layer (ILD) is then formed on the substrate, and the inner dielectric layer exposes the top of the first conductive type transistor and the second conductive type of transistor. Thereafter, a first etching process is performed to remove a first gate of the first conductive type transistor portion, and an opening is formed in the first active region, and the first conductive type is electrically A high dielectric constant gate dielectric layer of the crystal is exposed to the bottom of the opening. Finally, at least a first metal layer is formed in the opening.

According to the scope of the invention, there is further provided a method of fabricating a complementary MOS device having a bimetal gate. The method includes providing a substrate defining a first active region, a second active region, and a shallow trench isolation (STI) for electrically isolating the first active region from the second active region . Then, a first conductive type transistor and a second conductive type transistor are respectively formed in the first active region and the second active region, and a self-aligned metal telluride process is performed. An inner dielectric layer (ILD) is then formed on the substrate, and the inner dielectric layer exposes the top of the first conductive type transistor and the second conductive type of transistor. Thereafter, a first etching process is performed to remove a first gate of the first conductive type transistor portion, and a first opening is formed in the first active region, and the first conductive type transistor A high dielectric constant gate dielectric layer is exposed to the bottom of the opening. After the first opening is formed, at least a first metal layer is formed in the first opening. Next, a second etching process is performed to remove a second gate of the second conductive type transistor portion, and a second opening is formed in the second active region, and the second conductive type transistor A high dielectric constant gate dielectric layer is exposed to the bottom of the second opening. After the second opening is formed, at least a second metal layer is formed in the second opening.

According to the method for fabricating a complementary metal oxide semiconductor device having a bimetal gate provided by the present invention, at least one conductivity type electro-optic system is obtained by a post gate process, and thus can be used to fabricate a conductive transistor that avoids a high thermal budget. To improve the V _fb drop problem and increase the selectivity of the gate metal material. In addition, in the method provided by the present invention, since the high dielectric constant gate dielectric layer is not removed along with the gate, but remains in the opening, the gate layer is subsequently filled in the metal layer. During fabrication, it is no longer necessary to monitor the thickness control and uniformity control of the high dielectric constant gate dielectric layer for this very thin film, and because the high dielectric constant gate dielectric layer does not follow the gate one. And removed, so that a good interface between the high dielectric constant gate dielectric layer and the germanium substrate is also affected, thereby affecting the carrier mobility of the channel region.

Please refer to FIG. 2 to FIG. 8 . FIG. 2 to FIG. 8 are schematic diagrams showing a first preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. As shown in FIG. 2, a substrate 100, such as a germanium substrate, a germanium-containing substrate, or a silicon-on-insulator (SOI) substrate, is defined. A first active region 110 is defined on the surface of the substrate 100. And a second active region 112, and a shallow trench isolation (hereinafter referred to as STI) 102 for electrically isolating the first active region 110 from the second active region 112 is formed in the substrate 100. Next, a high dielectric constant (hereinafter abbreviated as High-K) gate dielectric layer 104, a tantalum carbide (TaC) layer 106, and a polysilicon layer 108 are sequentially formed on the substrate 100. In addition, in the first embodiment, a protective layer (not shown) may be formed between the High-K gate dielectric layer 104 and the tantalum carbide (TaC) layer 106 to protect the gate dielectric layer 104. Damaged in subsequent processes.

Please refer to Figure 3. A lithography and etching process is performed to etch the polysilicon layer 108, the tantalum carbide layer 106, and the High-K gate dielectric layer 104, and form a first gate in the first active region 110 and the second active region 112, respectively. 120 and a second gate 122. Please continue to refer to FIG. 3 , and then a first lightly doped buck (light doped) is formed in the substrate 100 on both sides of the first gate 120 and the second gate 122 by using different conductivity type ion implantation processes. Drain, hereinafter referred to as LDD) 130 and a second LDD 132. In addition, before the first LDD 130 and the second LDD 132 are formed, an offset spacer (not shown) may be formed on the sidewalls of the first gate 120 and the second gate 122, respectively. Then, a sidewall 134 is formed on the sidewalls of the first gate 120 and the second gate 122, respectively. Finally, a first source/drain 140 and a second source/drain 142 are respectively formed in the substrate 100 on both sides of the first gate 120 and the second gate 122 by using different conductivity type ion implantation processes. . A first conductive type transistor 150 and a second conductive type transistor 152 are formed in the first active region 110 and the second active region 120, respectively.

Please refer to Figure 4. Next, a self-aligned metal salicide process is performed on the surfaces of the first gate 120, the second gate 122, the first source/drain 140, and the second source/drain 142, respectively. A metal telluride layer 154 is formed. Then, as shown in FIG. 5, an inter-level dielectric layer (hereinafter referred to as ILD layer) 160 is formed on the substrate 100, and is subjected to chemical mechanical polishing (hereinafter referred to as CMP). The planarization process grinds the ILD layer 160 such that the ILD layer 160 exposes the metal oxide layer 154 on top of the first conductivity type transistor 150 and the second conductivity type transistor 152. Or after the CMP is planarized by the ILD layer 160, the ILD layer 160 above the first conductive type transistor 150 is etched back by an etch back process until the metal telluride layer on the top of the first conductive type transistor 150 is exposed. 154. Regardless of which method is implemented, the metal telluride layer 154 on top of the first conductivity type transistor 150 may be partially removed or completely retained.

Please refer to Figure 6. Next, the metal germanide layer 154 on the top of the first gate 120 is removed, and after the metal germanide layer 154 is removed, a first etching process and a second etching process are sequentially performed to respectively remove the first The first gate 120 of the portion of the conductive transistor 150. For example, the first etch process removes the polysilicon layer 108 of the first gate 120; and the second etch process removes the ruthenium carbide layer 106 of the first gate 120. An opening 162 as shown in FIG. 6 is formed in the first active region 150. It should be noted that in the present embodiment, the High-K gate dielectric layer 104 of the first conductivity type transistor 150 is exposed to the bottom of the opening 162. As described above, the gate dielectric layer 104 further includes a protective layer for protecting the gate dielectric layer 104. Therefore, after the second etching process, a third etching step may be performed to remove the protective layer. However, the protective layer can also be retained without removal. In addition, the arrangement of the protective layer is not limited to the first preferred embodiment, but may be a variation of each of the preferred embodiments disclosed herein.

Please refer to Figure 7. Next, a metal layer 170 is formed in the opening 162. The metal layer 170 includes a metal material such as molybdenum nitride (MoAlN), tungsten (W), molybdenum nitride (MoN), tantalum oxynitride (TaCNO), titanium nitride (TiN), or tungsten nitride (WN). . Since the above metal filling ability is poor, in order to avoid gaps in the filling, the first preferred embodiment uses a metal layer 172 as the main material for filling the opening 162 after forming the metal layer 170; and the metal layer 170 Can be used to adjust the work function. The metal layer 172 includes aluminum (Al), titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), titanium nitride (TiN), titanium carbide (TiC), and nitriding. Tantalum (TaN), titanium tungsten (Ti/W), or a composite metal such as titanium and titanium nitride (Ti/TiN). In addition, in order to avoid the reaction or diffusion effect of the high-K gate dielectric layer 104 and the metal layer 170, a barrier layer may be formed in the opening 162 before the metal layer 170 is formed (not shown). The barrier layer may include an element such as a high temperature transition metal, a precious metal, a rare earth metal, and a carbide, a nitride, a telluride, an aluminum nitride or a nitrogen halide.

Please refer to Figure 8. Finally, the unnecessary conductive metal layers 170, 172 are removed by a CMP process to complete the fabrication of the first conductive type transistor 150.

According to the first preferred embodiment of the present invention, the PMOS device can be used to fabricate a PMOS device which is susceptible to V _fb degradation caused by high temperature process, thereby providing a wider selection of materials. In addition, an interface layer (not shown) is formed between the High-K gate dielectric layer 104 and the substrate 100 to enhance the channel region before the formation of the High-K gate dielectric layer 104. Electron mobility, this interface layer is a ruthenium oxide layer, a ruthenium oxynitride layer, or a tantalum nitride layer formed by chemical bonding or heating to 850 ° C. The high-temperature process is also completed in the metal gate of the PMOS device, so it does not affect the PMOS device. In addition, since the High-K gate dielectric layer 104 is not removed in the first preferred embodiment, when the semiconductor process of 45 nm (line) line width is stepped, the removal from the High is eliminated. -K gate dielectric layer 104, which must be faced with film thickness control and uniformity control when re-reforming in such a tiny opening 162.

Please refer to FIG. 9 to FIG. 15. FIG. 9 to FIG. 15 are schematic diagrams showing a second preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. As shown in FIG. 9, a substrate 200, such as a germanium substrate, a germanium-containing substrate, or an SOI substrate, is provided. The surface of the substrate 200 defines a first active region 210 and a second active region 212. A shallow trench isolation (STI) 202 for electrically isolating the first active region 210 from the second active region 212. Next, a first conductive type transistor 250 and a second conductive type transistor 252 are formed in the first active region 210 and the second active region 212, respectively. Since the steps of forming the first conductive type transistor 250 and the second conductive type transistor 252 are the same as those of the first preferred embodiment, they are not described herein again. Next, a capping layer (not shown) is formed on the substrate 200. The capping layer may be a hafnium oxide layer, a tantalum nitride layer, or a hafnium oxynitride layer. Then, a portion of the cap layer is removed by a lithography and etching process, and a cap layer 280 as shown in FIG. 10 is formed on one of the first gates 220 of the first conductivity type transistor 250. In addition, the cap layer 280 may also be oxidized or formed simultaneously with a hard mask layer (not shown) for defining a gate, and simultaneously etched with the first gate 220 to remove the hard mask layer. .

Please refer to Figure 10 and Figure 11. Next, a self-aligned metal salicide process is performed. Since the first gate 220 is covered by the cap layer 280, only the polysilicon layer 208 of the second gate 222 is formed during the metal telluride process. A metal telluride layer 254 may be formed on the surfaces of the first source/drain 240 and the second source/drain 242, respectively. In addition, in the second preferred embodiment, as shown in FIG. 11, a contact etch stop layer 282 can be selectively formed on the substrate 200 after the metal germanide layer 254 is formed. Referred to as CESL), a step of applying ultraviolet light or thermal energy causes CESL 282 to generate a stress as a selective strain scheme (SSS). Since the selective stress system does not actually affect the CMOS device process, it is not limited to the second preferred embodiment and can be a variation of the preferred embodiments of the present invention.

Then, as shown in FIG. 12, an ILD layer 260 is formed on the substrate 200, and the ILD layer 260 is polished by a planarization process such as CMP, and the CMP planarization process is stopped at the first conductive type transistor 250 and The CESL 282 on top of the second conductivity type transistor 252. Or after the CMP planarizes the ILD layer 260, the ILD layer 260 over the first conductive type transistor 250 is etched back by an etch back process until the CESL 282 at the top of the first conductive type transistor 250 is exposed. In addition, the planarization process or the etch back process may continue until the cover layer 280 is exposed.

Please refer to Figure 13. Next, the CESL 282 on the first gate 220 and the cap layer 280 on the first gate 220 are sequentially removed by using different etching processes. After the film layers are removed, a first etching process and a second etching process are sequentially performed to respectively remove the first gate 220 of the first conductive type transistor 250 portion. For example, the first etch process removes the polysilicon layer 208 of the first gate 220; and the second etch process removes the ruthenium carbide layer 206. An opening 262 as shown in FIG. 13 is formed in the first active region 210. It is noted that the High-K gate dielectric layer 204 of the first conductivity type transistor 250 is exposed to the bottom of the opening 262. As described above, in the second preferred embodiment, the High-K gate dielectric layer 204 may also include a protective layer. Therefore, after the second etching process, a third etching step may be performed to remove the protective layer. However, the protective layer can also be retained without removal.

Please refer to Figure 14. Next, a metal layer 270 is formed in the opening 262. The metal material used for the metal layer 270 can be the same as the first preferred embodiment. As described above, since the metal layer 270 has a poor metal hole filling ability, in order to avoid gaps in the filling, in the second preferred embodiment, a metal layer 272 is also used as the main material for filling the opening 262; and the metal layer 270 is used. Can be used to adjust the work function. Similarly, the metal material used for the metal layer 272 can be the same as the first preferred embodiment. Please refer to Figure 15. Finally, the unnecessary first metal layer 270 and the second metal layer 272 are removed by a CMP process to complete the fabrication of the gate of the first conductivity type transistor 250.

Since the metal telluride is not easily removed, it is even possible to affect the profile of the ILD layer of the lower gate structure or its periphery when the metal halide is removed. Therefore, in the second preferred embodiment, the top of the first gate 220 is covered by the cap layer 280, so that no metal germanide is formed on the top of the first gate 220 during the metal telluride process. The removal of the above metal halide layer can be avoided.

Please refer to FIG. 16 to FIG. 21 . FIG. 16 to FIG. 21 are schematic diagrams showing a third preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. As shown in FIG. 18, a substrate 300, such as a germanium substrate, a germanium-containing substrate, or an SOI substrate, is provided. A surface of the substrate 300 defines a first active region 310 and a second active region 312, and the substrate 300 is formed. There is an STI 302 for electrically isolating the first active region 310 from the second active region 312. Next, a High-K gate dielectric layer 304, a tantalum carbide layer 306, and a polysilicon layer 308 are sequentially formed on the substrate 300. As described above, in the third preferred embodiment, a protective layer (not shown) may be formed between the gate dielectric layer 304 and the tantalum carbide layer 306 to protect the gate dielectric layer 304 in a subsequent process. Damaged. Subsequently, a lithography and etching process is performed to etch the polysilicon layer 308, the tantalum carbide layer 306, and the High-K gate dielectric layer 304, and the first gate is formed in the first active region 310 and the second active region 312, respectively. The pole 320 and a second gate 322. Continuing to refer to FIG. 16, a liner layer (not shown) may be formed on the substrate 300, which may be a hafnium oxide layer. Then, a first LDD 330 and a second LDD 332 are respectively formed in the substrate 300 on both sides of the first gate 320 and the second gate 322 by ion implantation processes of different conductivity types. After the first LDD 330 and the second LDD 332 are formed, a tantalum nitride layer 380 is formed on the substrate 300.

Please refer to Figure 17. Then, the cerium nitride layer 380 and the lining layer above the first gate 320 are removed by a lithography and etching process, and a polysilicon layer exposing the first gate 320 is formed in the first active region 310. Opening 382 of 308. A polysilicon oxidation step is then performed, such as by a rapid thermal oxidation (RTO) or oxygen plasma bombardment, through which a portion or all of the polysilicon layer 308 of the first gate 320 is oxidized.

Please refer to Figure 18. Then, the tantalum nitride layer 380 is etched back by an etching process to form a sidewall 334 on the sidewalls of the first gate 320 and the second gate 322, respectively. A first source/drain 340 and a second source/drain 342 are respectively formed in the substrate 300 on both sides of the first gate 320 and the second gate 322 by using different conductivity type ion implantation processes. A first conductive type transistor 350 and a second conductive type transistor 352 are formed in the first active region 310 and the second active region 320, respectively.

Please refer to Figure 19. Next, a self-aligned metal salicide process is performed. Since the polysilicon layer 308 of the first gate 320 has been oxidized in the polysilicon oxidation step, only the second gate is used in the self-aligned metal germanide process. A metal germanide layer 354 can be formed on the surface of the polysilicon layer 308, the first source/drain 340, and the second source/drain 342 of the pole 322, respectively. In addition, as previously described, a CESL 386 can also be selectively formed on the substrate 300 and subjected to a step of applying ultraviolet light or thermal energy to cause a stress in the CESL 386 as a selective stress system. As described above, since this selective stress system does not actually affect the CMOS device process, it is not limited to the third preferred embodiment.

Continuing to refer to FIG. 19, an ILD layer 360 is formed on the substrate 300, and the ILD layer 360 is polished by a CMP planarization process, and the CMP planarization process is stopped at the CESL 386. Or after the CMP planarizes the ILD layer 360, the ILD layer 360 over the first conductive type transistor 350 is etched back by an etch back process until the CESL 386 at the top of the first conductive type transistor 350 is exposed.

Please refer to Figure 20. Next, an etch process is performed to remove the CESL 386 on the first gate 320. After the CESL 386 is removed, a first etching process and a second etching process are sequentially performed to respectively remove the first gate 320 of one of the first conductive type transistors 350. For example, the first etch process removes the oxidized polysilicon layer 308 of the first gate 320; and the second etch process removes the ruthenium carbide layer 306. An opening 362 as shown in FIG. 20 is formed in the first active region 310. It is noted that the High-K gate dielectric layer 304 of the first conductivity type transistor 350 is exposed to the bottom of the opening 362. As described above, the High-K gate dielectric layer 304 may further include a protective layer for protecting the High-K gate dielectric layer 304. Therefore, a third etching step may be performed after the second etching process. The protective layer is removed, but the protective layer can also be retained without removal.

Please refer to Figure 21. Next, a metal layer 370 for adjusting the work function and a metal layer 372 as a main material for filling the opening 362 are formed in the opening 362, and finally the unnecessary metal layers 370, 372 are removed by a CMP process. The fabrication of the gate of the first conductivity type transistor 350 is completed. Since the steps and the metal materials used for the metal layers 370, 372 are the same as the first and second preferred embodiments described above, such details are omitted in the third preferred embodiment.

As previously mentioned, since the metal telluride is not easily removed, it is even possible to affect the contour of the lower gate structure or the ILD layer 360 around it when the metal halide is removed. Therefore, in the third preferred embodiment, the polysilicon layer 308 of the first gate 320 is oxidized by the polysilicon germanium oxidation process, so that no metal germanium is formed on the top of the first gate 320 during the metal telluride process. The problem of removal of the above metal halide layer can be avoided.

Referring to FIG. 22 to FIG. 26, FIG. 22 to FIG. 26 are schematic diagrams showing a fourth preferred embodiment of a method for fabricating a CMOS device having a bimetal gate according to the present invention. As shown in FIG. 22, a substrate 400, such as a germanium substrate, a germanium-containing substrate, or an SOI substrate, is defined. A surface of the substrate 400 defines a first active region 410 and a second active region 412, and a substrate 400 is formed therein. The STI 402 is used to electrically isolate the first active region 410 from the second active region 412. Next, a High-K gate dielectric layer 404 and a polysilicon layer 408 are sequentially formed on the substrate 400. In the fourth preferred embodiment, a protective layer (not shown) may be formed between the gate dielectric layer 404 and the polysilicon layer 408 to protect the gate dielectric layer 404 from damage during subsequent processes. Then, a portion of the polysilicon layer 408 and the high-K gate dielectric layer 404 are removed by a lithography and etching process to form a first gate 420 and a first active region 410 and a second active region 412, respectively. The second gate 422. Then, a first LDD 430 and a second LDD 432 are formed in the substrate 400 on both sides of the first gate 420 and the second gate 422 respectively; then the sidewalls of the first gate 420 and the second gate 422 are respectively respectively A sidewall 434 is formed. Finally, a first source/drain 440 and a second source/drain 442 are respectively formed in the substrate 400 on both sides of the first gate 420 and the second gate 422, and are formed as shown in FIG. The first conductive type transistor 450 and the second conductive type transistor 452.

Please refer to Figure 23. Subsequently, a self-aligned metal telluride process is performed, and a hard mask layer or a cap layer (not shown) is used to cover the surface of the polysilicon layer 408 of the first gate 420 and the second gate 422, and only the first The source/drain 440 and the second source/drain 442 surface respectively form a metal telluride layer 454. Referring to FIG. 23, an ILD layer 460 is then formed on the substrate 400, and the ILD layer 460 is polished by a CMP planarization process to expose the tops of the first gate 420 and the second gate 422.

Please refer to Figure 24. Next, a first etching process is performed to remove the polysilicon layer 408 of the first gate 420, and an opening 462 is formed in the first active region 450. It is noted that the High-K gate dielectric layer 404 of the first gate 420 is exposed to the bottom of the opening 462. The gate dielectric layer 404 may further include a protective layer for protecting the gate dielectric layer 404. Therefore, after the first etching process, another etching step may be performed to remove the protective layer, but the protective layer may also be used. Reserved without removal.

Please refer to Figure 25. Then at least one metal layer 470 is formed in the opening 462; the metal layer 470 comprises a metal material such as aluminum molybdenum nitride, tungsten, molybdenum nitride, tantalum carbonitride, titanium nitride, or tungsten nitride. Since the metal filling ability is poor, in order to avoid gaps in filling, a metal layer 472 can be used as the main material for filling the opening 462; and the metal layer 470 can be used to adjust the work function. The metal layer 472 includes aluminum, titanium, tantalum, tungsten, tantalum, molybdenum, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten alloy, or titanium and titanium nitride alloy. In addition, in order to prevent the high-K gate dielectric layer 404 from reacting or diffusing with the metal layer 470, a barrier layer (not shown) may be formed in the opening 462 before forming the first metal layer 470. The barrier layer may include an element such as a high temperature transition metal, a precious metal, a rare earth metal, and a carbide, a nitride, a telluride, an aluminum nitride or a nitrogen halide.

Please continue to see Figure 25. Next, a second etching process is performed to remove the polysilicon layer 408 of the second gate 422, and an opening 464 is formed in the second active region 412. It is noted that the High-K gate dielectric layer 404 of the second gate 422 is exposed to the bottom of the opening 464. If the gate dielectric layer 404 further includes a protective layer, another etching step may be performed to remove the protective layer after the second etching process, but the protective layer may be retained without removing.

Please refer to Figure 26. A metal layer 474 is then formed in the opening 464. The metal layer 474 contains a metal material such as tantalum carbide or titanium aluminum nitride (TiAlN). As described above, since the metal filling ability is poor, in order to avoid gaps in filling, a metal layer 476 can be utilized as the main material for filling the opening 464. The metal layer 476 comprises aluminum, titanium, tantalum, tungsten, tantalum, molybdenum, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten alloy, or titanium and titanium nitride alloy. In addition, in order to prevent the high-K gate dielectric layer 404 from reacting or diffusing with the metal layer 474, a barrier layer (not shown) may be formed in the opening 464 before the first metal layer 474 is formed. Finally, the unnecessary metal layers 470, 472, 474, 476 are removed by a CMP process or other etching process to complete the fabrication of the first conductive type transistor 450 and the second conductive type transistor 452.

According to the method for fabricating a complementary metal oxide semiconductor device having a bimetal gate according to the present invention, at least one conductivity type electro-optic system is obtained by a post gate process, so that it can be used to fabricate a conductive transistor that avoids a high thermal budget. Improves the problem of component V _fb drop while increasing the selectivity of the gate metal material. In addition, in the method provided by the present invention, the High-K gate dielectric layer is not removed along with the gate, but remains in the opening, so when the metal layer is subsequently filled to complete the gate fabrication For this extremely thin film, it is no longer necessary to monitor the thickness control and uniformity control of the high dielectric constant gate dielectric layer. At the same time, since the high dielectric constant gate dielectric layer is not removed along with the gate, it is also possible to prevent the good interface between the high dielectric constant gate dielectric layer and the germanium substrate from being affected and affecting the electrons in the channel region. Migration law. In addition, the present invention can integrate a selective strain scheme (SSS) such as CESL to improve the performance of the MOS device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100, 200, 300, 400. . . Base

102, 202, 302, 402. . . Shallow trench isolation

104, 204, 304, 404. . . High dielectric constant gate dielectric layer

105, 205, 305, 405. . . The protective layer

106, 206, 306. . . Tantalum carbide layer

108, 208, 308, 408. . . Polycrystalline layer

110, 210, 310, 410. . . First active area

112, 212, 312, 412. . . Second active area

120, 220, 320, 420. . . First gate

122, 222, 322, 422. . . Second gate

130, 330, 430. . . First lightly doped bungee

132, 332, 432. . . Second lightly doped bungee

134, 334, 434. . . Side wall

140, 240, 340, 440. . . First source/dip

142, 242, 342, 442. . . Second source/dip

150, 250, 350, 450. . . First conductivity type transistor

152, 252, 352, 452. . . Second conductivity type transistor

154, 254, 354, 454. . . Metal telluride layer

160, 260, 360, 460. . . Inner dielectric layer

162, 262, 362, 382, 462, 464. . . Opening

170, 172, 270, 272, 370, 372, 470, 472, 474, 476. . . Metal layer

280. . . Cover layer

282, 386. . . Contact hole etch stop layer

380. . . Tantalum nitride layer

Figure 1 is a diagram showing the relationship between the high-k dielectric layers EOT and V _fb of a PMOS device.

2 to 8 are schematic views showing a first preferred embodiment of the present invention.

9 to 15 are schematic views showing a second preferred embodiment of the present invention.

16 to 21 are schematic views showing a third preferred embodiment of the present invention.

22 to 26 are schematic views showing a fourth preferred embodiment of the present invention.

100. . . Base

102. . . Shallow trench isolation

104. . . High dielectric constant gate dielectric layer

106. . . Tantalum carbide layer

108. . . Polycrystalline layer

110. . . First active area

112. . . Second active area

122. . . Second gate

130. . . First lightly doped bungee

132. . . Second lightly doped bungee

134. . . Side wall

140. . . First source/dip

142. . . Second source/dip

150. . . First conductivity type transistor

152. . . Second conductivity type transistor

154. . . Metal telluride

160. . . Inner dielectric layer

162. . . Opening

Claims (20)

A method for fabricating a complementary metal oxide semiconductor (CMOS) device having a bimetal gate includes: providing a substrate, the surface of the substrate defining a first active region and a second active region; Forming a first conductive type transistor and a second conductive type transistor in the first active area and the second active area, the first conductive type transistor includes a first gate, and the second conductive type The crystal includes a second gate; performing a self-aligned metal salicide process to form at least a metal halide on the surface of the second gate; forming an inner dielectric layer on the substrate (inter-level) a dielectric layer, the inner dielectric layer exposing the top of the first conductive type transistor and the second conductive type transistor; performing a first etching process for removing the first conductive type a first gate of the transistor portion, and an opening is formed in the first active region, and a high dielectric constant gate dielectric layer of the first conductive type transistor is exposed to the opening Bottom; And forming at least a first metal layer in the opening. The method of claim 1, wherein the step of forming the first conductivity type transistor and the second conductivity type transistor further comprises: Forming the high dielectric constant gate dielectric layer and a tantalum carbide (TaC) layer and a polysilicon layer on the substrate; performing a lithography and etching process to etch the polysilicon layer, the tantalum carbide layer, and The high dielectric constant gate dielectric layer, and the first gate and the second gate are respectively formed in the first active region and the second active region; and the first gate and the second gate are respectively formed Forming a first lightly doped drain (LDD) and a second lightly doped drain in the base of the two sides; forming a first sidewall of the first gate and the second gate respectively a first source/drain and a second source/drain are respectively formed in the substrate on both sides of the first gate and the second gate. The method of claim 2, further comprising a second etching process, after the first etching process, the first etching process is for removing the polysilicon layer of the first conductive type transistor And the second etching process is for removing the tantalum carbide layer of the first conductive type transistor. The method of claim 2, further comprising the step of forming a protective layer in the first active region, and the protective layer covers the high dielectric constant gate dielectric layer. The method of claim 4, further comprising a third etching The process is performed after the first etching process to remove the protective layer and expose the high dielectric constant gate dielectric layer. The method of claim 2, further comprising a polysilicon oxidation step, after forming the first lightly doped drain and the second lightly doped drain to oxidize the first gate portion Or all of the polycrystalline layer. The method of claim 2, further comprising the step of forming a cap layer on the first gate, before the self-aligned metal telluride process, to avoid forming a top of the first gate Metal telluride. The method of claim 7, further comprising a fourth etching process for removing the cap layer before the first etching process. The method of claim 2, further comprising the step of forming a contact etch stop layer (CESL) on the substrate before forming the inner dielectric layer. The method of claim 9, further comprising a fifth etching process for removing the contact hole etch stop layer on the first gate before the first etching process. The method of claim 1, wherein the first metal layer comprises molybdenum nitride aluminum (MoAlN), tungsten (W), molybdenum nitride (MoN), carbon nitrogen. TaCNO, titanium nitride (TiN), or tungsten nitride (WN). The method of claim 1, further comprising the step of forming a second metal layer in the opening, after forming the first metal layer, and the second metal layer comprises aluminum (Al) , titanium (Ti), tantalum (Ta), tungsten (W), niobium (Nb), molybdenum (Mo), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti /W), or a composite metal such as titanium and titanium nitride (Ti/TiN). A method for fabricating a complementary metal oxide semiconductor device having a bimetal gate includes: providing a substrate defining a first active region and a second active region; wherein the first active region and the first Forming a first conductivity type transistor and a second conductivity type transistor in the active region, the first conductivity type transistor includes a first gate, and the second conductivity type transistor includes a second gate Performing a self-aligned metal telluride process to form at least a metal halide on the surface of the second gate; forming an inner dielectric layer (ILD) on the substrate, and exposing the inner dielectric layer a first conductive type transistor and a top portion of the second conductive type transistor; performing a first etching process to remove a first gate of the first conductive type transistor portion, and in the first active region Forming a first opening therein, And a high dielectric constant gate dielectric layer of the first conductive type transistor is exposed to the bottom of the first opening; at least a first metal layer is formed in the first opening; and a second etching process is performed, And removing a second gate of the second conductive type transistor portion to form a second opening in the second active region, and one of the second conductive type transistors has a high dielectric constant gate dielectric The layer is exposed to the bottom of the second opening; and at least a second metal layer is formed in the second opening. The method of claim 13, wherein the step of forming the first conductive type transistor and the second conductive type transistor further comprises: sequentially forming the high dielectric constant gate dielectric on the substrate An electric layer and a polysilicon layer; performing a lithography and etching process to etch the polysilicon layer and the high dielectric constant gate dielectric layer, respectively forming the first active region and the second active region a first light-doped drain (LDD) and a second light-doped drain are respectively formed in the base of the first gate and the second gate; Forming a sidewall on the sidewalls of the first gate and the second gate respectively; and forming a first source/drain and a gate in the bases on both sides of the first gate and the second gate Second source / drain. The method of claim 14, further comprising the step of forming a protective layer on the substrate, after forming the high dielectric constant gate dielectric layer, and the protective layer is The high dielectric constant gate dielectric layer is covered. The method of claim 15, further comprising a third etching process for removing the protective layer and exposing the high dielectric constant gate dielectric layer after the first etching process. The method of claim 13, wherein the first metal layer comprises aluminum molybdenum nitride, tungsten, molybdenum nitride, niobium carbonitride, titanium nitride or tungsten nitride. The method of claim 13, wherein the second metal layer comprises tantalum carbide or titanium aluminum nitride (TiAlN). The method of claim 13, further comprising the step of forming a third metal layer in the first opening and the second opening, respectively. The method of claim 19, wherein the third metal layer comprises aluminum, titanium, tantalum, tungsten, tantalum, molybdenum, titanium nitride, titanium carbide, tantalum nitride, titanium tungsten alloy, or titanium. Titanium nitride alloy.