TWI336845B - Bridges and the related electronic systems and methods for flushing data - Google Patents

Description

1336845 IX. Description of the invention: [Technical field to which the invention pertains] The present invention relates to a method for clearing data, in particular, to a material that can avoid data inconsistency without degrading performance, and the prior art Many computer systems use at least two bus bars. The military bar is usually called a memory bus for medium a, central processor and main memory. Communication, and, often, the peripheral bus is used for communication between the tweaking, smattering device, 乂h device (such as 厶h& system, disk drive or regional network) . The η ° horse makes the data transfer between the two busbars, usually it will pass. ^ _ φ 曰 Disaster use a bridge to connect the two busbars together. The main task of the bridge is to transfer data from one bus to another. In order to achieve this function, the bridge must have the slave capacity and the master capachy, so that it can receive the request from a bus as a slave component, and then act as the main component. Perform another appropriate bus operation on the other side. Therefore the 'bridge must have the ability to provide access from the bus to the other bus. The 5' bridge 15 will temporarily store (or post) the data to be transmitted from the system.

Client’s Docket No.: VIC07-0011 TT^ Docket N〇: 0608-A41152-TW/Final: In the device. ^ Data in the bridge can improve the performance of the system by encapsulating the data and pre-fetching the material. Then, when the synchronization event /Dennis 1336845 (synchronization event) occurs, the data is temporarily stored in the bridge, which will cause data inconsistency. SUMMARY OF THE INVENTION The present invention provides a bridge including a first main control element 'for outputting a cleaning request; a buffer unit including a plurality of buffers; and a cleaning request control circuit for receiving the cleaning request Detecting whether a plurality of buffers have been emptied, and recording buffers that have been emptied in the plurality of buffers. If the plurality of buffers have been emptied after receiving the cleaning request, outputting a clearing confirmation signal. In order to inform the first master element that the buffer unit is emptied. The present invention also provides a cleaning request control circuit for generating a cleanup completion confirmation signal in accordance with a cleaning requirement to indicate that all buffers of a buffer unit are emptied. The cleaning request control circuit includes: a plurality of detecting units respectively coupled to the buffers of the buffer unit, and determining, according to the cleaning request and the corresponding buffer outputting an idle signal output complex, the cleared signal to indicate the corresponding The buffer is cleared after receiving the cleaning request; and an output unit is configured to generate the cleaning completion confirmation signal when the plurality of detection units output the above determined clear signal. The invention further provides a data cleaning method for an electronic system, comprising: detecting whether a plurality of buffers in a buffer unit have been emptied when receiving a cleaning request from a first main control element in a bridge And recording the buffers that have been emptied in the plurality of buffers; and when the plurality of buffers have been emptied once after receiving the cleaning request, the output /Dennis

Client’s Docket N〇.:VIC07-0011 TT’s Docket N〇:0608-A41152-TW/Final 6 1336845 •—Clear the completion confirmation signal to the first master. In order to make the above and other objects and features of the present invention clear and easy to understand, the following is a special description of the 敕仵 敕仵 , , , , , , , 占 占 占 占 占 占 占 占 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 、 The drawings show the bamboo in detail as follows: [Embodiment] • The f 1 diagram is an embodiment of an electronic system. As shown in the figure, the electronic=system UKH system can be implemented in a computer system, but it is not limited to this, it can also be Lu, 'now in digital cameras, digital video recorders, consumer electronics, mobile devices, portable In electronic products or robots. The electronic system (10) is comprised of a master component ΜΑ, a slave component SA, a bridge 1 〇 and a peripheral device 20. For example, the main control component can be a central processing unit (CPU), the slave component S can be a system memory or one of the central processing unit cache memory, and the peripheral device 2 can be a Peripheral component interface (PCI) device, but is not limited thereto. The bridge 10 includes main control elements MB and MC, slave elements SB and SC, and buffer units BF1 and BF2, and the peripheral device 20 includes a master element MD and a slave element SD. Each buffer unit BF1 and BF2 package ' contains one or more buffers.

When the master element MA requests access to the slave component SD of the peripheral device 20, the slave component SB receives the transaction requests from the master component μα and pushes it into the buffer unit BF1. The master element MC performs the processing required by the slave element sb in the buffer unit BF1 so that the slave element SD accepts the processing request. Conversely, the master component MD in the winter peripheral device 20 requires access to the slave component SA.

Client's Docket No.: VIC07-0011 TT's Docket N〇: 0608-A41152-TW/Final /Dennis 1336845. The slave component SC will receive the transaction requests from the master component MD and put it into the buffer unit BF2. in. The master component MB performs the processing requirements placed by the slave component SC in the buffer unit BF2 such that the slave component SA accepts the processing request. In general, the processing requirement from the master element MA to the slave element SD is called downlink processing, and the processing requirement from the master element MD to the slave element, SA is called upstream transaction. In some cases, the processing in one direction (upstream or downstream) requires completion before the completion of the process, and the processing requirements in the other direction must be completed in order to maintain the order of processing requirements to avoid data consistency. . 1 For example, when the peripheral device 20 completes a write processing request and issues an interrupt signal to the main control unit MA (for example, a CPU), the notification can read a write data in the slave component SA (for example, system memory). . The master element MA issues a read request to the slave element SD to check the state of the peripheral device 2 before processing the data written in the slave element SA. The read request sent by the master component to the slave component SD is a synchronization event. Thus, the bridge 1 will terminate the processing of the new processing request from the master component MD and clear the data in the buffer unit BF2. To ensure the 'consistency of the data. In other words, the master component ΜΑ will first read the state of the slave component SD 'before the processing request is completed'. The bridge 1 must confirm that the pen write data has been placed in the slave component SA. Before the slave component SD reads the data or returns the read data to the master component MA, the bridge generates a flush request flush-req to the slave component sC, and waits for the slave component sc to reply to a cleanup. Confirmation signal (fl2

Client’s Docket No.: VIC07-0011 TT’s Docket Νο:0608·Α41152-TW/Final /Dennis 8 1336845 acknowledg^flush—ack indicates that the written data has been placed in the slave element SA.

However, when the slave component SC receives the cleaning request £jush_req, it will no longer put the data or instructions into the buffer unit BF2, that is, the slave component sc will stop working and the external master unit will retry. Process requests or issue a wait state. The cleanup completion confirmation signal (1) will be sent to ackn〇wledge) flush_ack will be cleared after all processing requests in buffer unit BF2 are cleared. Since the Dush_req is received when the cleanup request is received, the processing request will be stopped. The performance of the system will be reduced. In order to improve the performance of the system, the present invention also provides an embodiment thereof. The certificate 2 is a cleaning request control circuit of the present invention: an embodiment. The cleaning request control circuit 12 can be disposed in the bridge 1〇, and after receiving the cleaning request, flushing a req, the detection buffer unit wristband n buffers (for example, BF20~BF22) are cleared, open # 6 has recorded the buffers that have been cleared in the n buffers. If n buffers are not in the stagnation, and the sputum has cleared the flush request request after flush_req has been emptied once, then the output is cleared 6 + I to confirm the signal flush ack to the main control element MC. For example, the cleaning|supply control circuit 12 can be integrated into the slave component SC of FIG. 1, or can be placed between the master cell MC, the slave component %, and the buffer cell BF2. this. As shown in Fig. 2, the cleaning request release circuit 12 includes detection units 121, 122 and 123 and an output unit 1/) 124. The detecting units 121, 122 and 123 are configured to detect the phase buffer of the buffer unit BF2 when receiving the cleaning request fiush req of the self-control unit MC, and control whether the buffers BF20, BF21 and BF22 have been emptied. . Detection unit 121 you 4』 You include a register RGO and a /Denni:

Client's Docket No.: VIC07-0011 TT's Docket N〇: 0608-A41152-TW/Final 9 1336845 • The detection unit 122 includes a register RG1 and a processing unit 126, and the detection unit 123 includes A register RG2 and a processing unit 127. For example, when all the instructions or data stored in the buffers BF20, BF21, and BF22 are read or unloaded (m〇ve) by the main control unit MB, the buffers BF20, bfm, and 胂22 are regarded as Empty (idled, empty 〇r . , at this time the idle signals idle_0, idle_l and idle-2 of the buffers BF20, BF21 and BF22 will be set to high potential. When the detection unit parameter 121 detects the idle signal idle_0 is When set to high potential, it can be known that the buffer state BF20 has been cleared. Similarly, when the debt measurement unit 与 and 123 detect that the idle signals id]e_l and idle-2 are set to a high potential, It is known that the buffers BF21 and BF22 have been emptied. In most cases, the buffer BF2 〇, BF2l and BF22 are not in the idle state at the same time, so that the buffers RGO RG RG2 receive the buffer in this embodiment. When the idle signals idle_0, idle-1, and idle-2 of the high potentials of BF20, BF21 and BF22 are temporarily stored, the received idle signals idle_0, idle_l and idle_2 are temporarily stored and a corresponding cleared signal pending_ackO, pending_ackl is generated. With pending-ack2 for recording - under The buffers BF20, BF21 and BF22 are cleared after receiving the flushing request: flush_ack. At this time, the buffer that has been emptied is allowed to re-receive the slave component SC according to the processing request from the master component MD. For example, when the scratchpad RGO receives the idle signal idle-Ο with high potential, it will temporarily store the idle signal idle_0 and continuously generate a high/Dennis

Client's Docket N〇.:VIC07-0011 TT's Docket N〇:0608-A41152-TW/Final 1336845 The potential signal has been cleared to pencjing_ack〇, so that the buffer BF20 has been emptied. At this time, the 'bridge 1' allows the slave element SC to write the corresponding data or instruction to the buffer BF20 that has been emptied according to the processing request of the autonomous control element MD. If the signal pending_ackO has been cleared to a high level, the processing unit 125 outputs a high potential to clear the signal ack〇. Similarly, when the scratchpad receives the idle signal idle-1 with high potential, the idle signal idkj is temporarily stored and a high-potential cleared signal pending_ackl is continuously generated to record that the buffer BF21 has been emptied. And the bridge 1〇 allows the slave element SC to write the corresponding data or instruction to the buffer BF21 that has been emptied according to the processing request from the master element MD. Since the cleared signal pending_ackl is high, the processing unit 126 outputs a high potential to determine that the signal acki has been cleared. The action of the register RG2 is similar to the registers rgO~RG1, and will not be described again. If the buffers BF20, BF21, and BF22 have been emptied once after receiving the flush request flush-req, the output unit 124 outputs the cleanup completion confirmation signal flush_ack to the master element MC. If the buffers BF20, BF21 and BF22 have been emptied once after receiving the cleaning request flush_req, that is, the idle signals idle_0, idle_l and idle_2 have been set to a high potential, the output unit 124 will clear the signal ack according to the reception. The ackl and ack2 output cleanup completion confirmation signals flush_ack to indicate that the data stored by the buffer unit BF2 before receiving the cleanup request fjushjeq has been cleared. After the buffer BF20, BF21 or BF22 has been logged out, the bridge 10 allows the buffers BF20, BF21 and BF22 to receive from the slave /Dennis

Client's Docket N〇.:VIC07-0011 TT's Docket N〇:0608-A41152-TW/Final 11 1336845 * New data or new instructions for component SC, so even if the receiving of the master component mc is cleared, flush-req 'slave component The SC does not have to interrupt receiving the processing request from the master component MD, and continues to push the data and/or instructions into the buffer that has been emptied in the buffer unit BF2, so that the performance of the system will be effectively improved. ‘The third figure is another implementation of a cleaning control circuit in the present invention. Example. As shown in the figure, the cleaning request control circuit 13 includes detection units 121 to 123 and a gate AD4 serving as the output unit 124. Similarly, the cleaning request control circuit 13 can be integrated in the slave element SC of Fig. 1, or can be disposed between the master unit MC, the slave element SC, and the buffer unit BF2. The detection unit 121 and the gate AD Bu D-type flip-flop DFO and the multi-mode MUXO~MUX 1 constitute the register RGO ' and the gate AN 1 and the gate 0G1 shown in FIG. 2 constitute the second figure. Processing unit 125. And the AD 1 system has two input terminals respectively coupled to the idle signal idle_0 of the buffer BF20 of the buffer unit BF2 and the flush request reflu_req, and one round of the end coupled multiplexer MUX1. The multiplexer MUXO has two input terminals for respectively coupling to the output end of the D-type flip-flop DFO and the data "〇", (ie, low potential). More, the MUX1 has two input terminals coupled to the multiplexer respectively. The output of the MUX0 and the data "1" (ie, high potential), and an output coupled to the D-type forward and reverse DF0. The D-type flip-flop DF0 has an input coupled to the output of the multiplexer MUX1 The first clock input is coupled to a clock signal CLK1, and an output terminal outputs the cleared signal pending_ackO to the gate AN 1 and the input end of the multiplexer MUX0. The other input of the gate AN1 is connected to the cleanup. Flush_ack is required. Or gate OG1 has two inputs coupled to the gate/Dennis

Client's Docket No.: VIC07-0011 TT's Docket N〇: 0608-A41152-TW/Final 12 1336845 ·. The output of AN1 and the idle tag idle_0' of buffer BF20 in buffer unit bf2 and an output for output determination The signal ack has been cleared to the gate AD4. The circuit structures of the detecting units 122 and 123 are the same as those of the detecting unit 122, and thus will not be described again. The operation of the cleaning request control circuit 13 is explained below with reference to Fig. 4. - After receiving the cleanup request f!ush_req from the master control element MC, the D-type flip-flop DF0 outputs a high potential when receiving the idle signal idle_0 representing the high potential of the buffer BF20 has been cleared. The letter Pending-ack0 has been cleared. For example, when the cleanup request flushjeq and the idle nickname idle_0 are both potential, the output of the gate ad 1 will change from a low potential to a good potential, so that the high potential signal (ie, data, 1 ′) will be used by The multiplexer MUX1 outputs to the D-type flip-flop DFO, so the wheel-out terminal of the D-type flip-flop DF0 changes from a low potential to a high potential (ie, the output has cleared the signal pending_ackO) to indicate that the corresponding buffer is emptied. The cleared signal pending_ackO with high potential is also coupled to one of the inputs of MUX1 by the multiplexer 。. Since the control terminal of the multiplexer 接 is connected to the high potential cleaning request flush_req, thus more Both inputs of the device Μυχι are high, so regardless of the output of the gate AD1, the D-type positive and negative DFO output (empty number pending-ackO) will remain at a high potential. In other words, 'cleanup request control The circuit 13 has recorded the buffer BF20 which has been emptied after receiving the flush request flush_req. Therefore, even if the idle signal idle_0 becomes low due to the buffer BF20 being pushed by the slave element SC by the data or instruction Bits, the signal has been cleared pending_ackO D type flip-flop DF1 of the output will remain at a high potential, and such that / Dennis

Client's Docket N〇.:VIC07-0011 TT's Docket No:0608-A41152-TW/Final 13 1336845 Gate AN 1 outputs a high potential signal to or gate g〇, which in turn causes the gate G i to continuously output a high potential. The signal ack〇 has been cleared. Similarly, when receiving the idle id number id 2 representing the high potential of the buffer BF22 that has been emptied, the D-type flip-flop DF2 outputs a cleared signal pending_ack2 having a high potential indicating that the cleaning request control circuit 13 has The δ recorded buffer state BF22 has been emptied after receiving the cleanup request fjush_req. Therefore, even if the idle signal idle_2 becomes low due to the buffer BF22 being placed in the (pUSh) data or instruction by the slave element SC, the output of the d-type flip-flop DF2 is maintained at a high potential (the signal pending_ack2 is cleared), so that Or the gate G3 continuously outputs a high potential to confirm that the signal ack2 has been cleared. When the idle signal idle_l of the zeta potential is received, it means that the buffer BF21 has been emptied. At this time, the corresponding signals ack〇 and ack2 and the idle signal idle_l are both 咼 potentials. That is, all the buffers BF20 BFBF22 in the buffer unit BF2 have been emptied after receiving the cleaning request flush_req, and thus the output of the gate AD4. It will change from low to high (output clearing completion confirmation signal flush_ack to master element MC). After the cleaning completion confirmation signal flush_ack becomes high, the cleared signal pending_ackO~pending_ack2 is cleared in the next cycle. For example, if the flush completion acknowledge signal flush_ack is high, the flush request flush_req will be set low, causing the multiplexer MUX0 to output a low potential signal (ie, data 0) to the multiplexer MUX1. Since the output terminals of the gate AD1 and the multiplexer MUX0 are both low at this time, the multiplexer MUX1 outputs the low-level data 0 to the D-type flip-flop DF0, so the D-type flip-flop DF0 /Dennis

Client's Docket No.: VIC07-0011 ΊΓΤ^ Docket No:0608-A41152-TW/FinaI 14 1336845 * The rounded up signal pending_ackO changes from high to low. In the present embodiment, since the cleared signal pending_ack0~pending_ack2 is cleared in the next cycle in which the cleaning request flush_req becomes low, the gate AN1 is set to prevent the cleaning request circuit 13 from outputting an incorrect cleaning completion confirmation signal flush_ack. ^ Figure 5 is another embodiment of a cleaning control circuit in the present invention. As shown, the cleaning request control circuit 14 includes inverters INVO to INV2, and gates AD1 to AD4, multiplexers MUXO to MUX5, positive inverters DFO to DF2, and or gates 0G4 to OG6. Similarly, the cleaning request control circuit 14 may be integrated in the slave element SC of Fig. 1, or may be provided between the master unit MC, the slave element SC, and the buffer unit BF2. For example, the inverter INVO, and the gate AD1, the multiplexers MUX0 to MUX1, the flip-flop DFO, and the gate 0G4 may constitute the town-measurement unit 121 shown in FIG. 2; the inverter INV1 and the gate AD2. The multiplexers MUX2 to MUX3, the flip-flop DF1, and the gate 0G5 may constitute the detecting unit 122 shown in FIG. 2; the inverter INV2, the gate AD3, the multiplexers MUX4 to MUX5, the flip-flop DF2, and Or gate 0G6 can constitute the detection unit 123 shown in Fig. 2, and gate AD4 can be regarded as the output unit 丨24 shown in Fig. 2. And the AD1 system has three input terminals respectively coupled to the inverter INVO: the output terminal, the idle signal idle__〇 of the buffer BF20 in the buffer unit BF2, the flushing request flush_req, and the one-end coupling multiplexer MUX 1. The circumscribing MUXO has two input terminals for respectively connecting to the output end of the d-type flip-flop DFO and the data (ie, low potential). The multiplexer muxi has two input ends respectively coupled to the output end of the multiplexer MUX0 and

Client's Docket N〇.:VIC07-0011 TT's Docket N〇:0608-A41152-TW/Final /Dennis 15 1336845. Material "1" (ie high potential) and - wheel end coupled to D-type flip-flop DF〇 D-type flip-flop DFO has an input terminal that is connected to the output end of the multiplexer ,1, a clock input terminal coupled to a clock signal CLK1, and an output end face connected to the gate 0G4 and the multiplexer MUXO. An input terminal and a gate AD2 have three wheel terminals respectively _ connected to the inverter output terminal, the buffer unit BF2 buffer BF21 idle signal idle j. With the cleaning requirements, and an output coupled to the multiplex Μυχ3一. The multiplexer MUX2 has two input terminals for coupling to the output of the D-type flip-flop • DF1 and the data “〇, (ie, the low-potential multiplexer 具有3 has two inputs coupled to each other at most The output of the MUX2 and the material "1" (ie high potential), and an output end are coupled to the D-type flip-flop DF1. The D-type flip-flop DF1 has an input coupled to the output of the multiplexer Μυχ3 The first clock input is coupled to a clock signal CLK1, and an output is coupled Or gate OG5 and one of the inputs of the multiplexer MUX2. And the gate AD3 has two wheel-in terminals respectively connected to the output of the inverter ΙΝ γ2, the idle signal idle id of the buffer BF22 in the buffer unit BF2 • and cleaning Flush-req is required, and an output is coupled to the multiplexer MUX5. ^ Multi-function MUX4 has two inputs for respectively coupling to the output of the D-type flip-flop DF2 and data (ie, low potential). The Μυχ5 has two input terminals coupled to the output of the multiplexer MUX4 and the data "1" (ie, high potential), and an output coupled to the D-type flip-flop DF2. The D-type flip-flop DF2 has an input The output end is coupled to the output end of the multiplexer '5. One clock input terminal is coupled to a clock signal CLK1, and an output terminal is coupled to one of the input terminals of the OR gate 0G6 and the multiplexer MUX4. ^Dennis

Client's Docket N〇.:VIC07-0011 TT's Docket N〇:0608-A41152-TW/Final 16 1336845 or gate 0G4 has two inputs coupled to the output of the 正-type flip-flop DFO and the buffer in the buffer unit BF2 The idle signal idle_0 of BF20. Or the gate OG5 has two input terminals respectively connected to the output end of the d-type flip-flop DF1 and the idle signal idle_l of the buffer BF21 in the buffer unit BF2. Or the gate OG6 has two input terminals respectively coupled to the output end of the d-type flip-flop DF2 and the idle signal idle_2 of the buffer BF22 in the buffer unit BF2. The gate AD4 has three input terminals respectively coupled to the input terminals of the gates G4, OG5 and OG6, and an output terminal coupled to the input terminals of the inverters INV0 to INV2. The operation of the cleaning request control circuit 14 is explained below with reference to Fig. 6. After receiving the flush request request flush_req from the master control element MC, when receiving the high potential idle signal idlej) that the buffer BF20 has been cleared, the D-type flip-flop DF0 outputs the cleared signal pending_ackO having a high potential. . For example, since the flush completion acknowledgment signal flush_ack is still asserted at this time, the output of the inverter INV0 is at the south potential. Therefore, when the cleaning request fjush_;req and the idle signal idle_0 are both high, the output of the gate AD1 will change from a low potential to a high potential, so that the high potential signal (ie, the data "1") will be passed through the multiplexer. MUX 1 is output to the D-type flip-flop DF0, so the output of the D-type flip-flop DF0 will change from low to high (ie, the output has cleared the signal pending_ackO) 'to indicate that the corresponding buffer is cleared. At the same time, the cleared signal pending_ackO with high potential is also coupled to one of the inputs of MUX1 by the multiplexer MUX0. Since both inputs of the multiplexer MUX1 are high,

Client's Docket N〇.:VIC07-0011 TT's Docket N〇:0608-A41152-TW/Final /Dennis 1336845 and the output of the gate AD1, the output of the D-type flip-flop DF1 (empty signal pending_aCkO) will remain in High potential. In other words, the cleanup 2 control circuit 14 has recorded the buffer BF2 and has been emptied after receiving the flush request flush_req. Therefore, even if the idle signal idle_0 becomes low due to the buffer BF2 being pushed by the slave component SC to the data or the instruction, the cleared signal pending-ack of the D-type flip-flop DFO output is maintained at The high potential causes the gate 0G4 to continuously output a high potential to confirm that the signal ack〇 has been cleared. Similarly, when receiving the high-level idle signal idle-2 representing that the buffer BF22 has been emptied, the D-type flip-flop DF2 outputs a cleared signal pending_ack2 having a high potential, indicating that the cleaning request control circuit 14 has recorded the buffer. The BF22 has been emptied after receiving the cleanup request fiush-req. Therefore, even if the idle signal idle_2 becomes low due to the buffer BF22 being pushed by the slave element SC, the output of the d-type flip-flop DF2 is maintained at a high potential (the signal pending_ack2 is cleared). The determination that the gate 6 continues to output a high potential has cleared the signal ack2. When the high potential idle signal idle_l is received, it means that the buffer BF21 has been emptied. At this time, the corresponding signals ack〇 and acci2 and the idle signal idle_l are all high, that is, all the buffers BF20~BF22 in the buffer unit BF2 have been cleared after receiving the flush request flush_req, so the output of the gate AD4 It will change from low to high (output clearing completion confirmation signal flush_ack to master element MC). The signal has been cleared after the cleaning completion confirmation signal flush_ack goes high /Dennis

Client’s Docket No.: VIC07-0011 TT's Docket N〇: 0608-A41152-TW/Final 18 1336845 - Pending_ack0~pending_ack2 will be cleared. For example, if the cleaning completion signal flush_ack is high, and the output terminals of the gate AD1 and the multiplexer MUXO are both low, the multiplexer MUX1 outputs low potential data to the D-type flip-flop DFO. The D-type flip-flop DFO output has cleared the signal pending ackO is cleared (from high to low). • In fact, the cleaning request control circuit μ in Figure 5 may not include the inverse phase comparators WV0~INV2 'that is, and the gates AD1 to AD3 contain only two outputs, respectively receiving the flush request flush_req and the corresponding idle signal ❿ idleO~ Idle2. However, when the cleaning completion confirmation signal f]ush_ack is high and the idle signal and the cleaning request flush_req are both high, the multiplexer (for example, MUX1) and the corresponding D-type flip-flop (DF0) will be based on the gate (AD1). The output signal is subjected to unnecessary operations. To prevent this from happening, it can be set by the master component MC: if the cleanup completion acknowledge signal flush_ack is high, the flush request signal flush_req is held low. In this embodiment, the slave component SC does not need to interrupt receiving the processing request from the master component MD even if it receives the flush request-req of the master component MC, and can continue to put the data and/or instructions into the buffer. The buffer in cell BF2 has been emptied' so the performance of the system will be effectively boosted. Figure 7 is another embodiment of the electronic system of the present invention. As shown in the figure, the 'electronic system 100' is similar to the electronic system 1 shown in Fig. 1, with the difference that the cleaning request control circuit 12 shown in Fig. 2 is added to the slave element SC of the bridge 1〇. For example, 'bridge 1 can be - north

Client's Docket N〇.: VIC07-0011 /Dennis TT's Docket No:〇6〇8-A41152-TW/Final 19 1336845 Bridge crystal two weeks: ί bridge wafer or a combination thereof, but is not limited thereto. The field and clothing set 20 completes a write processing request, and issues a number to the main control 4 (for example, which), the notification can be read in the system memory, the write-write capital #, and the belonging SA (for example, Λ #. In the shirt member (4) in the service component SA, the master component Μα will check the peripherals of the 'master component ΜΑ will read the slave component's milk shape before the processing request is completed, the bridge] () must confirm

It has been released into the subordinate tree SA. The slave component commits the reading data ^ = before the data of the :: is returned to the master component MA, the bridge ι〇; generates - flushes the request f!ush_req to the slave component %, and waits for a few pieces of SC Reply-cleanup completion confirmation signal (flush ackuoWledge) flush-aek indicates that the writer has been placed in the SA.冨Main component] When V1C issues the cleaning request fjush-req, the cleaning request control circuit 12 in the bridge 1 侦测 detects n buffers in the buffer unit BF2 when receiving the cleaning request (for example, BF〇〇~Bf〇 2) * No cleared 'and recorded the buffers that have been cleared in n buffers. When ^ buffers have been cleared once after receiving the cleaning request fjush_req, then the output clear completion confirmation signal f!ush_ack to The master component MC indicates that the data or instruction written before the flush request flush_req was received has been read. Therefore, the slave component SC does not interrupt the reception of the processing request from the master component MD in the peripheral device 20 due to the cleaning request flush_req issued by the master component MC, and can continue to put the data and/or instructions into the buffering unit BF2. So that the performance of the system will be effectively improved. In some real

Client's Docket No.: VIC07-0011 TT's Docket No: 0608-A41152-TW/Final /Dennis In the example, the ''green request request control circuit 12' may be provided in the SB and the SD, but is not limited thereto. , ' Although this issue has been exposed as above, it is not used to it: send: 'any well-known craftsman' without leaving the spirit of the invention and α 'although some changes and refinements can be made' The protection model of the invention is subject to the definition of "special _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Cleaning requirements control circuit - implementation = 3 diagram is the 2Sj towel cleaning requirements (four) secret circuit = for the cleaning of the control circuit in Figure 3: the composition diagram is the cleaning operation of the control circuit in Figure 2 - The signal timing diagram of the cleaning request control circuit in the second figure is another embodiment of the electronic system of the present invention. [Main component symbol description] 1〇: bridge; 12~14: cleaning request control circuit; 20: Peripheral vibration; 121~123: pre-measurement unit; 124: output unit; 125~127: processing unit; /Dennis

Client's Docket No.:VlC〇7-〇〇n TT's Docket N〇:0608-A41152-TW/FinaI 1336845 .. 100,100”: electronic system; RG0~RG2: register; OG1~OG6: or gate; AD1 ~ AD4, AN1 ~ AN3: and gate; MA, MB, MC, MD: main control components; . SA, SB, SC, SD: slave components; BF BF2: buffer unit; BF20 ~ BF22: buffer Lu MUX0~MUX5: multiplexer; INV0, INV2: inverter; DF0~DF2: D-type flip-flop; flush_req: cleanup request; flush_ack: cleanup completion acknowledgement; idleO~idle2: idle signal; pending_ackO~pending —ack2 : The signal has been cleared; ackO~ack2: It is determined that the signal has been cleared; • CLK1: Clock signal.

Client's Docket N〇.:VIC07-0011 TT’s Docket N〇:0608-A41152-TW/Final /Dennis 22

Claims (1)

1336845 Case No. 096127719 November 4, 1999 Revision 4 This patent application scope: tt年丨丨月}曰修正1. A bridge, including · a first main control component for outputting a cleaning request; a buffer unit comprising a plurality of buffers; and a cleaning request control circuit, detecting that the plurality of buffers have been emptied when receiving the cleaning request, and recording that the plurality of buffers are emptied a buffer, if the plurality of buffers have been emptied after receiving the cleaning request, outputting a cleaning completion confirmation signal to notify the first main control unit that the buffer unit is emptied; wherein the cleaning request control circuit includes The plurality of detecting units are correspondingly coupled to the plurality of buffers. When any one of the buffers is emptied, the corresponding detecting unit outputs a determined clear signal; and an output unit is configured to When the plurality of detecting units output the above determined clear signal, the cleaning completion confirmation signal is generated; wherein the plurality of detecting units The measuring units each include: a buffer, generating a cleared signal according to the cleaning request and one of the idle signals sent by the corresponding one of the buffers, to indicate that the corresponding buffer receives the cleaning request Is cleared; and a processing unit generates the above determined clear signal according to the cleared signal and the idle signal. 2. The bridge of claim 1, wherein after receiving the cleaning request, the buffer unit receives information from a first slave component of VIC07-0011/0608-A41152-TW/Finall 23 1336845 or instruction. 3. The bridge according to claim 1, wherein the processing unit comprises: a gate, having two outputs respectively receiving the cleared signal and a cleaning request; and a gate or a gate output according to the gate The signal and the corresponding idle signal sent by the corresponding buffer output the above determined clear signal. 4. The bridge of claim 1, wherein the plurality of detecting units detect whether the corresponding buffer has been emptied according to the corresponding idle signal. 5. The bridge of claim 1, wherein the plurality of detecting units clear all of the cleared signals after the cleaning request control circuit outputs the cleaning completion confirmation signal. 6. The bridge of claim 1, wherein the register of the plurality of detection units further generates the cleared signal according to the cleaning completion confirmation signal. 7. The cleaning request control circuit is configured to generate a cleaning completion confirmation signal according to a cleaning requirement to indicate that all buffers of a buffer unit are emptied, and the cleaning request control circuit comprises: a plurality of detection units coupled separately Corresponding to one of the buffers of the buffer unit, and outputting at least one determined clear signal according to the cleaning requirement and at least one idle signal sent by the corresponding buffer, to indicate that the corresponding buffer receives the cleaning After the request is cleared; and an output unit is configured to generate the above clearing completion confirmation signal when the plurality of detecting units are outputted above VIC07-0011 / 0608-A41152-TW/Final 1 24 1336845 The plurality of detecting units each include: a register, and generating a cleared signal according to the cleaning request and the corresponding idle signal, to indicate that the corresponding buffer is emptied after receiving the cleaning request. And a processing unit, according to the above cleared signal and the idle signal, generated OK signal has been cleared. 8. The cleaning request control circuit according to claim 7, wherein the processing unit comprises: a gate, having two outputs respectively receiving the cleared signal and the cleaning request; and a gate or the The signal output from the gate is outputted with the corresponding buffer corresponding to the above, and the output clear signal is outputted. 9. The cleaning request control circuit according to claim 7, wherein the plurality of detecting units clear all the cleared signals after the cleaning request control circuit outputs the cleaning completion confirmation signal. 10. The cleaning request control circuit of claim 7, wherein the register of the plurality of detecting units further generates the cleared signal according to the cleaning completion confirmation signal. 11. The cleaning request control circuit of claim 7, wherein the plurality of temporary registers each comprise: a gate and a gate for receiving the cleaning request and the corresponding idle signal; a first multiplexer, Selectively outputting the cleared signal and a low bit signal according to the cleaning completion confirmation signal; VIC07-0011 /0608-A41152-TW/Final 1 25 13-36845 - second multiplex H' is used according to the above _Output output of the first multiplexer wheel 屮 产 产 & & & & & & & & & f f f f f f f f f f f f f f f f f f f f f f f f f f f f f 虎 虎 虎The wheel number 'generates the above cleared signal. ^ 12. An electronic system data flushing method, comprising: detecting a plurality of buffers in a buffer unit when receiving a cleaning request from a first-master component of a bridge Clearing, recording the buffers in the plurality of buffers that have been emptied; " when the plurality of buffers have been emptied after receiving the above cleaning request - output - clearing completion confirmation signal to the above control a component; when the buffer is emptied, the output determines that the signal has been emptied to record the emptied buffer; and the idle signal is generated according to the cleaning request and the corresponding buffer is generated - Clearing the signal 'to indicate that the corresponding buffer has been emptied after receiving the cleaning request; and generating the above determined clear signal based on the cleared signal and the idle signal. 13. The data processing method of an electronic system according to claim 12, wherein the buffer unit receives the data or instruction from a first slave component after receiving the cleaning request. 14. The method for cleaning data of an electronic system according to claim 12, wherein the corresponding VIC07-0011 / 0608-A41152-TW/Final 1 26 13.36845 buffer is detected according to the corresponding idle signal. Was cleared. 15. The data clearing method of the electronic system of claim 12, further comprising: after outputting the cleaning completion confirmation signal, clearing all of the cleared signals. VIC07-0011/0608-A41152-TW/Finall 27