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TWI311367B - Chip structure - Google Patents

Chip structure Download PDF

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Publication number
TWI311367B
TWI311367B TW095126002A TW95126002A TWI311367B TW I311367 B TWI311367 B TW I311367B TW 095126002 A TW095126002 A TW 095126002A TW 95126002 A TW95126002 A TW 95126002A TW I311367 B TWI311367 B TW I311367B
Authority
TW
Taiwan
Prior art keywords
wafer structure
bump
wafer
top surface
soft
Prior art date
Application number
TW095126002A
Other languages
English (en)
Other versions
TW200807655A (en
Inventor
Yu-Lin Yang
Original Assignee
Chipmos Technologies Inc
Chipmos Technologies Bermuda
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Chipmos Technologies Inc, Chipmos Technologies Bermuda filed Critical Chipmos Technologies Inc
Priority to TW095126002A priority Critical patent/TWI311367B/zh
Priority to US11/550,304 priority patent/US7528495B2/en
Publication of TW200807655A publication Critical patent/TW200807655A/zh
Application granted granted Critical
Publication of TWI311367B publication Critical patent/TWI311367B/zh

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Description

I311367〇 05003 20313twf,doc/0〇6 九、發明說明： 【發明所屬之技術領域】 ^ 本發明是有關於一種晶片結構，且特別是有關於一種 、具有軟性凸塊的晶片結構。 【先前技術】 在半^r體產業中’積體電路（integrated circuits，1C) 的生產主要可分為三個階段：積體電路的設計（扣 瞻 design)、積體電路的製作（ICpr〇cess)及積體電路的封 裝（IC package) ° ,在積體電路的製作中，晶片（chip)是經由晶圓（wafer) 製作、形成積體電路、電性測試（electrical testing)以及 切軎彳晶圓（wafer sawing)等步驟而完成。晶圓具有一主動 面Uctivesurface)，其泛指晶圓之具有主動元件（active dev1Ce)的表面。當晶圓内部之積體電路完成後，晶圓之 • 主動面將配置有多個焊墊（bondingpad)，以使最終由晶 # 圓切割所形成的晶片可經由這些焊墊而向外電性連接於一 承载器（carrier )。 請參考圖1，其繪示習知之一種晶片結構的側視示意 圖。習知晶片結構100包括一基材（substrate) 11〇、多個 晶片焊墊（chip bonding pad) 12〇、一保護層（passivati〇n layer) 130 與多個導電凸塊（conductivebump) 14〇。基材 110具有一主動面112’而這些晶片焊墊]2〇配置於主動面 112上。保護層13〇覆蓋主動面】丨2 ’且暴露出這些晶片焊 5 13 11 ^5003 20313twf.doc/006 塾：：：乍塊:°分別配置於這些晶片焊 (未㈣=㈣崎（細— f+虛然而’在玻璃基板上’被設計要與這此導電&姊140 射應電性連接的這些電性接點Z Μ凸塊140 計或其他因素而無法完全: = 由於佈線設 進而使得這些晶片焊墊“=應 7配置（redistribution)的處理是必要的。 【發明内容】 本發明之目的是提供一種晶片結構，A曰 — 由軟性凸塊與重配置導電跡線而適連：干：可藉 電性接點。 L關連接至承載器的 為達上述或是其他目的，本發明提出 其包括-基材、至少一晶彻、一保蠖層、 凸塊（compliant; bump )與至少_ | ^ 專人卜生 (redistribution conductive trace)。基材具導電跡線 片焊墊配置於主動面上。保護層配置於主' 主動面’日日 出':曰:片焊墊。軟性凸塊具有-頂面與1面面i中= 分軟性凸塊配置於保護層上。重配置導 /、r芏夕邛 片焊墊電性連接，且重配置導電跡線的^端與晶 凸塊的部分側面與至少部分頂面。 而復盖於軟性 在本發明之一實施例中，上述之軟性凸塊可配置於晶 Ι3113ώ7〇 05003 20313twf.doc/006 片焊墊與保護層上，且軟性凸塊可覆蓋部分晶片焊墊。 在本發明之一實施例中，上述之軟性凸塊可配置於保 護層上。 在本發明之一實施例中，上述之軟性凸塊可配置於保 護層上。此外，上述部分重配置導電跡線可配置於保護層 上。 在本發明之一實施例中，上述之軟性凸塊之頂面可為 規則形狀。 在本發明之一實施例中，上述之軟性凸塊之頂面可為 規則形狀。此外，上述之軟性凸塊之頂面可為矩形。 在本發明之一實施例中，上述之軟性凸塊之頂面可為 規則形狀。此外，上述之軟性凸塊之頂面可為圓形。 在本發明之一實施例中，上述之軟性凸塊之頂面可為 規則形狀。此外，上述之軟性凸塊之頂面可為環形。 在本發明之一實施例中，上述之軟性凸塊之頂面可為 不規則形狀。 在本發明之一實施例中，上述之軟性凸塊的數量可為 多個。 在本發明之一實施例中，上述之軟性凸塊的數量可為 多個。此外，上述這些軟性凸塊可排列為陣列（array )。 在本發明之一實施例中，上述之軟性凸塊的材質包括 聚亞醯胺（polyimide)。 在本發明之一實施例中，上述之軟性凸塊的厚度可大 於等於5微米且可小於等於11微米。 13113&7c 05003 20313twf.doc/006 在本發明之-實施例中，上述之位於軟性凸塊之頂面 上的重配置導電跡線之一端的表面粗糖度可大於〇微米且 可小於等於1微米。 在本發明之-實施例中，上述之重配置導電跡線的厚 度可大於等於2微米且可小於等於6微米。 在本發明之-實施例中，上述之晶片結構更包括一異 方性導電膜（am她Qp⑽nduetivefllm)，配置於位於軟 性凸塊之頂面上的重配置導電跡線之一端上。 =發明之-實施例中，上述之保護層的材質包括聚 亞鯭胺或苯並環丁烯（b_Cyd〇bmene，BCB) 接時基:上述地當晶片結構與承載器上的電性接點電性連 Ϊ二=塊與電性接點相對應連接，所以晶片焊 的電::=重配置導電跡線而電性連接細 於外，因此本曰片導電跡線所覆蓋而暴露 口此田日日片結構與承载器彼此 :適度的變形而仍維持晶片結;二可 連接的效能。另外，由於a ，之間良好的電性 而連接至多個軟性凸 間彼此電性連接的接觸面積，及二==載畈 為讓本發明之上述和其 & ^的機率。 明如下。 '土舞並配合所附圖式，作詳細』 8 13 11 36^50, 03 20313twf.doc/006 【實施方式】 立圖2A繪不本發明一實施例之一種晶片結構的俯視示 =圖，圖2B繪示圖2A之晶片結構沿著、線A_A的剖面示 思圖’而圖2C I會示圖2A之晶片結構沿著線B_B的剖面 =意圖。請參考圖2A、圖2B與圖2C，本實施例之晶片 ί構2⑻包括一基材21〇、至少一晶片焊墊220 (圖2A示 二地~不6個）、-保護層23〇、至少一軟性凸塊24〇 (圖 ^意地_ i 5個）與至少一重配置導電跡線2 5 〇 (圖 曰不意地緣示6條）。基材21〇具有一主動面212，這些 :片焊墊220配置於主動面212上。保護層23〇配置於^ 面212上，且暴露出這些晶片焊墊22〇。 24/ΓΙ义f個軟性凸塊240具有—職242與一側面 上。H ^軟性凸塊24G至少部分地配置於保護層23〇 片焊墊220的】= 250 ::端對應;_ 250的另-端對應覆蓋各個軟性凸置導電跡線 與至少部分頂面242个：：塊240的部分侧面244 244有一部八3去二°平5之，各個軟性凸塊240的側面 外，且在本實施例中，斤此舌π 、、泉250所復盍而暴露於 # ★炎& D二重配置導電跡線250可依昭i =概,t綱物崎娜㈣24〇;ς 板是麵基 由於這娜卿物输 9
Bum 05003 20313twf.doc/006 這些晶片谭墊220可藉由這些軟性凸塊2 4 〇與這些重配置 導電跡線250而電性連接至相對應的這些電性接點上。因 此’本實施例之晶片結構可避免習知之晶片結構刚 (見圖I)的這些晶月焊墊⑽與承载器之這此電性接點 之間無法完全對應電性連接的缺點。此外，由料性 凸塊細的材質較軟恤邊），且各個軟性凸塊；40的 側面244有-部分是未被重配置導電跡線 卜，因此當晶片結構與承载器(一上It t時，各個軟性凸塊可作適度的變形而仍維持晶片结 構200與承載器之間良好的電性連接的效能。 請參考圖2A ’在本實施例中’各個^ ^ 242的外型可為規則形狀，例如為_或』, 各個軟性凸塊240之丁㈤42的外型亦可為苴他 則形狀或不規則形狀。此外，簡2A的 ^規 ΐ== ΐΓί Γ1跡線2 5 Q之—端可覆蓋多個軟性凸 塊240，且這魏性凸塊可排列為陣列。在此必 明的是，這些軟性凸塊240之頂面242㈣型、、士此^ 凸塊240的數量與排列方式可依照設計者 化二权性 本實施例是用以舉例而非限定本發明。、而/而改又， 請參考圖2B，在本實施例中’有些軟性凸塊·
元全配置於保護層230上，且圖2B中的 、 T 2S0的-部份可配置於保護層23〇上，=導電跡線 質包括聚亞_或苯並環丁稀。然而，請失^曰230的材 實施例中’有一軟性凸塊24。亦可配置於晶片二C; 10 13 1 1 ^6^5003 20313twf.d〇c/Q06 保護層230上，且此軟性凸塊24〇可覆蓋部分晶片焊墊 220。請參考圖2A、圖沈與圖X：，在本實施例中，這些 軟性凸塊240的材質包括聚亞醯胺，且各個軟性凸塊24〇 的厚度τι (亦即各個軟性凸塊24〇之頂面撕與保護層 之間的距離）可大於等於5微米且可小於等於u微 ^若1數學式表示則為5峻T1幻W在此必須說明 二’貝際ΐ，這些軟性凸塊240的厚度丁1可能有些許 塊2口40 軟/生凸塊240有高有低，但是各個軟性凸 尤〇的厚度丁1仍可位於上述的範圍之内。 “此H卜’請再參考圖2Β與圖2C，在本實施例中，位於 2〇1二二2:广頊面242上的這些重配置導電跡線 微米且可= 高度粗趟度)可大於。 度T2可大於等於2 且導電跡線250的厚 實施例之晶片結構200更包括一里方2微米。另外，本 省略緣示），其配置於位於料軟性“=26()(圖Μ 上的這些重配置導電跡線25〇之—=塊里24之頂面加 ^以將位於這些軟性凸塊24〇之頂導電膜 V電跡線250之—端對應黏接與電性連接重配置 卞）的故些電性接點（未績示）。 承载為（未繪 、’·τ上所述，本發明之晶片結構至少罝 卞一、當晶片結構與承載器上的多個電、有下列優點： :性連接時，由於這些軟性凸塊與這些電=點（未繪示） 這些晶片焊塾可藉由這些軟性心
20313twf.d〇c/〇〇6 導電跡線而電性連接至相對應的這 二、由於這些軟性凸塊的材質較敕，=上。 之側面的一部分是未被重配置且各個軟性凸塊 外，因此當晶片結構與承裁器彼此;：=蓋而暴露於 可作適度的變形而仍維持晶片結構與各個軟性凸塊 性連接的效能。 一栽為之間良好的電 導電-可藉由這些重配置 晶片結構與承載器之間彼此電:面;此可增加 結合失敗的機率。 电丨连獲的接觸面積，及減少 限定㈣如上，输非用以 脫離本發k ± =_技觸財具㈣常知财，在不 為準。 …耗圍當視後附之申請專利範圍所界定者 【圖式簡單說明】 =會不習知之—種晶片結構的侧視示意圖。 圖2A检千士 ~ $圖。 曰’、5明—貫施例之一種晶片結構的俯視示 卜圖25、會不圖2Α之晶片結構沿著線Α-Α白勺剖面示意 。圖2C、’’s不圖2Α之晶月結構沿著線Β_Β的剖面示意 12 BUM 5003 20313twf.doc/006 【主要元件符號說明】
100、200 :晶片結構 110、210 :基材 112、212 :主動面 120、220 :晶片焊墊 130、230 :保護層 140 :導電凸塊 240 :軟性凸塊 242 :頂面 244 :側面 250 :重配置導電跡線 260 :異方性導電膜 T1 :軟性凸塊的厚度 T2 :重配置導電跡線的厚度
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Claims (1)

1311367
98-4-16 十、申請專利範圍： 1 · 一種晶片結構.，包括： 一基材，具有一主動面； 至少一晶片焊墊，配置於該主動面上； 一保護層，配置於該主動面上，且暴露出讀晶片焊墊； 多個軟性凸塊，分別具有一頂面與一側面，其中至少 部分該些軟性凸塊完全配置於該保護層上； 、
至少-重配置導電跡線，其中該重配置導電跡線的一 端與該晶片焊墊電性連接，且該重配置導電跡線的另一端 覆盍於該些軟性凸塊的部分該些侧面與至少部分該此頂 面；以及 以一、 一異方性導電膜，配置於位於該些軟性凸塊之該些頂 面上的該重配置導電跡線之一端上。 2·如申請專利範圍第丨項所述之晶片結構，其中該軟 性凸塊配置於該晶片焊墊與該保護層上，且該軟性凸塊覆 蓋部分該晶片焊墊。
3·如申請專利範圍第丨項所述之晶片結構，其中該軟 性凸塊配置於該保護層上。 4. 如申請專利範圍第3項所述之晶片結構，其中部分 該重配置導電跡線配置於該保護層上。 5. 如申請專利範圍第1項所述之晶片結構，其中該軟 性凸塊之該頂面為規則形狀。 6. 如申請專利範圍第5項所述之晶片結構，其中該軟 性凸塊之該頂面為矩形。 14 1311367
98-4-16 7. 如申請專利範圍第5項所述之晶片結構，其中該軟 性凸塊之該頂面為圓形。 8. 如申請專利範圍第5項所述之晶片結構，其中該軟 性凸塊之該頂面為環形。 9. 如申請專利範圍第1項所述之晶片結構，其中該軟 性凸塊之該頂面為不規則形狀。 10. 如申請專利範圍第1項所述之晶片結構，其中該些 軟性凸塊排列為陣列。 ® 11.如申請專利範圍第1項所述之晶片結構，其中該軟 性凸塊的材質包括聚亞醯胺。 12. 如申請專利範圍第1項所述之晶片結構，其中該軟 性凸塊的厚度大於等於5微米且小於等於11微米。 13. 如申請專利範圍第1項所述之晶片結構，其中位於 該軟性凸塊之該頂面上的該重配置導電跡線之一端的表面 粗糙度大於〇微米且小於等於1微米。 14. 如申請專利範圍第1項所述之晶片結構，其中該重 φ 配置導電跡線的厚度大於等於2微米且小於等於6微米。 15. 如申請專利範圍第1項所述之晶片結構，其中該保 護層的材質包括聚亞醯胺或苯並環丁烯。 15 1311367 98-4-16 redistribution conductive trace covers part of the side surfaces and at least part of the top surfaces of the compliant bumps. Accordingly, the chip bonding pad of the chip structure may be electrically connected to the corresponding electrical contact of the carrier through the compliant bump and the redistribution conductive trace. 七、指定代表圖： (一） 本案之指定代表圖：圖2A (二） 本代表圖之元件符號簡單說明： 200 晶片結構 210 基材 212 主動面 220 晶片焊墊 230 保護層 240 軟性凸塊 242 頂面 244 侧面 250 重配置導電跡線 八、本案若有化學式時，請揭示最能顯示發明特徵 的化學式： 無
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