TWI398205B - Method for manufacturing printed circuit board - Google Patents

Description

Printed circuit board manufacturing method

The present invention relates to a method of manufacturing a printed circuit board.

With the development of the electronics industry, the demand for high functionality, miniaturization, price competitiveness, and short lead times for electronic components has increased. In response to such a trend, the package substrate manufacturing company applies a semi-additive process (SAP) to reduce the thickness and density of the substrate.

However, according to the semi-additive method, a high-density circuit pattern can be realized. However, when a circuit pattern and a via hole are formed, the number of processes increases, and an additional cost of the manufacturing process occurs. Further, in order to carry out the electroless copper plating on the surface of the substrate and the inside of the processing hole, it takes a lot of cost and time.

In the prior art, a machined hole is formed on a double-sided copper-clad laminate, and then the inner wall of the hole and the surface of the substrate are processed by desmear processing, and then electroless copper plating is performed. Then, electrolytic plating is performed on the electroless copper plating layer to form a circuit pattern and a via hole. That is, in the past, after the processing holes were formed, the inside of the processing holes was plated in order to connect the layers. Due to such a plating process of the inner wall of the machined hole, the plating layer on the surface of the substrate becomes thick, and it is difficult to form a fine circuit.

In order to solve the problems of the prior art, an object of the present invention is to provide a method for manufacturing a printed circuit board, which can produce a substrate that is thinner and higher in density, and can reduce the time and cost of the manufacturing process.

According to an embodiment of the present invention, a method of manufacturing a printed circuit board comprising: a stage of forming a first circuit pattern; a stage of forming a bump on the first circuit pattern; and a first circuit pattern Laminating the insulating material, so that the first circuit pattern is buried in the insulating material, and the step of penetrating the insulating material by the bump; the stage of forming the second circuit pattern on the insulating material; and pressurizing the second circuit pattern to The second circuit pattern is buried in the stage of the insulating material.

Here, the stage of forming bumps on the first circuit pattern can be performed by printing silver ink on the first circuit pattern.

The stage of forming the first circuit pattern may include: providing a stage of a carrier having a metal layer laminated on one side thereof; forming a stage of plating a photoresist on the metal layer; and a stage of forming a conductive substance on the metal layer.

Here, the metal layer laminated on the carrier may be composed of a first metal layer formed on the carrier and a second metal layer formed on the first metal layer.

The first metal layer may comprise copper (Cu) and the second metal layer may comprise nickel (Ni).

The stage of forming the second circuit pattern on the insulating material may include: a stage of forming a conductive layer on the insulating material and the bump; a stage of removing the carrier; a stage of forming an etching photoresist on the conductive layer; and etching the conductive layer and the first The stage of a metal layer.

In the stage of forming the conductive layer on the insulating material and the bump, the pressing process can be performed by pressing the conductive layer against the insulating material to electrically connect the conductive layer and the bump.

In addition, after the stage of forming the second circuit pattern, the stage of removing the second metal layer may be further included.

The stage of removing the second metal layer can be performed by supplying an etching solution and etching the second metal layer.

On the other hand, the stage of forming the second circuit pattern on the insulating material may include: a stage of forming a seed layer on the insulating material and the bump; a stage of removing the carrier; and a stage of forming a plating resist on the seed layer and the metal layer. a stage of forming a conductive substance on the seed layer; a stage of removing the plating resist; and a stage of etching the seed layer and the metal layer.

Here, at the stage of forming the seed layer on the insulating material and the bump, the seed layer can be electrically connected to the bump by pressurizing the seed layer against the insulating material by a pressing process.

Moreover, the stage of forming the first circuit pattern may include: providing a stage of a carrier having a metal layer laminated on one side thereof; a stage of laminating a photosensitive substance on the metal layer; and selectively exposing the photosensitive substance to the display Like, to form the stage of etching the photoresist; and the stage of etching the metal layer.

a stage of forming a second circuit pattern on the insulating material, comprising: a stage of forming a conductive layer on the insulating material and the bump; a stage of removing the carrier; a stage of forming an etching photoresist on the conductive layer and the first circuit pattern; The stage of etching the conductive layer.

Further, at the stage of forming the conductive layer on the insulating material and the bump, the pressing process can be performed by pressing the conductive layer against the insulating material to electrically connect the conductive layer and the bump.

According to the embodiment of the present invention, a fine circuit pattern and a high-density circuit pattern can be obtained, and the cost and time required for the manufacturing process can be reduced, and the insulation reliability between the patterns can be improved.

The present invention is susceptible to various modifications and various embodiments are possible, and in the present invention, specific embodiments are illustrated and described in detail. However, the present invention is not limited to the specific embodiments, but is to be construed as including all modifications, equivalents, and alternatives, which are included in the spirit and scope of the invention. In the description of the present invention, the detailed description of the related art will be omitted, and the detailed description of the present invention will be omitted if the gist of the present invention is not clear.

The terms "first" and "second" are used merely to describe various constituent elements, and the above constituent elements are not limited by the above terms. The above terms are only used to distinguish one component from another.

It is to be understood that the phraseology used in the present invention is intended to be a The performance of a single number includes the performance of plurals as long as it is not clearly expressed in the sentence. In this case, the terms "including" or "having" are used to designate the existence of features, numbers, stages, actions, components, components, or combinations described in the specification, and do not preclude one or The presence or additional possibilities of one or more other features, numbers, stages, actions, components, components, or combinations.

In the following, an embodiment of the printed circuit board and the method of manufacturing the same according to the present invention will be described in detail with reference to the accompanying drawings, and the same reference numerals will be given to the same or corresponding components, and the description will be omitted. Repeat instructions.

1 is a flow chart showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention, and FIGS. 2 to 11 are views showing a process of manufacturing a printed circuit board according to a first embodiment of the present invention. Figure. Referring to FIGS. 2 to 11 , the first circuit pattern 10 , the second circuit pattern 20 , the bumps 30 , the insulating material 40 , the carrier 50 , the metal layer 52 , the first metal layer 54 , and the second metal layer 56 , A plating resist 60, a conductive layer 62, and an etch photoresist 64 are shown.

In the first embodiment of the present invention, in the step S110, as shown in Figs. 2 to 4, the first circuit pattern 10 is formed on the carrier 50.

First, in stage S111, as shown in Fig. 2, a carrier 50 having a metal layer 52 laminated on one side thereof is provided. The carrier serves as a support for forming the first circuit pattern 10. The carrier supports the first circuit pattern so that after the first circuit pattern is formed, the lamination process of the insulating material 40 can be performed. Moreover, in the present embodiment, the first metal layer 54 and the second metal layer 56 are laminated on the carrier. The first metal layer 54 is formed on the carrier, and the second metal layer 56 is formed on the first metal layer by electrolytic plating.

The first metal layer 54 and the second metal layer 56 may be formed of different materials. The first metal layer 54 can be removed by etching the solution when the conductive layer 62 is etched during the formation of the second circuit pattern 20 to be described later. That is, the material forming the first metal layer 54 is a material which can be etched by using the same etching solution as the second circuit pattern 20. In the present embodiment, the first metal layer may contain copper (Cu) in the same manner as the second circuit pattern.

Moreover, the second metal layer 56 in this embodiment functions as a seed layer when the first circuit pattern 10 is formed. Further, in the process of forming the second circuit pattern 20, it functions as a mask for etching the first circuit pattern 10 to be etched by the etching solution. Therefore, the second metal layer 56 is formed of a material different from the second circuit pattern 20 and the first metal layer 54 so as not to be etched by the etching solution of the first metal layer 54, that is, etching copper (Cu). The etching solution is etched. The second metal layer 56 in this embodiment may contain nickel (Ni).

In step S112, a photosensitive material is laminated on the carrier 50, that is, on the second metal layer 56 of the carrier. Then, in step S113, a photosensitive material is selectively exposed by using a photomask or the like to remove a part thereof. That is, as shown in FIG. 3, the plating resist 60 is formed on the second metal layer 56 by lithography. The plating photoresist is formed corresponding to the shape of the first circuit pattern 10 to be formed on the second metal layer 56. That is, the second metal layer corresponding to the portion of the first circuit pattern is not covered by the plating photoresist 60 to expose the outside.

In step S114, a conductive substance is formed on the second metal layer 56. As shown in Fig. 3, electrolytic plating is performed in a state in which the plating resist 60 of the second metal layer 56 is selectively covered. Using an electrolytic plating process, a conductive material can be formed on the second metal layer 56 that is not covered by the plating photoresist.

After the electroconductive plating is performed on the second metal layer 56, the electroplating photoresist 60 is peeled off. As shown in FIG. 4, the first circuit pattern 10 can be formed on the second metal layer 56 by removing the plating photoresist. Copper (Cu) can be used as the conductive material in the present embodiment.

In stage S120, as shown in FIG. 5, bumps 30 are formed on the first circuit pattern 10. The bumps electrically connect the first circuit pattern to the two layers of the second circuit pattern 20 to be described later. The bump which is a function of electrical conduction can be formed of a conductive substance. In the present embodiment, the process of forming the bumps 30 on the first circuit pattern can be performed by printing silver (Silver; Ag) ink on the first circuit pattern 10. Silver ink is printed on a portion of the first circuit pattern that is designed to be electrically conductive between the layers, that is, on the electrode pads on which the bumps 30 are to be formed. As shown in FIG. 5, the conductive bumps 30 can be formed on the first circuit pattern by the silver ink being hardened. In the present embodiment, silver ink is exemplified, but various conductive materials such as solder ink can be used.

In the step S130, as shown in Fig. 6, the insulating material 40 is laminated on the first circuit pattern 10. The first circuit pattern is buried in the insulating material by the insulating material 40 being laminated. The patterns of the first circuit pattern 10 can be filled with the insulating material 40. The insulating material 40 of the present embodiment can be laminated in a semi-hardened state. Therefore, the first circuit pattern can be buried in the insulating material. Further, although the insulating material is laminated, the insulating material is penetrated by the conductive bumps 30. As shown in Fig. 6, the insulating material 40 is penetrated by the bumps 30, and the upper end of the bumps 30 is exposed outside the insulating material.

In the step S140, as shown in Figs. 7 to 9, a second circuit pattern 20 is formed on the insulating material 40. In step S141, as shown in Fig. 7, a conductive layer 62 is laminated on the insulating material and the bumps 30. The conductive layer 62 is formed as a bump that can cover the insulating material and expose the outside of the insulating material. This conductive layer is the metal layer of the second circuit pattern 20. In this embodiment, the conductive layer 62 may be a copper foil layer of copper. The conductive layer can be formed according to a process of laminating the copper foil against the insulating layer 40 at a high temperature and a high pressure. The conductive layer is electrically connected to the conductive bumps during being pressed onto the insulating layer.

The pressing process in this embodiment can be carried out by a pressure of 5 to 30 kgf/cm ² and a temperature of 150 ° C or more. The carrier bonded to the first metal layer can be separated from the first metal layer 54 by a high temperature and high pressure pressing process. That is, in the step S142, after the lamination process of the conductive layer 62, the carrier 50 is removed.

In the step S143, as shown in Fig. 8, an etching resist 64 is formed on the conductive layer 62. The etching photoresist can be formed by performing a lithography process on the photosensitive insulating material. The etch photoresist 64 selectively covers the conductive layer 62.

In the step S144, as shown in FIG. 9, the conductive layer 62 and the first metal layer 54 which are not covered by the etching photoresist 64 are etched. In this embodiment, the conductive layer 62 and the first metal layer 54 are formed of copper (Cu). The conductive layer 62 and the first metal layer 54 can be etched by supplying an etching solution capable of etching a copper (Cu) metal layer. In the etching process, the conductive layer 62 not covered by the etch photoresist 64 may be selectively etched, and the first metal layer 54 may be removed.

Here, the etching solution of the copper (Cu) metal layer can be etched, and the second metal layer 56 made of nickel (Ni) cannot be etched. Even if the first metal layer 54 is removed, the second metal layer 56 is not etched by the etching solution. Therefore, the first circuit pattern 10 utilizes the second metal layer 56 without being etched.

As shown in FIG. 9, after the etching process, the second circuit pattern 20 can be formed on the insulating material 40 by peeling off the etching photoresist 64.

Next, in step S150, as shown in Fig. 10, the second circuit pattern 20 is pressed to cause the second circuit pattern to be buried in the insulating material 40. As shown in Fig. 9, the second circuit pattern is exposed from the insulating material. If the flattening process is performed in a state in which the second circuit pattern is exposed, and the second circuit pattern is buried in the insulating material, the insulation reliability between the patterns can be improved.

Next, in step S160, as shown in Fig. 11, the second metal layer 56 covering the first circuit pattern 10 is removed. The second metal layer 56 formed of a material different from the first metal layer 54 is not etched during the formation of the second circuit pattern 20 to protect the first circuit pattern.

According to the present embodiment, the second metal layer 56 made of nickel (Ni) can be removed by etching the first circuit pattern 10 of the copper (Cu) material and the etching solution of the second circuit pattern 20. As shown in FIG. 11, an etching solution that selectively etches only the second metal layer 56 can be used to remove the second metal layer.

According to the first embodiment of the present invention, the first circuit pattern 10 can be realized by a semi-additive method to realize a high-density shape of 10/10~15/15 μm (line width/line spacing; Line/Space), the second circuit The pattern 20 can be realized by a subtractive method of 20/20 to 25/25 μm (line width/line spacing; Line/Space). For the mounting surface of the electronic component to which the fine circuit pattern must be formed, the fine pattern of the first circuit pattern 10 can be used, and the second circuit pattern 20 can be used for the bonding surface of the bump or the solder ball to be connected to the outside.

According to the first embodiment of the present invention, the circuit pattern can be separately formed by a semi-additive method or a subtractive method corresponding to the portion to which the printed circuit board is to be applied. Therefore, a fine circuit pattern and a high-density circuit pattern can be realized, and the expensive desmear and electroless copper plating time required in the semi-additive method can be reduced. In addition, the process time required in the electrolytic plating process can be reduced.

Further, as shown in Fig. 11, by embedding the insulating material 40 in the first circuit pattern 10 and the second circuit pattern 20, it is possible to provide a printed circuit board which is thinned and has improved insulation reliability.

Hereinafter, a method of manufacturing a printed circuit board according to a second embodiment of the present invention will be described based on FIGS. 12 to 22.

12 is a flow chart showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention, and FIGS. 13 to 22 are views showing a process of manufacturing a printed circuit board according to a second embodiment of the present invention. Figure. Referring to FIGS. 13 to 22, the first circuit pattern 10, the second circuit pattern 20, the bumps 30, the insulating material 40, the carrier 50, the metal layer 52, the plating photoresist 60, the seed layer 70, and the plating light Block 72 is shown.

In the second embodiment of the present invention, in step S210, as shown in Figs. 13 to 15, a first circuit pattern 10 is formed on the carrier 50.

First, in stage S211, as shown in Fig. 13, a carrier 50 having a metal layer 52 laminated on one side thereof is provided. The carrier, as described in the first embodiment, serves as a support for forming the first circuit pattern 10 for supporting the first circuit pattern so that the lamination process of the insulating material 40 can be performed after the first circuit pattern is formed. .

Next, in step S212, a photosensitive material is laminated on the carrier 50, that is, on the metal layer 52 of the carrier. Then, in step S213, a photosensitive material is selectively exposed and developed using a photomask or the like to remove a part thereof. That is, as shown in Fig. 14, a plating resist 60 is formed on the metal layer 52 of the carrier by lithography. The plating resist is formed corresponding to the shape of the first circuit pattern 10 to be formed on the metal layer 52. That is, the portion of the metal layer 52 corresponding to the first circuit pattern is not covered by the plating photoresist 60 to expose the outside.

In step S214, a conductive substance is formed on the metal layer 52. As shown in Fig. 14, electrolytic plating is performed in a state in which the plating resist 60 of the metal layer 52 is selectively covered. With the electrolytic plating process, the conductive material can be formed on the metal layer not covered by the plating photoresist.

After the conductive material is formed on the metal layer 52 by electrolytic plating, the plating resist 60 is peeled off. As shown in Fig. 15, the first circuit pattern 10 can be formed on the metal layer by removing the plating resist. In the conductive material of the present embodiment, it may be formed of copper (Cu).

In stage S220, as shown in Fig. 16, a bump 30 is formed on the first circuit pattern 10. Then, in step S230, as shown in Fig. 17, the insulating material 40 is laminated on the first circuit pattern 10, so that the first circuit pattern is buried in the insulating material 40. Further, the bump 30 penetrates the insulating material and is exposed to the outside. The stage S220 of forming the bumps 30 on the first circuit pattern in the present embodiment and the step S230 of laminating the insulating material on the first circuit pattern can be performed by the same process as the first embodiment of the present invention. The material of the conductive bump 30 and the insulating material may be the same as that of the first embodiment.

Next, in step S240, as shown in Figs. 18 to 21, a second circuit pattern 20 is formed on the insulating material 40. The second circuit pattern in this embodiment can be formed by a semi-additive method.

In step S241, as shown in Fig. 18, a seed layer 70 is formed on the insulating material 40 and the bumps 30. The seed layer is formed to cover the insulating material and expose the outer bumps of the insulating material. In addition, the seed layer is electrically connected to the bump. The seed layer 70 is a base layer to be formed in the second circuit pattern 20 during electrolytic plating. The seed layer 70 in the second embodiment of the present invention is a copper foil layer (about 1 to 3 μm) of a thin plate of a second circuit pattern 20 of a copper (Cu) material according to an electrolytic plating process. The seed layer 70 in this embodiment is formed by a process in which a copper foil layer is pressed against an insulating material at a high temperature and a high pressure as described in the first embodiment.

Further, according to the description of the first embodiment, the carrier 50 bonded to the metal layer 52 can be separated from the metal layer 52 by a high temperature and high pressure pressing process. That is, in stage S242, after the layering process of the seed layer 70, the carrier 50 can be removed.

Then, in step S243, as shown in Fig. 19, a plating resist 72 is formed on the seed layer 70 and the metal layer 52. The plating resist 72 can be formed by performing a lithography process on the photosensitive insulating material. The electroplated photoresist is integrally covered with a metal layer 52 and selectively covers the seed layer.

The plating resist 72 is formed such that the seed layer 70 is opened corresponding to the shape of the second circuit pattern 20. In the step S244, electrolytic plating is performed to form a conductive material on the seed layer 70 which is not covered by the plating photoresist. The conductive material formed on the seed layer is the second circuit pattern 20. Therefore, the conductive material may be copper (Cu).

After the electrolytic plating process, in step S245, as shown in Fig. 20, the plating resist 72 is removed. The plating layer is peeled off, and the seed layer 70 and the metal layer 52 are exposed to the outside.

In step S246, as shown in Fig. 21, the seed layer 70 and the metal layer 52 exposed to the outside are etched. Flash etching is formed on the seed layer 70 between the patterns of the second circuit pattern 20. Also, the metal layer 52 covering the first circuit pattern 10 is etched. According to the second embodiment of the present invention, the etching solution can be supplied to etch the seed layer 70 and the metal layer 52 of the metallic substance. If the seed layer and the metal layer are etched, the first circuit pattern is buried in the insulating material 40, and the second circuit pattern 20 is formed on the insulating material 40.

Next, in step S250, as shown in Fig. 22, the second circuit pattern 20 formed on the insulating material 40 is pressurized, and the second circuit pattern is buried in the insulating material. As shown in Fig. 21, the second circuit pattern is exposed from the insulating material 40. The flattening process is performed in a state in which the second circuit pattern is exposed. By embedding the insulating material in the second circuit pattern, the insulation reliability between the patterns can be improved.

According to the second embodiment of the present invention, the first circuit pattern 10 and the second circuit pattern 20 can be formed by a semi-additive method to form 10/10~15/15μm (line width/line spacing; Line/Space). High-density fine pattern. By forming a fine circuit pattern, it is possible to realize fine pitches which are advantageous for the mounting of electronic components and wire bonding.

Further, as shown in Fig. 22, by embedding the insulating material 40 in the first circuit pattern 10 and the second circuit pattern 20, it is possible to provide a printed circuit board which is thinned and has improved insulation reliability.

Hereinafter, a method of manufacturing a printed circuit board according to a third embodiment of the present invention will be described based on Figs. 23 to 32.

Figure 23 is a flowchart showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention, and Figs. 24 to 32 are diagrams showing a process of manufacturing a printed circuit board according to a third embodiment of the present invention. Figure. Referring to FIGS. 24 to 32, the first circuit pattern 10, the second circuit pattern 20, the bumps 30, the insulating material 40, the carrier 50, the metal layer 52, the etching photoresist 80, the conductive layer 82, and the etching light The resistance 84 series is indicated.

In the third embodiment of the present invention, in the step S310, as shown in Figs. 24 to 26, the first circuit pattern 10 is formed on the carrier.

According to the present embodiment, in the stage S311, as shown in Fig. 24, a carrier 50 having a metal layer 52 laminated on one side thereof is provided. As described in the first embodiment, the carrier supports the first circuit pattern as a support for forming the first circuit pattern 10 so that the lamination process of the insulating material 40 can be performed after the first circuit pattern is formed.

In stage S312, a photosensitive material is laminated on the carrier 50, that is, on the metal layer 52 of the carrier. Then, in step S313, a photosensitive material is selectively exposed and developed using a photomask or the like to remove a part thereof. That is, as shown in Fig. 25, an etch photoresist 80 is formed on the carrier metal layer 52 by lithography, and the etch photoresist 80 covers the metal layer corresponding to the portion of the first circuit pattern 10.

In a third embodiment of the invention, the first circuit pattern 10 is formed by selectively etching the metal layer 52. In the step S314, the etching solution is supplied in a state where the etching photoresist 80 has been formed on the metal layer 52, and the metal layer is selectively etched. The metal layer covered by the etched photoresist 80 is not etched but remains on the carrier 50. Therefore, as shown in Fig. 26, the first circuit pattern 10 is formed on the carrier 50 by removing the etching photoresist 80.

Then, in step S320, as shown in Fig. 27, the conductive bumps 30 are formed on the first circuit pattern 10. Next, in step S330, as shown in Fig. 28, the insulating material 40 is laminated on the first circuit pattern 10, and the first circuit pattern is buried in the insulating material 40. Further, the bump 30 penetrates the insulating material and is exposed to the outside. The stage S320 of forming the bumps 30 on the first circuit pattern and the stage S330 of laminating the insulating material 40 on the first circuit pattern in this embodiment can be performed by the same process as the first embodiment of the present invention. The material of the conductive bumps and the insulating material 40 may be the same as that of the first embodiment.

In step S340, as shown in Figs. 29 to 31, a second circuit pattern 20 is formed on the insulating material 40. In the step S341, as shown in Fig. 29, the conductive layer 82 is laminated on the insulating material and the bumps 30. The conductive layer 82 is formed as a bump that covers the insulating material and exposes the outside of the insulating material. This conductive layer is the metal layer of the second circuit pattern 20. The conductive layer of this embodiment may be a copper foil layer of copper. The conductive layer 82, as explained in the first embodiment of the present invention, can be formed in accordance with a process of laminating a copper foil against an insulating layer at a high temperature and a high pressure. The conductive layer and the bumps can be electrically connected by a pressing process.

The pressing process in the third embodiment of the present invention can be carried out by a pressure of 5 to 30 kgf/cm ² and a temperature of 150 ° C or more. The carrier 50 bonded to the insulating material 40 and the first circuit pattern 10 can be separated from the insulating material and the first circuit pattern 10 by a high temperature and high pressure pressing process. That is, in the step S342, after the lamination process of the conductive layer 82, the carrier 50 is removed.

In step S343, as shown in FIG. 30, an etching photoresist 84 is formed on the conductive layer 82 and the first circuit pattern 10. According to the description of the first embodiment, the etching photoresist 84 can be formed by performing a lithography process on the photosensitive insulating material laminated on the conductive layer 82. Further, the first circuit pattern 10 and the insulating material 40 are covered by the etching photoresist 84. On the other hand, the etch photoresist 84 partially covers the conductive layer 82. That is, the etch photoresist 84 covers only a portion of the conductive layer 82 corresponding to the second first pass pattern 20.

In step S344, as shown in Fig. 30, an etching solution is supplied in a state in which the etching photoresist 84 is formed, and the conductive layer 82 is selectively etched. The first circuit pattern 10, the insulating material 40, and a portion of the conductive layer 82 covered by the etched photoresist 84 are not etched. As shown in FIG. 31, after the etching process, if the etching photoresist 84 is removed, the second circuit pattern 20 is formed on the insulating material 40.

Then, in step S350, as shown in Fig. 32, the second circuit pattern 20 is pressurized so that the second circuit pattern is buried in the insulating material 40. As shown in Fig. 31, the second circuit pattern is exposed on the insulating material, and the flattening process is performed in a state where the second circuit pattern is exposed. By embedding the insulating material in the second circuit pattern, the insulation reliability between the patterns can be improved.

According to the third embodiment of the present invention, by forming the first circuit pattern 10 and the second circuit pattern 20 by the subtraction method, the expensive desmear and electroless copper plating required in the semi-additive method can be reduced. Time. In addition, the processing time required in the electrolytic plating process can also be reduced.

The first circuit pattern 10 in the third embodiment of the present invention is formed by an etching process. Therefore, in the etching process characteristics, the width of the upper portion of the pattern which is exposed to the outside is formed to be larger than the width of the lower portion of the pattern buried in the insulating material 40. That is, the profile of the circuit pattern becomes trapezoidal by side etching. By the width of the upper portion of the first circuit pattern 10 being formed wider, the bonding area of the wire bonding can be wider when the wires are bonded. Therefore, the reliability of wire bonding can be improved.

Further, as shown in Fig. 32, by embedding the insulating material 40 in the first circuit pattern 10 and the second circuit pattern 20, it is possible to provide a printed circuit board which is thinned and has improved insulation reliability.

The invention has been described with reference to the preferred embodiments of the present invention, but it is understood that the scope of the invention and the scope of the invention described in the claims The present invention has been variously modified and changed.

10. . . First circuit pattern

20. . . Second circuit pattern

30. . . Bump

40. . . Insulating material

50. . . Carrier

52. . . Metal layer

54. . . First metal layer

56. . . Second metal layer

60. . . Electroplated photoresist

62. . . Conductive layer

64. . . Etching photoresist

70. . . Seed layer

72. . . Electroplated photoresist

80. . . Etching photoresist

82. . . Conductive layer

84. . . Etching photoresist

Fig. 1 is a flow chart showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention.

Fig. 2 is a process diagram showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention.

Fig. 3 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 4 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 5 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 6 is a process view showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 7 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 8 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 9 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Fig. 10 is a process diagram showing a method of manufacturing a printed circuit board according to the first embodiment of the present invention.

Figure 11 is a process diagram showing a method of manufacturing a printed circuit board according to a first embodiment of the present invention.

Fig. 12 is a flow chart showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 13 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 14 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Fig. 15 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 16 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 17 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 18 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 19 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 20 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 21 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 22 is a process diagram showing a method of manufacturing a printed circuit board according to a second embodiment of the present invention.

Figure 23 is a flow chart showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 24 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 25 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 26 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 27 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 28 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 29 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 30 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 31 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Figure 32 is a process diagram showing a method of manufacturing a printed circuit board according to a third embodiment of the present invention.

Claims (7)

A manufacturing method of a printed circuit board includes: a stage of forming a first circuit pattern; a stage of forming a bump on the first circuit pattern; and laminating the insulating material on the first circuit pattern to make the first circuit pattern a stage of being embedded in the insulating material and penetrating the insulating material by the bump; forming a second circuit pattern on the insulating material; and pressing the second circuit pattern to make the second circuit pattern a stage of being embedded in the insulating material; wherein the step of forming the first circuit pattern comprises: providing a stage on which a metal layer is laminated; forming a plating resist on the metal layer; and a stage of forming a conductive material on the metal layer; wherein the metal layer comprises: a first metal layer formed on the carrier; and a second metal layer formed on the first metal layer, the second metal The layer is formed of a material etched by an etching solution different from the first metal layer; wherein the second circuit pattern is formed on the insulating material Section line comprises: forming a conductive layer phase on the insulating material and said bumps, the conductive layer of the etched lines of the first metal layer by a same etching solution a material forming stage; a stage of removing the carrier; a stage of forming an etching photoresist on the conductive layer; and a step of simultaneously etching the conductive layer and the first metal layer; wherein, after the step of pressing the second circuit pattern, A stage including the removal of the second metal layer described above is included. The method of manufacturing a printed circuit board according to the first aspect of the invention, wherein the step of forming a bump on the first circuit pattern is performed by printing silver ink on the first circuit pattern. The method of manufacturing a printed circuit board according to claim 1, wherein the first metal layer comprises copper (Cu). The method of manufacturing a printed circuit board according to claim 1, wherein the second metal layer contains nickel (Ni). The method of manufacturing a printed circuit board according to the first aspect of the invention, wherein the step of forming a conductive layer on the insulating material and the bump is performed by pressing the conductive layer to the insulating layer by a pressing process. The conductive layer is electrically connected to the bump. A method of manufacturing a printed circuit board includes: forming a first circuit pattern; a step of forming a bump on the first circuit pattern; stacking the insulating material on the first circuit pattern, so that the first circuit pattern is buried in the insulating material, and the insulating material is penetrated by the bump a stage of forming a second circuit pattern on the insulating material; and pressurizing the second circuit pattern to cause the second circuit pattern to be buried in the insulating material; wherein the first circuit pattern is formed, The invention comprises: a stage of providing a carrier having a metal layer laminated on one side; a stage of forming an etching photoresist on the metal layer; and a stage of forming a conductive substance on the metal layer; wherein the second layer is formed on the insulating material The stage of the circuit pattern includes: a stage of forming a seed layer on the insulating material and the bump; a stage of removing the carrier; a stage of forming a plating resist on the seed layer and the metal layer; and the seed layer a stage of forming a conductive substance; a stage of removing the plating resist; and a step of etching the seed layer and the metal layer. The method of manufacturing a printed circuit board according to claim 6, wherein the seed layer is formed on the insulating material and the bump, and the seed layer is pressurized to the insulating layer by a pressing process. material The seed layer is electrically connected to the bump.