TWI385495B - Negative voltage generating circuit - Google Patents

Description

Negative voltage generating circuit

The present invention relates to a negative voltage generating circuit.

With the rapid development of modern electronic technology and high-speed ultra-large integrated circuits, more and more electronic systems require positive and negative voltages to work properly. For example, operational amplifiers and computer PCI (Peripheral Component Interconnect) cards require negative voltage. For normal operation, the -12V power supply is commonly used on the motherboard as the power supply voltage for the PCI device and the operating voltage of the printed chip. The circuit design has a growing demand for a negative voltage power supply with a large output current, but a negative voltage circuit capable of providing practicality, simple circuit, and low cost is rare.

In view of the above, it is necessary to provide a negative voltage generating circuit which is simple in circuit and low in cost, and can provide a negative voltage required for operation of an electronic device.

A negative voltage generating circuit includes a digital analog conversion display driving chip, a switching element, a resistor, a first capacitor, a first diode, a second diode, and a second capacitor, the digital analogy The conversion display driving chip includes a positive voltage input pin, an oscillating output pin and a negative voltage input pin, the switching element includes a first end, a second end and a third end, the positive voltage input pin is connected to a power source, The oscillating output pin is connected to the first end of the switching element, the second end of the switching element is connected to one end of the first capacitor, and the power is connected through the resistor, the third end of the switching element is grounded, and the first capacitor is another One end is respectively connected to the anode of the first diode and the cathode of the second diode, the cathode of the first diode is grounded, and the anode of the second diode is connected to the negative voltage input of the digital analog display driving chip a pin, and grounded through the second capacitor, the oscillating output pin outputs a high-low level oscillating pulse signal to control the switching element to be turned off or on, so that the first capacitor is charged or discharged, when the first electric When the discharge is performed, the first capacitor is supplied to the negative analog input of the digital analog display driving chip and a negative voltage is charged, and the second capacitor is charged. When the first capacitor is charged, the second capacitor is the digital analog conversion display. The negative voltage input pin of the driver chip provides a negative voltage.

Compared with the prior art, the negative voltage generating circuit controls the switching of the switching element through the digital analog display display driving chip, thereby charging the first capacitor and outputting a negative voltage through the discharging of the first capacitor, and the circuit is simple. The cost is lower.

Referring to FIG. 1, a preferred embodiment of the negative voltage generating circuit of the present invention includes a digital analog conversion display driving chip U1, a display unit U2, resistors R1, R2, a field effect transistor Q1, capacitors C1, C2, C3, and C4. And diodes D1, D2.

The digital analog conversion display driving chip U1 includes a positive voltage input pin v+, a first oscillation output pin osc1, a second oscillation output pin osc2, a third oscillation output pin osc3, a negative voltage input pin v-, and a plurality of data. Output pins p1-p16. The positive voltage input pin v+ is connected to a power source vcc, and the second oscillation output pin osc2 is connected to the first oscillation output pin osc1 through a resistor R1. The third oscillation output pin osc3 is connected to the first oscillation output pin osc1 through a capacitor C1. The equal data output pins p1-p16 are electrically connected to the display unit U2 through the complex transmission line. The third oscillation output pin osc3 is also connected to the gate of the field effect transistor Q1. The source of the field effect transistor Q1 is connected to one end of the capacitor C2, and is connected to the power source Vcc through the resistor R2. The field effect transistor Q1 The bungee is grounded. The other end of the capacitor C2 is connected to the anode of the diode D1 and the cathode of the diode D2. The cathode of the diode D1 is grounded, and the anode of the diode D2 is connected to the negative voltage input of the digital analog display driving wafer U1. The foot v- is grounded through the capacitors C3 and C4 respectively.

The resistor R1 and the capacitor C1 constitute an oscillating circuit, and a pulse signal having an oscillating frequency of 0.45/R1C1 is generated at the third oscillating output pin osc3 of the digital analog conversion display driving chip U1. The capacitor C2 is used for charging and discharging, the capacitor C3 is used for high frequency filtering, the capacitor C4 is used for low frequency filtering, and the capacitor C3, C4 is the negative voltage input pin of the digital analog conversion display driving chip U1 during the charging of the capacitor C2. Provides a negative voltage input. The diode D1 is a Schottky diode for providing a low impedance loop for charging the capacitor C2, and the diode D2 provides a load circuit for discharging the capacitor C2. The field effect transistor Q1 is a P-channel MOS type field effect transistor, and the digital analog conversion display driving chip U1 is an ICL7107 type chip provided by Interx Corporation of the United States, and the display unit U2 is composed of a plurality of light emitting diodes. Digital display panel.

During operation, the digital analog output display driver chip U1 of the third oscillation output pin osc3 outputs a pulse signal that alternates between high and low levels. When the signal from the third oscillation output pin osc3 is high, the field effect power The crystal Q1 is turned off, and the power source Vcc charges the capacitor C2. When the capacitor C2 is fully charged, there is almost no current on the resistor R2. The diode D1 is a Schottky diode, and there is a voltage drop (such as 0.2V), so the voltage value across the capacitor C2 is the power source. The difference between the input voltage value of Vcc and the voltage drop across diode D1.

When the signal sent by the third oscillation output pin osc3 is low level, the field effect transistor Q1 is turned on, the source is extremely low, and the source of the field effect transistor Q1 is connected to the end of the capacitor C2, that is, the capacitor C2. One terminal voltage connected to the field effect transistor Q1 is 0V. Since the capacitor has a characteristic that the voltage cannot be abruptly changed, when the voltage at one end of the capacitor C2 connected to the field effect transistor Q1 is 0V, the voltage at the other end is a negative value. Therefore, the capacitor C2 is discharged through the capacitors C3, C4 and the diode D2, so that the negative voltage input pin v- receives a negative voltage.

When the analog output of the third analog output pin osc3 of the driving analog chip U1 is continuously high and low, the capacitor C2 is constantly in a charging and discharging state, and when the signal sent by the third oscillation output pin osc3 is low level, The capacitor C2 is discharged through the capacitors C3, C4 and the diode D2, and supplies a negative voltage to the negative voltage input pin v-. Since the capacitors C3 and C4 are connected in parallel with the diode D1, when the capacitor C2 is discharged, the negative voltage input pin v- is input to the negative voltage and the capacitors C3 and C4 are charged, when the third oscillation output pin osc3 is issued. When the signal is high, the capacitor C2 cannot supply a negative voltage input to the negative voltage input pin v-, but the third capacitor C3 and the fourth capacitor C4 have been charged during the last low level, and the capacitors C3, C4 at this time. A negative voltage input is provided to the negative voltage input pin v-, thereby ensuring the continuity and stability of the negative voltage input pin v-input negative voltage.

If the input voltage of the power supply Vcc is 5V, when the signal sent by the third oscillation output pin osc3 is high level, the capacitor C2 becomes 5V after charging, when the signal sent by the third oscillation output pin osc3 is low level. The capacitor C2 is connected to the field effect transistor Q1 at a voltage of 0V, and the other terminal voltage is -5V. The capacitor C2 is discharged through the capacitors C3, C4 and the diode D2, so that the negative voltage input pin v- is received. The voltage is a negative value, and the voltage value is a negative value (such as -4.8V) of the difference between the input voltage value of the power source Vcc and the voltage drop of the diode D2, because the voltage drop on the diode D2 is small, Therefore, the absolute value of the input voltage of the negative voltage input pin v- is approximately equal to the input voltage value of the power supply Vcc. The display unit U2 is configured to display a negative voltage value received by the negative voltage input pin v- of the digital analog conversion display driving chip U1, and the digital analog conversion display driving chip U1 can receive its negative voltage input pin v- The negative voltage is subjected to analog-to-digital conversion, and then the digital display panel composed of a plurality of light-emitting diodes electrically connected to the plurality of data output pins p1-p16 displays the magnitude of the negative voltage.

The negative voltage generating circuit can also connect different numbers of diodes between the cathode of the diode D1 and the ground. Since there is a voltage drop on the diode, the negative voltage input pin v- is connected according to the second The difference in the number of poles receives a different negative voltage value. The negative voltage generating circuit of the invention has the advantages of simple structure, strong practicability and low cost.

In summary, the present invention complies with the requirements of the invention patent and submits a patent application according to law. However, the above-mentioned embodiments are only the specific embodiments of the present invention, and equivalent modifications or variations made by those skilled in the art will be included in the following claims.

Digital analog conversion display driver chip. . . U1

Display unit. . . U2

resistance. . . R1, R2

capacitance. . . C1~C4

Diode. . . D1, D2

Field effect transistor. . . Q1

1 is a circuit diagram of a preferred embodiment of a negative voltage generating circuit of the present invention.

Digital analog conversion display driver chip. . . U1

Display unit. . . U2

resistance. . . R1, R2

capacitance. . . C1~C4

Diode. . . D1, D2

Field effect transistor. . . Q1

Claims (7)

A negative voltage generating circuit includes a digital analog conversion display driving chip, a switching element, a resistor, a first capacitor, a first diode, a second diode, and a second capacitor, the digital analogy The conversion display driving chip includes a positive voltage input pin, an oscillating output pin and a negative voltage input pin, the switching element includes a first end, a second end and a third end, the positive voltage input pin is connected to a power source, The oscillating output pin is connected to the first end of the switching element, the second end of the switching element is connected to one end of the first capacitor, and the power is connected through the resistor, the third end of the switching element is grounded, and the first capacitor is another One end is respectively connected to the anode of the first diode and the cathode of the second diode, the cathode of the first diode is grounded, and the anode of the second diode is connected to the negative voltage input of the digital analog display driving chip a pin, and grounded through the second capacitor, the oscillating output pin outputs a high-low level oscillating pulse signal to control the switching element to be turned off or on, so that the first capacitor is charged or discharged, when the first electric When the discharge is performed, the first capacitor is supplied to the negative analog input of the digital analog display driving chip and a negative voltage is charged, and the second capacitor is charged. When the first capacitor is charged, the second capacitor is the digital analog conversion display. The negative voltage input pin of the driver chip provides a negative voltage. The negative voltage generating circuit of claim 1, wherein the digital analog display driving chip further comprises a plurality of data output pins, wherein the data analog output of the digital analog display driving chip is electrically connected to a display panel, the display The panel is configured to display a negative voltage value received by the negative voltage input pin of the digital analog display driver chip. The negative voltage generating circuit of claim 1, further comprising a third capacitor, wherein the anode of the second diode is further grounded through the third capacitor. The negative voltage generating circuit of claim 1, wherein the switching element is a P-channel MOS type field effect transistor, and the first end, the second end and the third end are respectively the field effect transistor Gate, source and bungee. The negative voltage generating circuit of claim 1, wherein the first diode is a Schottky diode. The negative voltage generating circuit of claim 1, further comprising a third diode connected in series between the cathode of the first diode and the ground. The negative voltage generating circuit of claim 2, wherein the display panel is a digital display panel composed of a plurality of light emitting diodes.