1246735 A7 B7 五、發明說明（1 ) 技術領域 本發明係關於半導體積體電路及其之測試技術以及製 造技術，特別是關於在內藏測試電路之半導體積體電路中 ，使與外部之控制裝置之間之測試資料之交換容易化之技 術，例如，關於適用在系統L S I (大型積體電路）等之 半導體積體電路及其檢查方法以及製造方法有效之技術。 背景技術 習知上一般搭載R A Μ (隨機存取記憶體）或C P U 等之被稱爲系統L S I之邏輯L S I之測試容易化設計手 法，以將構成內部邏輯之正反器串列接續，輸入測試資料 ，使內部邏輯電路動作，使之串列輸出邏輯之狀態以進行 檢查之掃描路徑方式被經常使用。 又，在上述掃描路徑方式以外，有將隨機圖案產生器 與特徵壓縮器當成測試電路搭載於晶片之Β I S Τ (內建 自我測試）方式。 可是在前述掃描測試方式中，爲了掃描路徑之控制， 最少也需要4個之測試用端子。又，於ΒIST方式中， 在啓動晶片內部之測試電路，使測試結果輸出上也需要數 個之測試用端子。而且，於任何一種之測試方式中，被稱 爲測試機之裝置被接續於上述測試用端子，以實行測試。 習知上，搭載如上述之測試電路之邏輯L S I之測試 係在晶圓階段，於半導體晶片之銲墊（p a d )使接觸探 針而進行之探針檢查之外，半導體晶片在被密封於封裝之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） I (請先閱讀背面之注意事項再填寫本頁) tT--------- 經濟部智慧財產局員工消費合作社印製 -4 - 1246735 A7 B7 五、發明說明（2 ) 階段，於被設置在測試用基板上之插座插入1 C而進行之 老化（burn-in )試驗之2階段被進行。又’於老化試驗中 ，一般在被設置於測試用基板上之複數之插座分別裝置 L S I ，同時測試複數之L S I。 但是，如前述般地，於各晶片最少也需要設置數個之 測試用端子，必須連接這些之測試用端子與外部之測試裝 置，在晶圓階段之探針檢查中，如欲同時測試多數之晶片 ，需要使巨大數目之探針接觸於晶片之對應銲墊之故，該 位置對正極爲困難之同時，以充分之壓力使個別之探針接 觸也變得困難。又，於藉由測試用基板之檢查中，被密封 在封裝之裝置與晶片相比，體積變得極爲大之故，構裝密 度降低之同時，測試用端子之數目一變多，應形成在基板 上之配線的數目變多之故，一次可以測試之L S I之數目 有限度，導致測試成本之上升。 本發明之目的在於提供：不於各晶片設置測試用之端 子（銲墊或銷），使晶片內部之測試電路動作，可以取得 其測試結果之半導體積體電路及其之測試方法以及製造方 法。 本發明之其它目的在於提供：減少測試之際需要接續 之端子（銲墊或銷）之數目，可以大幅增加同時可以測試 之晶片之數目之半導體積體電路及其測試方法以及製造方 法。 本發明之進而其它之目的在於提供：即使爲晶圓之狀 態、在被密封於封裝之狀態，可以同樣進行測試之半導體 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） i (請先閱讀背面之注意事項再填寫本頁) 訂---------#f. 經濟部智慧財產局員工消費合作社印製 1246735 經濟部智慧財產局員工消費合作社印製 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 B7_ 五、發明說明（3 ) 積體電路及其測試方法以及製造方法。 本發明之前述以及其它目的與新的特徵由本詳細說明 書之記述以及所附圖面理應可以變明白。 發明之揭示 如簡單說明本案所揭示之發明之中之代表性者之槪要 ，則如下述。 即，於內藏測試電路之半導體積體電路設置：在與外 部之控制裝置之間以非接觸方式進行資料之傳送接收之電 路與傳送接收手段者。具體爲：在半導體積體電路之晶片 上透過絕緣膜例如形成渦卷狀之導電層圖案，將其之一端 接續於測試電路之輸入輸出端子之同時，於測試電路之輸 入輸出部設置：將上述導電層圖案當成感應線圈或天線驅 動，傳送信號之傳送電路，以及檢測流經上述導電層圖案 之電流或電壓之變化，鑑別由外部對於感應線圈或天線被 傳送之信號之接收電路，在與外部之控制裝置之間，以非 接觸方式進行資料之傳送接收。又，代替感應線圈或天線 ，設置對向電極利用靜電電容耦合以傳送接收，設置發光 元件與受光元件以光信號進行資料之傳送接收亦可。 如依據上述手段，不須於各晶片設置測試用之端子（ 銲墊或銷），使晶片內部之測試電路動作，可以取得該測 試結果之故，可以減少在晶圓階段之測試之際應接觸之由 測試裝置來之探針數。又，晶片與探針之定位變得容易之 同時，不需要大的接觸壓力之故，變成可以同時進行更多 (請先閱讀背面之注音？事項再填寫本頁)1246735 A7 B7 V. INSTRUCTION DESCRIPTION (1) TECHNICAL FIELD The present invention relates to a semiconductor integrated circuit and its testing technology and manufacturing technology, and more particularly to a semiconductor integrated circuit in a built-in test circuit, and an external control device A technique for facilitating the exchange of test data between them, for example, a technique applicable to a semiconductor integrated circuit such as a system LSI (large integrated circuit), an inspection method thereof, and a manufacturing method. BACKGROUND ART Conventionally, a test simplification design method of a logic LSI called a system LSI such as an RA Μ (random access memory) or a CPU is generally used to connect a flip-flop that constitutes an internal logic, and input test The data is used to make the internal logic circuit operate so that the state of the output logic is serialized for inspection. Further, in addition to the above-described scanning path method, there is a method in which a random pattern generator and a characteristic compressor are mounted on a wafer as a test circuit (built-in self-test). However, in the aforementioned scan test mode, at least four test terminals are required for the control of the scan path. Moreover, in the ΒIST method, several test terminals are required to start the test circuit inside the wafer, so that the test result output. Moreover, in any of the test methods, a device called a test machine is connected to the above test terminals to carry out the test. Conventionally, the test of the logic LSI equipped with the test circuit described above is in the wafer stage, and the semiconductor wafer is sealed in the package in addition to the probe inspection of the contact pad of the semiconductor wafer. The paper size applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) I (please read the notes on the back and fill out this page) tT--------- Ministry of Economic Affairs Intellectual Property Office employees Consumer Cooperatives Print - 4 - 1246735 A7 B7 V. Inventive Note (2) The stage is carried out in two stages of the burn-in test performed by inserting 1 C into the socket on the test substrate. Further, in the aging test, the plurality of sockets which are disposed on the test substrate are generally equipped with L S I , and the complex L S I is simultaneously tested. However, as mentioned above, a minimum of several test terminals are required for each wafer, and these test terminals and external test devices must be connected. In the probe inspection at the wafer stage, if you want to test most of them at the same time, For wafers, it is necessary to have a large number of probes in contact with the corresponding pads of the wafer. This position is difficult for the positive electrode, and it is difficult to contact individual probes with sufficient pressure. Moreover, in the inspection of the test substrate, the device sealed in the package has a much larger volume than the wafer, and the mounting density is lowered, and the number of terminals for testing is increased. As the number of wirings on the substrate increases, the number of LSIs that can be tested at one time is limited, resulting in an increase in test cost. SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit, a test method and a manufacturing method thereof, in which a test terminal (pad or pin) is not provided for each wafer, and a test circuit inside the wafer is operated to obtain a test result. Another object of the present invention is to provide a semiconductor integrated circuit, a test method, and a manufacturing method which can reduce the number of terminals (pads or pins) that need to be connected at the time of testing, and which can greatly increase the number of wafers that can be simultaneously tested. Still another object of the present invention is to provide a semiconductor paper size that can be similarly tested, even in the state of a wafer, in a state of being sealed in a package, in accordance with the Chinese National Standard (CNS) A4 specification (210 X 297 mm). i (Please read the note on the back and fill out this page) Order---------#f. Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Print 1246735 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Print this paper The scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) A7 B7_ V. Invention Description (3) Integrated circuit and its test method and manufacturing method. The foregoing and other objects and features of the present invention will become apparent from Disclosure of the Invention As a brief description of the representative of the invention disclosed in the present invention, it is as follows. Namely, the semiconductor integrated circuit of the built-in test circuit is provided with a circuit for transmitting and receiving data and a transmitting and receiving means in a non-contact manner with an external control device. Specifically, the conductive film is formed on the wafer of the semiconductor integrated circuit by, for example, forming a spiral-shaped conductive layer pattern, and one end thereof is connected to the input/output terminal of the test circuit, and is disposed at the input/output portion of the test circuit: The conductive layer pattern is driven by an induction coil or an antenna, transmits a signal transmission circuit, and detects a change in current or voltage flowing through the conductive layer pattern to identify a receiving circuit that is externally transmitted to the induction coil or the antenna, and externally The data is transmitted and received in a non-contact manner between the control devices. Further, instead of the induction coil or the antenna, the counter electrode is provided by electrostatic capacitance coupling for transmission and reception, and the light-emitting element and the light-receiving element are provided to transmit and receive data by optical signals. According to the above means, it is not necessary to provide test terminals (pads or pins) on each wafer, so that the test circuit inside the chip can be operated, and the test result can be obtained, and the contact at the wafer stage can be reduced. The number of probes from the test device. Moreover, the positioning of the wafer and the probe becomes easy, and it is possible to carry out more at the same time without requiring a large contact pressure (please read the phonetic transcription on the back side and then fill out this page)
W 1246735 A7 B7 五、發明說明（4 ) (請先閱讀背面之注咅？事項再填寫本頁) 數之晶片之測試，能夠大幅降低測試成本。進而，可以以 非接觸方式進行晶片之測試之故，即使在晶圓之狀態、在 被密封於封裝之狀態，可以同樣地進行測試，能夠提升產 品之信賴性。 實施發明用之最好形態 以下，依據圖面說明本發明之合適之實施例。 圖1 ( A )係顯示本發明之第1實施例。於圖1 ( A )中，W F係單晶矽之類的1片之半導體晶圓、1 〇 〇係 分別被形成在此晶圓WF上之半導體積體電路。各半導體 積體電路1 0 0爲藉由周知之半導體製造技術複數個同時 被形成在晶圓W F上，在製程之最終工程，沿著被設置在 電路間之格子狀之切割區域被切斷，被作成個個獨立之晶 片，被密封在封裝、以樹脂被模鑄，成爲產品被出貨。以 下，將被切斷前之半導體積體電路與被切斷被密封在封裝 前之半導體積體電路稱爲晶片。 經濟部智慧財產局員工消費合作社印製 如圖1 ( A )所示般地，於本實施例中，於每一晶片 形成作爲後述之感應線圈被使用之渦卷狀之圖案1 1。此 渦卷狀圖案1 1係藉由透過絕緣膜被形成在各晶片上之旅 等之導電層所構成。渦卷狀圖案1 1之端部被接續於被設 置在晶片上之後述之傳送接收電路。又，在此實施例中， 透過被設置在各晶片之電源銲墊2 1進行電源之供給。 圖1 ( B )係顯示本發明之第2實施例。於此實施例 中，在晶圓W F之周緣部設置接受測試用之電源電壓之供 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） A7 1246735 _B7 五、發明說明（5 ) 給用之共通之電源銲墊2 2。雖然未圖示出，由此電源銲 墊2 2對各晶片供給電源之電源線例如被設置在晶圓之各 晶片1 0 0間之切斷區域，此電源線之一端被接續上述共 通電源銲墊2 2，又另一端被接續於各晶片之電源銲墊。 此電源銲墊2 2以及電源線也可以藉由構成上述渦卷狀圖 案11之導電層而形成。W 1246735 A7 B7 V. INSTRUCTIONS (4) (Please read the note on the back side and then fill out this page) The test of the number of wafers can significantly reduce the cost of testing. Further, since the wafer can be tested in a non-contact manner, the test can be performed in the same manner even in the state of the wafer and sealed in the package, and the reliability of the product can be improved. BEST MODE FOR CARRYING OUT THE INVENTION Hereinafter, a suitable embodiment of the present invention will be described with reference to the drawings. Fig. 1 (A) shows a first embodiment of the present invention. In Fig. 1(A), a semiconductor wafer such as a W F-based single crystal germanium or a semiconductor wafer is formed on the wafer WF by a semiconductor wafer. Each of the semiconductor integrated circuits 100 is formed on the wafer WF by a plurality of well-known semiconductor fabrication techniques, and is cut along a lattice-shaped cutting region provided between the circuits in the final process of the process. It is made into a separate wafer, sealed in a package, molded with a resin, and shipped as a product. Hereinafter, the semiconductor integrated circuit before being cut and the semiconductor integrated circuit which is sealed before being sealed are referred to as wafers. In the present embodiment, a wrap-like pattern 1 1 used as an induction coil to be described later is formed in each of the wafers as shown in Fig. 1 (A). The spiral pattern 11 is composed of a conductive layer formed on the respective wafers through an insulating film. The end portion of the spiral pattern 1 1 is connected to a transfer receiving circuit which will be described later on the wafer. Further, in this embodiment, the power supply is performed through the power supply pads 2 1 provided on the respective wafers. Fig. 1 (B) shows a second embodiment of the present invention. In this embodiment, the power supply voltage for testing is set at the peripheral portion of the wafer WF. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). A7 1246735 _B7 5. Invention Description (5 ) A common power pad 2 2 is used. Although not shown, the power supply line for supplying power to each of the wafers by the power pad 2 2 is disposed, for example, in a cut-off area between the wafers of the wafers, and one end of the power line is connected to the common power supply. Pad 2 2, the other end is connected to the power pads of each wafer. The power pad 2 2 and the power supply line can also be formed by the conductive layer constituting the scroll pattern 11.
圖1 ( C )係顯示本發明之第3實施例。於圖1 ( A )之實施例中，相對於對應晶圓W F上之各晶片1 0 0， 分別形成成爲感應線圈之渦卷狀圖案1 1 ，於圖1 ( C ) 之實施例中，全晶片共通，即在晶圓全體形成1個之渦卷 狀圖案1 1。而且，各晶片之傳送接收電路之端子透過被 形成在切斷區域之配線，分別共通被接續於此渦卷狀圖案 1 1。又，在晶圓W F之周緣部設置接受測試用之電源電 壓之供給用之各晶片共通之電源銲墊2 2。又，感應線圈 不單信號之傳送接收，也可以利用於電力之供給之故，於 各晶片設置由整流電路形成之電源電路，也可以省略測試 用之共通電源銲墊2 2。 圖2係顯示檢查上述晶圓W F上之各晶片之裝置之槪 略構成例。其中在圖2顯示對應圖1 ( A )之實施例之測 試裝置之構成例，又，於圖3顯示對應圖1 ( C )之實施 例之測試裝置之構成例。 圖2中，3 0 0係控制裝置、3 1 0係由此控制裝置 3 0 0被延伸設置之纜線、3 2 0係被設置在纜線3 1 0 之前端之探針卡，在此探針卡3 2 0，電源電壓供給用之 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） Γ^Τ --------^---------. (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1246735 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（6 ) 一對之探針3 2 1被搭載於其之下面，又，線圈3 2 2被 搭載於卡中央。 在圖2之測試裝置中，被設置在探針卡3 2 0之線圈 3 2 2之直徑被設爲與被設置在晶片1 〇 〇之線圈（1 1 )幾乎相同之直徑。晶圓WF被載置於分別可以在正交之 X軸與Y軸方向移動之XY工作台4 0 〇上，由上方將探 針卡3 0 0接近其一之晶片1 0 0，使一對之探針3 2 1 接觸晶片之電源銲墊（2 1 )。此時，線圏3 2 2之中心 與被設置於欲測試之晶片之渦卷狀圖案（1 1 )之中心一 致地進行定位。1個晶片之測試一終了，工作台4 0 〇只 跳過1個之晶片份，於下一晶片之線圈（1 1 )使探針卡 3 2 0之線圈3 2 2與其相面對之同時，探針3 2 1也被 接觸於下一晶片之電源銲墊（2 1 )。 在圖3之測試裝置中’被設置在探針卡3 2 0之線圈 3 2 2之直徑與被設置在晶圓W F之線圈1 2幾乎爲相同 之直徑。載置晶圓WF之工作台4 0 0也可以爲固定式者 。被設置在探針卡3 2 0之探針3 2 1被設置爲可以與晶 圓WF上之共通電源銲墊2 2接觸。 對應圖1 ( B )之實施例之測試裝置雖然未圖示出， 爲具有並有圖2之裝置之構成與圖3之裝置之構成的構造 。即，探針卡被設置2片，與圖2之裝置相同地，與晶片 1 0 0上之線圏1 1幾乎爲相同之直徑之線圈3 2 2被設 置在一方之卡，工作台4 0 0與探針卡3 2 0被設爲可以 相對地移動。與晶圓W F上之各晶片共通之電源銲墊2 2 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -9 - --------訂·------11 (請先閱讀背面之注意事項再填寫本頁) 1246735 A7 B7 五、發明說明（7 ) (請先閱讀背面之注咅？事項再填寫本頁) 可以接觸之一對之探針3 2 1被設置在另一方之卡，對於 工作台4 0 0不可以相對地移動，即，與工作台一齊移動 ，經常對晶圓供給電源地構成。 圖4係顯示藉由圖2所示之測試裝置所進行之測試之 順序。在測試之際，一使被接續於控制裝置3 0 0之探針 卡3 2 0之探針3 2 1與各晶片之電源銲墊2 1或晶圓 W F上之共通電源銲墊2 2接觸，對各晶片供給電源電壓 ，晶片內部之測試電路被啓動，開始自我測試（步驟S 1 )。而且，各晶片一測試終了，透過線圈1 1或1 2輸出 測試終了信號後（步驟S 2 )，輸出顯示測試結果（“有 “或“無“缺陷）之信號（步驟S 3 )。進而，藉由圖3 之測試裝置進行測試之情形，預先在各晶片內儲存辨識碼 ，各晶片與測試結果一齊地輸出晶片之辨識碼。 控制裝置3 0 0 —接收測試終了信號，將接著被送來 之測試結果每一晶片地記憶在記憶體。而且，在顯示裝置 之畫面上，例如如圖5所示般地，將各晶片之測試結果以 〇或X之標號，對應晶圓上之晶片位置，測繪顯示之，藉 由列表機印刷在紙張上進行輸出地構成。 經濟部智慧財產局員工消費合作社印製 圖6係顯示合適適用本發明之半導體積體電路之一例 之系統L S I之第1實施例。 圖6中，標號1 1 0〜1 8 0係被形成在半導體晶片 1〇0之內部電路、1 9 0係進行這些之內部電路與外部 之其它的半導體積體電路等之間之信號的輸入輸出之介面 電路、B U S係接續上述內部電路1 1 0〜1 8 0相互間 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 經濟部智慧財產局員工消費合作社印製 J246735 A7 ______B7 五、發明說明（8 ) 以及內部電路1 1 0〜1 8 0與介面電路1 9 0之間之內 部總線。 上述內部電路110〜180之中，110以及 1 2 0係構成使用者要求之邏輯機能之使用者邏輯電路之 類的定做邏輯電路，其中1 2 0爲藉由可以任意地構成邏 輯之F P G A (場可程式閘陣列）所構成。在此實施例中 ，於此F P G A 1 2構成測試電路，測試終了後，構成使 用者邏輯。但是，此F P GA 1 2不構成使用者邏輯，原 樣殘留也沒有關係。1 2 0爲解讀程式之命令，實行對應 之處理貨運算之CPU (中央處理單元），130以及 1 4 0係靜態R A Μ (隨機存取記憶體）、1 5 0〜 1 7 0係動態R A Μ。介面電路1 9 0雖無特別限制，係 包含：進行與5 V系統之L S I之間之信號之傳送接收之 介面電路5VI/F，以及進行與3 · 3V系統之LS I 之間之信號之傳送接收之介面電路3 · 3 V I / F。進而 ，在此實施例之系統L S I設置：在內部電路1 1 〇〜 1 8 0之測試時，爲了進行與外部之測試裝置之間之信號 之輸入輸出，於以I Ε Ε Ε 1 1 4 9 · 1規格所規定之 丁 A Ρ (測試存取埠）追加使透過線圈之傳送接收成爲可 能之電路之測試用介面電路（以下，稱此爲T A P ) 2 〇 〇。具備此種T A P 2 0 0之故’被接續於本實施例 之半導體積體電路之測試裝置（圖2之控制裝置3 0 0 ) 並非如習知之邏輯L S I或記憶體之測試機之高機能者， 可以爲能夠進行資料之寫入與讀出以及簡單之資料處理者 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -11 - (請先閱讀背面之注意事項再填寫本頁)Fig. 1 (C) shows a third embodiment of the present invention. In the embodiment of FIG. 1(A), a spiral pattern 1 1 as an induction coil is formed with respect to each of the wafers 100 on the corresponding wafer WF. In the embodiment of FIG. 1(C), The wafers are common, that is, one spiral pattern 11 is formed on the entire wafer. Further, the terminals of the transfer/reception circuits of the respective wafers are transmitted through the wiring formed in the cut-off region, and are connected to the spiral pattern 1 1 in common. Further, a power pad 2 2 common to each of the wafers for supplying the power supply voltage for testing is provided on the peripheral portion of the wafer WF. Further, the induction coil may not be transmitted or received by a single signal, and may be used for supplying power, and a power supply circuit formed of a rectifier circuit may be provided for each wafer, and the common power supply pad 2 2 for testing may be omitted. Fig. 2 is a schematic view showing a schematic configuration of an apparatus for inspecting each wafer on the wafer WF. Fig. 2 shows a configuration example of a test apparatus corresponding to the embodiment of Fig. 1(A), and Fig. 3 shows a configuration example of a test apparatus corresponding to the embodiment of Fig. 1(C). In Fig. 2, the 3000 control device, the 310 system is a cable that is extended by the control device 300, and the microphone is a probe card that is disposed at the front end of the cable 3 1 0, where Probe card 3 2 0, the paper size for power supply voltage is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) Γ^Τ --------^------- --. (Please read the note on the back and fill out this page.) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 1246735 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed 5, Invention Description (6) A pair of exploration The needle 3 2 1 is mounted on the lower side thereof, and the coil 3 22 is mounted on the center of the card. In the test apparatus of Fig. 2, the diameter of the coil 3 2 2 provided on the probe card 320 is set to be almost the same diameter as the coil (1 1 ) provided on the wafer 1 。 . The wafer WF is placed on the XY table 40 分别 which can be moved in the orthogonal X-axis and Y-axis directions, respectively, and the probe card 300 is brought close to the wafer 1 0 0 from the top to make a pair The probe 3 2 1 contacts the power pad (2 1 ) of the wafer. At this time, the center of the coil 3 2 2 is positioned in unison with the center of the spiral pattern (1 1 ) provided on the wafer to be tested. After the test of one wafer is finished, the workbench 40 跳过 skips only one wafer share, and the coil of the next chip (1 1 ) makes the coil of the probe card 3 2 0 face it at the same time. The probe 3 2 1 is also contacted with the power pad (2 1 ) of the next wafer. In the test apparatus of Fig. 3, the diameter of the coil 3 2 2 disposed at the probe card 306 is almost the same as the diameter of the coil 12 provided at the wafer WF. The table 40 on which the wafer WF is placed may also be a fixed type. The probe 3 2 1 disposed on the probe card 320 is placed in contact with the common power pad 2 2 on the crystal WF. The test apparatus corresponding to the embodiment of Fig. 1(B), although not shown, has a configuration having the configuration of the apparatus of Fig. 2 and the apparatus of Fig. 3. That is, the probe card is provided in two pieces, and similarly to the device of Fig. 2, the coil 3 2 2 having the same diameter as the wire 圏 1 1 on the wafer 100 is placed on one of the cards, and the table 40 0 and the probe card 3 2 0 are set to be relatively movable. Power pad common to all wafers on wafer WF 2 2 This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) -9 - -------- order ·--- ---11 (Please read the note on the back and fill out this page) 1246735 A7 B7 V. INSTRUCTIONS (7) (Please read the note on the back first and then fill out this page) You can touch one of the probes The 3 2 1 card is placed on the other side, and it is not possible to move relative to the table 400, that is, to move together with the table, and to constantly supply power to the wafer. Figure 4 is a diagram showing the sequence of tests performed by the test apparatus shown in Figure 2. At the time of testing, the probe 3 2 1 of the probe card 3 2 0 connected to the control device 300 is brought into contact with the power pad 2 1 of each wafer or the common power pad 2 2 on the wafer WF. The power supply voltage is supplied to each of the wafers, and the test circuit inside the wafer is activated to start self-test (step S1). Further, after the end of each test of the wafer, after the end of the test signal is output through the coil 11 or 12 (step S2), a signal indicating that the test result ("there is " or "no defect") is output (step S3). Further, in the case of testing by the test apparatus of FIG. 3, the identification code is stored in advance in each wafer, and each wafer outputs the identification code of the wafer together with the test result. The control device 300 - receives the test end signal, and the test result that is subsequently sent is memorized in the memory for each wafer. Moreover, on the screen of the display device, for example, as shown in FIG. 5, the test results of the respective wafers are marked with 〇 or X, corresponding to the position of the wafer on the wafer, and the display is displayed on the paper by the list machine. The output is constructed. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, Employees' Cooperatives, Fig. 6 shows a first embodiment of a system L S I which is an example of a semiconductor integrated circuit to which the present invention is applied. In Fig. 6, reference numerals 1 1 0 to 1 8 0 are input signals formed between the internal circuits of the semiconductor wafer 1〇0, and the internal circuits of the above-mentioned internal circuits and other semiconductor integrated circuits, and the like. Output interface circuit, BUS system connection The above internal circuit 1 1 0~1 8 0 The paper scale applies to China National Standard (CNS) A4 specification (210 X 297 mm) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperative Printed J246735 A7 ______B7 V. Description of the invention (8) and the internal bus between the internal circuits 1 10 0 to 1 0 0 and the interface circuit 1 90. Among the internal circuits 110 to 180, 110 and 120 are custom logic circuits constituting a user logic circuit of a logic function required by a user, wherein 120 is an FPGA capable of arbitrarily constructing logic (field) The programmable gate array is composed of. In this embodiment, the F P G A 1 2 constitutes a test circuit which, after the end of the test, constitutes the user logic. However, this F P GA 1 2 does not constitute user logic, and it does not matter as it is. 1 2 0 is the command to interpret the program, the corresponding processing CPU (central processing unit), 130 and 1 0 0 static RA Μ (random access memory), 1 5 0~ 1 7 0 dynamic RA Hey. The interface circuit 190 is not particularly limited, and includes: a interface circuit 5VI/F for performing signal transmission and reception with an LSI of a 5 V system, and a signal transmission between LS I and a 3·3V system. Receive interface circuit 3 · 3 VI / F. Further, in the system LSI of this embodiment, in the test of the internal circuit 1 1 〇 ～ 1 0 0, in order to perform input and output of signals with an external test device, I Ε Ε Ε 1 1 4 9 • A test interface circuit (hereinafter referred to as TAP) that is a circuit that enables transmission and reception through a coil is added to the D-A (test access port) specified in the specification. The test device (the control device 300 of FIG. 2) connected to the semiconductor integrated circuit of the present embodiment is not a high-performance function of a conventional logic LSI or a memory tester. It can be used for writing and reading of data and simple data processing. The paper is applicable to China National Standard (CNS) A4 specification (210 X 297 mm) -11 - (Please read the notes on the back and fill in the form) This page)
經濟部智慧財產局員工消費合作社印製 1246735 A7 __B7___ 五、發明說明（9 ) ，例如，也可以將個人電腦當成控制裝置3 0 0使用。 而且，在此實施例之L S I中，被設置於每一晶片之 渦卷狀之導電層圖案1 1之一端被接續於T A P 2 0 0之 輸入輸出端子之同時，在TAP 2 0 0設置：將上述導電 層圖案1 1當成線圈驅動而傳送信號之傳送電路以及檢測 流經上述導電層圖案之電流等之變化，鑑別由外部對於線 圈被傳送來之信號之接收電路，以非接觸方式在與外部之 測試裝置之間可以進行資料之傳送接收地構成。 上述靜態R Α Μ 1 4 0、1 5 0以及動態R A Μ 1 6 0〜1 8 0係包含：選擇對應透過內部總線B U S， 位址信號被給予時之記憶體單元之位置解碼器等之記憶體 周邊電路。進而，動態R Α Μ 1 6 0〜1 8 0包含：即使 非存取時間非常長，記憶體單元之資訊電荷也不會損失地 ，週期地進行虛擬選擇之更新控制電路。 又，雖無特別限制，但是在此實施例中，在動態 R Α Μ 1 6 0〜1 8 0中分別設置：在記憶體陣列內有缺 陷位元之情形，將包含該缺陷位元之記憶體行或記憶體列 與預備之記憶體行1 6 1〜1 8 1或預備之記憶體列 1 6 2〜1 8 2置換之所謂之冗餘電路。 於此實施例中，藉由利用F P G A 1 2 0 ’可以構成 測試定做邏輯電路1 1 〇或C P U 1 3 0之邏輯測試電路 ，或測試S R A Μ以及D R A Μ之記憶體測試電路。又’ 代替藉由F P G A 1 2 0構成測試電路，構成由：以構成 於F P G A 1 2 0之測試電路測試C P U 1 3 0後，依循 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -Ί2- ------I I ^--------一 (請先閱讀背面之注意事項再填寫本頁) 1246735 A7 B7 五、發明說明（1〇 ) 指定之算術在C P U 1 3 0產生測試形態之A L P G (算 術形態產生器）所形成之測試電路，以測試定做邏輯電路 (請先閱讀背面之注音？事項再填寫本頁) 110 或 RAM140 〜180。 進而，代替藉由FPGA1 20或CPU1 3 0構成 測試電路，也可以於定做邏輯電路1 1 〇或C P U 1 3 0 、SRAM140、150、DRAM160 〜180 等 之每一電路方塊設置以方塊單位進行測試之B I S T電路 ，接續此B I ST電路與TAP200，透過TAP 2 0 0在B I S T電路與外部之測試裝置之間進行信號之 交換地構成。又，也可以涵蓋晶片全體或每一電路方塊設 置測試用掃描路徑，利用上述T A P 2 0 0所具有之掃描 路徑之控制機能以進行測試。 經濟部智慧財產局員工消費合作社印製 又，構築產生利用被形成在晶片上之F P G A依循指 定之算術，測試邏輯電路或記憶體之測試形態之A L P G 以進行測試之技術已經由本專利申請人例如公開於國際公 開W〇〇 〇 / 6 2 3 3 9等，可以利用該技術。上述前一 發明係以：測試終了後，在F P G A構成使用者邏輯電路 以減低伴隨測試電路搭載之硬體之總開銷爲目的之發明， 於本實施例之L S I中，也同樣地在測試終了後，藉由在 F P G A構成使用者邏輯電路，可以降低硬體之總開銷。 圖7係顯示圖6所示之T A P 2 0 0之構成例。 T A P係以I E E E 1 1 4 9 · 1規格而被規定之掃描測 試或B I S T電路用之介面以及控制電路，在此實施例中 ，係藉由：由IEEE 1149 · 1規格被規定之本來之 -13- 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1246735 A7 B7 五、發明說明（11 ) 請 先 閱 讀 背 面 之 注 意 事 項 TAP形成之TAP部2 1 0，以及被設置於TAP部 2 1 0與由渦卷狀圖案形成之線圈被接續之一對之端子 P 1、P 2之間，驅動線圈，進行與外部裝置之間之傳送 接收之傳送接收部2 2 0所構成。 其中，T A P部2 1 0係藉由：使用於將由輸入基板 來之測試資料移往輸出基板時之旁路寄存器2 1 1、使用 於對電路傳送特定之信號之情形之資料寄存器2 1 2 '設 定晶片固有之製造辨識號碼用之裝置I D寄存器2 1 3、 使用於控制資料寄存器之選擇或內部之測試方法之情形的 指示寄存器2 1 4、控制TAP部2 1 0全體之控制器 2 1 5等所構成。 上述資料寄存器2 1 2係選擇處理之寄存器。又，在 被設定於指示寄存器214之命令係準備有4個必須命令 與3個選擇命令。在控制器215由專用之3個外部端子 輸入：指定測試模式用之測試模式選擇信號T M S、測試 時脈T C Κ、重置信號T R S Τ，依據這些信號，形成對 於上述寄存器2 1 1〜2 1 4或選擇器電路2 1 6〜 2 1 8之控制信號。 經濟部智慧財產局員工消費合作社印製 又，在T A Ρ部2 1 0設置測試資料T D I之輸入端 子與測試結果資料T D ◦之輸出端子，被輸入之測試資料 TD I透過上述選擇器電路2 1 6被供給於各寄存器 2 1 1〜2 1 4或內部之掃描路徑Isc an、Bsc an。又，由 寄存器211〜214之內容以及內部電路來之掃描輸出 資料透過選擇器電路2 1 7、2 1 8被輸出於晶片外部。 -14- 本紙張尺度適用中國國家標準（CNS)A4規袼（210 X 297公釐） 1246735 A7 B7 五、發明說明（12 ) 進而，依循資料寄存器2 1 2與指示寄存器2 1 4之內容 ，對於內部之B 1 s T電路之信號被形成而被供給於 丁 A P部2 1 0之同時，顯示由B I S T電路被輸出之測 試結果之信號透過選擇器電路2 1 7、2 1 8當成測g式結 果資料T D 0可以輸出地構成。 傳送接收部2 2 0係被設置在上述T A P部2 1 0與 渦卷狀圖案1 1被接續之外部端子P 1、P 2之間’驅動 由渦卷狀圖案1 1形成之線圈’傳送信號之同時’檢測流 經線圈之電流之變化’鑑別由外部被傳送來之信號’產生 因應TAP之規格之信號TD I、TRST、TMS以及 時脈T C K之電路。 具體爲：傳送接收部2 2 0係由：透過由一對之電感 器形成之互相感應耦合Μ I C被接續於渦卷狀圖案1 1被 接續之外部端子Ρ 1、Ρ 2之開關電路2 2 1、由接收信 號解調載波與資料之解調電路2 2 2、使源振盪器2 3 1 之振盪信號與藉由源振盪器2 3 1與解調電路2 2 2被解 調之載波同步之引入電路2 3 2、由倍增源振盪器2 3 1 之振盪信號之頻率之倍增電路2 3 3等形成之時脈產生電 路2 2 3、解碼由解調電路2 2 2被解調之輸入資料’產 生測試輸入資料T D I或對於T A Ρ控制器2 1 5之測試 模式選擇信號T M S以及重置信號T R S T與掃描用時脈 B C L Κ之解碼器電路2 2 4、該晶片之辨識碼被儲存著 之R0M2 2 5、在由TAP部2 1 0來之測試結果資料 T D〇附加辨識碼之編碼器電路2 2 6、將在編碼器電路 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 1246735 A7 __B7___ V. Invention description (9), for example, the personal computer can also be used as the control device 300. Further, in the LSI of this embodiment, one end of the spiral-shaped conductive layer pattern 11 provided on each wafer is connected to the input and output terminals of the TAP 200, and is set at the TAP 200: The conductive layer pattern 11 is a transmission circuit for transmitting a signal by a coil and detecting a change in a current flowing through the conductive layer pattern, and the like, and a receiving circuit for identifying a signal transmitted from the external coil, in a non-contact manner with the outside The test devices can be configured to transmit and receive data. The static R Α Μ 1 4 0, 1 50 and the dynamic RA Μ 1 6 0~1 8 0 include: selecting a memory corresponding to the position decoder of the memory unit when the address signal is given through the internal bus BUS. Body peripheral circuit. Further, the dynamic R Α Μ 1 6 0 to 1 8 0 includes an update control circuit that periodically performs virtual selection even if the non-access time is extremely long and the information charge of the memory cell is not lost. Further, although not particularly limited, in this embodiment, in the case of dynamic R Α Μ 1 60 0 to 1 0 0, respectively, a case where a defective bit exists in the memory array, and a memory containing the defective bit is set The so-called redundant circuit of the body row or memory column and the prepared memory row 1 6 1~1 8 1 or the prepared memory column 1 6 2~1 8 2 . In this embodiment, the logic test circuit for testing the custom logic circuit 1 1 〇 or C P U 1 3 0 can be constructed by using F P G A 1 2 0 ', or the memory test circuit of S R A Μ and D R A 测试 can be tested. In addition, instead of constructing the test circuit by FPGA 1 2 0, it consists of: After testing the CPU 1 3 0 of the test circuit formed on the FPGA 1 20, the Chinese National Standard (CNS) A4 specification (210 X 297) is applied according to the paper scale. )) -Ί2- ------II ^--------1 (please read the notes on the back and fill out this page) 1246735 A7 B7 V. Invention Description (1〇) Designated Arithmetic A test circuit formed by the ALPG (arithmetic shape generator) of the test pattern is generated in the CPU 130 to test the custom logic circuit (please read the phonetic note on the back side and then fill in the page) 110 or RAM 140 to 180. Further, instead of constructing the test circuit by the FPGA 1 20 or the CPU 1 30, it is also possible to set the test in block units for each of the circuit blocks of the custom logic circuit 1 1 or the CPU 1 3 0 , the SRAM 140, 150, the DRAMs 160 to 180, and the like. The BIST circuit, which is connected to the TAP 200, is formed by exchanging signals between the BIST circuit and an external test device through the TAP 200. Further, the test scan path may be set to cover the entire wafer or each circuit block, and the control function of the scan path of the above T A P 2000 may be used for the test. The Ministry of Economic Affairs, the Intellectual Property Office, the employee consumption cooperative, and the construction of the technology that utilizes the ALPG that is formed on the wafer to follow the specified arithmetic, test the logic circuit or the test mode of the memory for testing, has been disclosed by the applicant. This technology can be utilized in international publications W〇〇〇/ 6 2 3 3 9 and the like. The above-mentioned first invention is an invention for the purpose of reducing the total cost of the hardware included in the test circuit after the end of the test, and in the LSI of the present embodiment, similarly after the end of the test. By constructing user logic circuits in the FPGA, the total cost of the hardware can be reduced. Fig. 7 is a view showing an example of the configuration of T A P 2 0 0 shown in Fig. 6. TAP is a interface for scanning test or BIST circuit and control circuit specified in the IEEE 1 1 4 9 · 1 specification. In this embodiment, it is specified by the IEEE 1149 · 1 specification. - This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1246735 A7 B7 V. Invention description (11) Please read the TAP part of the TAP section 2 1 0, and be set to The TAP unit 211 forms a transmission/reception unit 2 2 0 between the terminals P 1 and P 2 which are connected to the coil formed by the spiral pattern, and drives the coil to perform transmission and reception with the external device. . The TAP unit 2 1 0 is used by the bypass register 2 1 1 for transferring the test data from the input substrate to the output substrate, and the data register 2 1 2 ' for the case of transmitting a specific signal to the circuit. The device ID register 2 1 3 for setting the manufacturing identification number inherent to the wafer, the indication register for the case of the selection of the control data register or the internal test method, and the controller 2 1 5 for controlling the TAP unit 2 1 0 And so on. The above data register 2 1 2 is a register for selecting processing. Further, four command commands and three selection commands are prepared in the command set in the instruction register 214. The controller 215 is input by three dedicated external terminals: a test mode selection signal TMS for specifying a test mode, a test clock TC Κ, and a reset signal TRS Τ, according to these signals, for the above-mentioned registers 2 1 1 to 2 1 4 or the control circuit of the selector circuit 2 1 6~ 2 1 8 . The Ministry of Economic Affairs, the Intellectual Property Bureau, the employee consumption cooperative, and the input terminal of the test data TDI and the output terminal of the test result data TD 2 are set in the TA Ρ 2 2, and the input test data TD I passes through the selector circuit 2 1 6 is supplied to each of the registers 2 1 1 to 2 1 4 or the internal scan paths Isc an and Bsc an. Further, the scan output data from the contents of the registers 211 to 214 and the internal circuits are output to the outside of the wafer through the selector circuits 2 1 7 and 2 1 8 . -14- This paper scale applies to China National Standard (CNS) A4 (210 X 297 mm) 1246735 A7 B7 V. Invention Description (12) Further, according to the contents of the data register 2 1 2 and the indication register 2 1 4, While the signal of the internal B 1 s T circuit is formed and supplied to the D AP portion 2 1 0, the signal indicating the test result outputted by the BIST circuit is transmitted through the selector circuit 2 1 7 and 2 1 8 as the measurement g. The result data TD 0 can be constructed as an output. The transmission/reception unit 2 20 is disposed between the TAP unit 2 1 0 and the external terminals P 1 and P 2 to which the spiral pattern 1 1 is connected, and drives a coil formed by the spiral pattern 1 1 to transmit a signal. At the same time 'detecting the change in current flowing through the coil' to identify the signal transmitted from the outside' generates a signal TD I, TRST, TMS and clock TCK in response to the specifications of the TAP. Specifically, the transmitting and receiving unit 2 2 0 is: a switching circuit 2 that is connected to the external terminal Ρ 1 and Ρ 2 by which the mutual inductive coupling Μ IC formed by the pair of inductors is connected to the spiral pattern 1 1 1. Demodulation circuit for demodulating carrier and data by received signal 2 2 2. Synchronizing the oscillating signal of source oscillator 2 3 1 with the carrier demodulated by source oscillator 213 and demodulation circuit 2 2 2 The introduction circuit 2 3 2, the clock generation circuit 2 2 3 formed by the multiplication circuit 2 3 3 of the oscillation signal of the multiplication source oscillator 2 3 1 , and the input demodulated by the demodulation circuit 2 2 2 The data 'generating test input data TDI or the test mode selection signal TMS for the TA Ρ controller 2 1 5 and the reset signal TRST and the decoding clock circuit BCL 解码 the decoder circuit 2 2 4, the identification code of the chip is stored R0M2 2 5, the encoder circuit 2 2 6 in the test result data TD 由 from the TAP part 2 1 0, will apply the Chinese National Standard (CNS) A4 specification (210 X) on the paper scale of the encoder circuit. 297 mm) (Please read the notes on the back and fill out this page) Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperative, printing
-15- 1246735 A7 B7 五、發明說明（13 ) 2 2 6所被產生之碼載於載波輸出之調製電路2 2 7等所 構成。 藉由時脈產生電路2 2 3所被產生之源振盪信號之倍 增時脈對T A P控制器2 1 5作爲測試用時脈T C K被供 給之同時，源振盪信號作爲載波被供給於調製電路2 2 6 。上述調製電路2 3 0之調製方式例如可以使用A S K調 製（振幅調製）或P S K調製（相位調製）等。 在圖6之實施例之系統L S I中，將被構築於 FPGA 1 2 0或CPU 1 3 0上之自我測試電路視爲 B I ST電路，利用上述TAP200之所具有之 B I S T電路用之信號輸入輸出機能，輸入對於F P G A 1 2 0或C P U 1 3 0之自我測試用之設定信號或資料、 輸出測試結果。 又，圖7中，“ Iscan”係將鏈狀結合構成內部邏輯電路 之正反器之移位寄存器當成測試資料之掃描路徑使用，意 指進行內部邏輯電路之診斷用之測試路徑。又，“ Bscaii” 係將鏈狀結合被設置於信號輸入輸出部（圖6之介面電路 1 9 0 )內之正反器之移位寄存器當成掃描路徑使用，意 指進行與其它之半導體積體電路之間之接續狀態之診斷（ 邊界掃描測試）用之測試路徑。 關於利用I E E E 1 1 4 9 · 1規格所規定之T A P 之半導體積體電路，藉由將對內部電路之測試電路的構成 或對晶片內之測試程式之載入透過T A P進行，可以實現 測試用所必要之端子以數個（4〜5個）便可之半導體積 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） (請先閱讀背面之注音？事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製-15- 1246735 A7 B7 V. INSTRUCTION DESCRIPTION (13) 2 2 6 The generated code is composed of a modulation circuit 2 2 7 of the carrier output. The multiplication clock of the source oscillation signal generated by the clock generation circuit 2 2 3 is supplied to the TAP controller 2 1 5 as the test clock TCK, and the source oscillation signal is supplied as a carrier to the modulation circuit 2 2 . 6 . The modulation method of the above-described modulation circuit 220 can be, for example, A S K modulation (amplitude modulation) or P S K modulation (phase modulation). In the system LSI of the embodiment of FIG. 6, the self-test circuit constructed on the FPGA 120 or the CPU 130 is regarded as a BI ST circuit, and the signal input/output function for the BIST circuit of the TAP 200 is utilized. Enter the setting signal or data for self-test of FPGA 1 2 0 or CPU 1 3 0, and output the test result. Further, in Fig. 7, "Iscan" uses a shift register which is chain-connected to form a flip-flop of an internal logic circuit as a scan path of test data, and means a test path for performing diagnosis of an internal logic circuit. Further, "Bscaii" uses a shift register of a flip-flop that is disposed in a signal input/output portion (interface circuit 1 90 in FIG. 6) as a scan path, meaning that it is integrated with other semiconductors. The test path used for the diagnosis of the connection state between circuits (Boundary Scan Test). With regard to the semiconductor integrated circuit using the TAP specified in the IEEE 1 1 4.9 specification, the test device can be realized by the configuration of the test circuit for the internal circuit or the loading of the test program in the wafer through the TAP. The necessary terminals are available in several (4~5) semiconductor products. The paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm). (Please read the phonetic on the back? Please fill out this page again) Ministry of Economic Affairs, Intellectual Property Bureau, employee consumption cooperative, printing
-16- A7 1246735 B7___ 五、發明說明（14 ) 體電路裝置。即，T A P係被標準化之電路，以4〜5個 之測試端子可以實行自我測試之故，藉由適用T A P，測 試用所必要之端子數可以少’能夠減少L S I之端子數。 進而，於利用此實施例之T A P之介面電路2 〇 〇中，在 內部設置時脈產生電路2 2 3之同時，藉由設置解碼接收 資料產生控制信號之解碼器電路2 2 4，可以使完全之串 列輸入輸出成爲可能，必要之端子指示作爲線圈之渦卷狀 圖案11被接續之P1、P2。 於圖8顯示被設置於上述T A P 2 0 0之傳送接收電 路2 2 0之其它之實施例。 圖8中，2 2 8係由整流由被接續於線圈（渦卷狀圖 案1 1 )之兩端子間之線圈（1 1 )被輸入之交流信號， 產生直流電源電壓之二極體電橋所形成之整流電路， 2 2 9係監視由上述整流電路2 2 8被輸出之電壓，檢測 信號被輸入線圈（1 1 )以產生啓動信號S T之啓動電路 ，2 4 1係被接續於線圏（1 1 )之兩端子間，波形整型 輸入交流信號而輸出之資料接收電路，2 4 2係由依據藉 由調製電路2 2 7被調製之信號，開、關驅動汲極端子透 過電容器C t 1、C t 2被接續於線圈（1 1 )之各端子 之一對的驅動用MOSFET Qdl、Qd2，藉將由電容器C t 1 、C t 2與線圈（1 1 )形成之共振電路切換爲共振狀態 以及非共振狀態，傳送資料之驅動電路等形成之資料傳送 電路。 又，上述電容器C t 1、C t 2可以形成在晶片內， 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------^--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1246735 A7 B7___ 五、發明說明（15 ) (請先閱讀背面之注音？事項再填寫本頁) 但是在爲了抑制晶片尺寸之增加，也可以形成在各晶片間 之切斷區域。又，於前述實施例中，雖係作成由晶片之電 源銲墊2 1或於晶圓設置電源銲墊2 2由該電源銲墊給予 測試用之電源電壓，但是在圖8之實施例中，也可以在整 流電路2 2 8之下一段設置由：吸收藉由整流電路被整流 之電壓的變動，產生指定之電位之電源電壓V c c之電壓 限制器電路以及使以該限制器電路所產生之電源電壓 V c c安定化之串聯穩壓器等形成之電源安定化電路，藉 由將由此電源安定化電路被輸出之電源電壓供給該晶片內 部之各電路，不透過電源銲墊對各晶片給予測試動作用之 電源電壓而構成。 圖9係顯示重疊快閃記憶體或S R A Μ之類的不同的 半導體記憶體以作成C S Ρ (晶片尺寸封裝）構造之半導 體裝置之情形的本發明之實施例之裝置構造。 經濟部智慧財產局員工消費合作社印製 圖9中，5 0 0係形成印刷電路之絕緣基板，5 1 0 係被形成在基板5 0 0之下面之凸點（bump )，5 2 0係 被搭載於絕緣基板5 0 0之上面之快閃記憶體之類的第1 記憶體，5 3 0係被搭載於此記憶體5 2 0之上之 S R A Μ之類的第2記憶體。快閃記憶體5 2 0與絕緣基 板5 0 0之間以及S R A Μ 5 3 0與快閃記憶體5 2 0之 間分別藉由黏著劑等被結合。雖然未圖示出，但是在快閃 記憶體5 2 0與S R A Μ 5 3 0之晶片內部分別設置測試 電路與傳送接收電路。 S R A Μ 5 3 0被設爲比快閃記憶體5 2 0還小之晶 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1246735 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（16 ) 片尺寸，在於快閃記憶體5 2 0之上搭載S R A Μ 5 3 〇 之狀態下，於比S R A Μ 5 3 0還突出外側之快閃記憶體 5 2 0之晶片外延部形成快閃記憶體之銲墊列5 2 1、 5 2 2，此銲墊列5 2 1、5 2 2與絕緣基板5 0 0上之 對應銲墊部之間以及被形成在s R A Μ 5 3 0之晶片外延 部之銲墊列5 3 1、5 3 2與絕緣基板5 0 0上之對應銲 墊部之間分別藉由銲線5 4 1〜5 4 4被電氣地接續著。 於此實施例中，由導電層形成之渦卷狀圖案1 1被形 成在記憶體晶片下方之絕緣基板5 0 0表面或基板內’接 續用配線1 1 a、1 1 b分別由此渦卷狀圖案1 1之兩端 被引出，在被設置於這些配線1 1 a、1 1 b之端部之銲 墊55 1、552與被設置於上述各晶片520、530 之傳送接收電路之輸入輸出端子（圖7之端子P 1、P 2 )之間也以銲線被接續著。 因此，基板上之渦卷狀圖案1 1被設爲上述快閃記憶 體晶片5 2 0與S R A Μ晶片5 3 0之共通線圈，透過此 線圈進行對於各晶片之測試用之信號之輸入輸出。如此， 即使透過共通線圏而進行信號之輸入輸出，於各晶片儲存 不同之辨識碼，在傳送接收之際，辨識碼與測試結果一齊 地被傳送之故，外部之測試裝置可以辨識到底爲哪一個晶 片之測試結果。 接著，利用圖1 0說明半導體積體電路裝置之一例之 圖6的系統L S I之開發以及製造之順序。 半導體積體電路裝置之開發首先進行要開發之半導體 —--------訂--------- C請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -19- 1246735 經濟部智慧財產局員工消費合作社印製 Α7 Β7 五、發明說明（17 ) 積體電路之邏輯機能之設計（步驟S 1 1 )。此邏輯機能 設計一般係利用H D L而進行。又，關於H D L記述，由 狀態遷移圖或流程圖自動地製作H D L記述文之支援工具 (程式）由E D Α供應商所提供之故，在利用其之狀況下 ，可以有效率地進行。又，被H D L記述之設計資料藉由 產生被稱爲測試向量之測試形態之驗證用程式，進行驗證 動作是否適當之假想測試。在藉由假想測試發現不良之情 形，修正H D L記述文。 接著，依據在步驟S 1 1設計之資料，進行邏輯閘等 級之電路設計（步驟S 1 2 )。具體爲：設計構成具有所 期望之機能之電路之邏輯閘或正反器之類的單元（cell ) 。而且，依據此設計資料，進行邏輯合成，製作以淨淸單 之形式記述各邏輯閘以及單元間之接續資訊之設計資料（ 步驟s 1 3 )。又，如閘陣列般地，在已經進行邏輯閘之 電路設計之L S I上構成所期望之邏輯機能之情形，可以 省略步驟S 1 2之電路設計。又，此處也藉由E D A供應 商提供將被H D L記述之設計資料轉換爲邏輯閘等級之設 計資料，合成其之被稱爲邏輯合成工具之程式之故，可以 利用其進行。又，被產生之邏輯閘等級之設計資料再度藉 由測試向量（假想測試機）被驗證。在藉由假想測試機發 現不良之情形，修正邏輯閘等級之設計資料。 接著，依據以淨淸單形式被記述之上述邏輯閘等級之 設計資料，藉由被稱爲自動佈置工具之程式產生元件等級 之佈置資料（步驟S 1 4 )。此種自動佈置工具也由複數 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -20- --------訂---------· (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 1246735 A7 B7 五、發明說明（18 ) 之E D A供應商提供。之後，決定在晶圓上之晶片之佈置 (步驟S 1 5 )。此時，也決定被形成在各晶片上之線圈 之渦卷狀圖案之佈置以及接續線圈與晶片內之傳送接收電 路之配線之佈置。而且’依據被決定之佈置資料’藉由原 圖（a r t w 〇 r k )產生光罩圖案資料，依據此資料， 製作光罩（步驟S 1 6 )。 之後，藉由前工程在半導體晶圓上進行擴散處理或配 線圖案之形成等之處理，形成半導體積體電路（步驟 S 1 7 )。此後，於測試裝置設置晶圓’使探針卡相面對 ，開始測試（步驟S 1 8 )。在此實施例中，於此晶圓測 試係使用圖2所示之測試裝置。此時’使探針卡之探針接 觸於晶圓上之各晶片之電源銲墊之同時’使線圈相面對， 晶圓測試以非接觸進行。而且，晶圓測試一終了，進行將 晶圓分割爲各晶片之切割（步驟S 1 9 )。 被分割之晶片藉由樹脂等之密封材料被密封於封裝中 (步驟S 2 0 )。此時，在步驟S 1 8之晶圓測試被判定 爲不良之晶片預先被去除。之後，封裝狀態之半導體積體 電路裝置藉由老化裝置被置於高溫下，以封裝狀態再度進 行藉由測試裝置之測試（步驟S 2 1、S 2 2 )。此時之 測試內容與在步驟S 1 8所進行之晶圓測試之內容幾乎相 同，而且，與晶圓測試相同地，由被搭載於測試用基板之 插座對被測試裝置只供給電源電壓，對被測試裝置之測試 資料之傳送或由被測試裝置來之測試結果之接收係透過被 相互面對之線圈而進行。而且，在此測試被判定爲不良者 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -21 - ϋ ϋ ϋ ϋ ϋ 1 ϋ ϋ ϋ . ϋ -ϋ I 1 ϋ I ϋ J,J ϋ H 1 H I ϋ I I (請先閱讀背面之注意事項再填寫本頁) 1246735 經濟部智慧財產局員工消費合作社印製 A7 B7 五、發明說明（19 ) 於封裝表面被賦予標記（步驟S 2 3 )，在篩選工程被去 除，只有良品被捆包出貨（步驟S 2 4 )。 圖1 1係顯示步驟S 1 8之晶圓測試以及步驟S 2 2 之基板測試之更詳細之測試順序。 在各測試中，首先檢查F P G A 1 2 0是否正常動作 ，被判定不良之有無，在有不良時，進行不良地方之迴避 (步驟S101〜S103)。接著，在去除FPGA 1 2 0內之上述不良地方之部份構築測試SRAM1 4 0 以及150用之測試電路（ALPG) ，SRAM140 以及1 5 0之測試依序被實行（步驟S 1 0 4、S 1 0 5 )° 於S R Α Μ 1 4 0以及1 5 0沒有發現不良地方之情 形，於去除F P GA 1 2 0內之上述不良地方之部份構築 測試定做邏輯電路1 1 0以及C P U 1 3 0用之測試電路 (邏輯測試機），實行定做邏輯電路1 1 0以及C P U 1 3 0之測試（步驟S 1 〇 6〜S 1 〇 8 )。此時，利用 檢查已經終了之S R A Μ，儲存測試圖案或測試圖案產生 程式。 在沒有發現不良之情形，在去除F P G A 1 0內之上 述不良地方之部份構築測試D R Α Μ 1 6 0〜1 8 0用之 測試電路（A L P G ) ，D R Α Μ 1 6 0〜1 8 0之測試 依序被實行（步驟Sl〇9、Sll〇)。而且，在不良 地方被發現之情形，其被記憶於S R Α Μ 1 4 0或1 5 0 或外部之記憶裝置厚，利用被設置於D R Α Μ 1 6 0〜 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -2Z- (請先閱讀背面之注意事項再填寫本頁)-16- A7 1246735 B7___ V. INSTRUCTIONS (14) Body circuit device. That is, T A P is a standardized circuit, and 4 to 5 test terminals can be self-tested. By applying T A P, the number of terminals necessary for the test can be reduced, and the number of terminals of L S I can be reduced. Further, in the interface circuit 2 of the TAP of this embodiment, while the clock generation circuit 2 2 3 is internally provided, the decoder circuit 2 2 4 for generating the control signal by decoding the received data can be completely eliminated. The serial input/output is possible, and the necessary terminals indicate P1 and P2 which are connected as the spiral pattern 11 of the coil. Another embodiment of the transmission receiving circuit 2 2 0 provided in the above T A P 2 0 0 is shown in FIG. In Fig. 8, 2 2 8 is a diode bridge which generates a DC power supply voltage by rectifying an AC signal input from a coil (1 1 ) connected between two terminals of a coil (scroll pattern 1 1 ). The rectifying circuit is formed, and the 2 2 9 system monitors the voltage outputted by the rectifying circuit 2 2 8 , and the detecting signal is input to the coil ( 1 1 ) to generate the starting circuit of the start signal ST, and the 24 1 system is connected to the coil ( 1 1) Between the two terminals, the data receiving circuit that inputs the AC signal and outputs the waveform, and the signal receiving circuit that is modulated by the modulation circuit 2 27 is opened and closed to drive the 汲 terminal through the capacitor C t 1. C t 2 is connected to the driving MOSFETs Qd1, Qd2 of one of the terminals of the coil (1 1 ), and the resonant circuit formed by the capacitors C t 1 , C t 2 and the coil (1 1 ) is switched to resonance. The state and non-resonant state, the data transmission circuit formed by the drive circuit for transmitting data. Moreover, the above capacitors C t 1 , C t 2 can be formed in the wafer, and the paper size is applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) --------^----- ---- (Please read the note on the back and then fill out this page) Ministry of Economic Affairs Intellectual Property Bureau employee consumption cooperative printing 1246735 A7 B7___ V. Invention description (15) (Please read the phonetic on the back? However, in order to suppress an increase in the size of the wafer, a cut region between the respective wafers may be formed. Moreover, in the foregoing embodiment, the power supply voltage for testing is given by the power supply pad 2 1 or the power supply pad 2 2 is provided on the wafer, but in the embodiment of FIG. Alternatively, a voltage limiter circuit for absorbing a variation of a voltage rectified by the rectifier circuit, generating a power supply voltage V cc of a specified potential, and causing the resistor circuit to be generated by the limiter circuit may be disposed under the rectifier circuit 2 2 8 A power supply stabilization circuit formed by a series voltage regulator such as a power supply voltage V cc is stabilized, and a power supply voltage outputted from the power supply stabilization circuit is supplied to each circuit inside the wafer, and each wafer is tested without a power supply pad. It is composed of the power supply voltage of the action. Fig. 9 is a view showing the configuration of an apparatus of an embodiment of the present invention in the case of a semiconductor device in which a different semiconductor memory such as a flash memory or an SR A is laminated to form a C Ρ (wafer size package) structure. In the Ministry of Economic Affairs, the Intellectual Property Office and the Consumer Cooperatives printed in Figure 9, 500 is the insulating substrate that forms the printed circuit, and the 5 10 is formed as a bump under the substrate 500, and the 5 2 0 is The first memory such as a flash memory mounted on the upper surface of the insulating substrate 500, 530 is a second memory such as SRA 搭载 mounted on the memory 520. The flash memory 520 is bonded to the insulating substrate 510 and between S R A Μ 5 3 0 and the flash memory 520 by an adhesive or the like. Although not shown, a test circuit and a transmission/reception circuit are provided inside the wafers of the flash memory 520 and the S R A Μ 5 3 0, respectively. SRA Μ 5 3 0 is set to be smaller than flash memory 520. The paper size is applicable to China National Standard (CNS) A4 specification (210 X 297 mm). 1246735 A7 B7 Ministry of Economic Affairs Intellectual Property Bureau Staff Consumption Cooperative Printed five, invention description (16) The size of the chip is that the flash memory 5 2 0 is mounted on the SRA Μ 5 3 〇, and the flash memory 5 2 0 is protruded outside the SRA Μ 5 3 0 The wafer epitaxial portion forms a pad row 5 2 1 , 5 2 2 of the flash memory, and the pad row 5 2 1 , 5 2 2 and the corresponding pad portion on the insulating substrate 500 are formed between The pads 5 5 1 and 5 3 2 of the wafer extension portion of the s RA Μ 5 3 0 and the corresponding pad portions on the insulating substrate 500 are electrically connected by bonding wires 5 4 1 to 5 4 4, respectively. Continued. In this embodiment, the spiral pattern 11 formed of the conductive layer is formed on the surface of the insulating substrate 500 under the memory wafer or in the substrate. The connecting wirings 1 1 a, 1 1 b are respectively scrolled Both ends of the pattern 1 1 are drawn, and the pads 55 1 and 552 provided at the ends of the wirings 1 1 a and 1 1 b and the input and output of the transmission/reception circuits provided in the respective wafers 520 and 530 The terminals (terminals P 1 and P 2 in Fig. 7) are also connected by a bonding wire. Therefore, the spiral pattern 11 on the substrate is set as a common coil of the above-described flash memory chip 520 and S R A Μ wafer 530, and the input and output signals for testing the respective wafers are performed through the coil. In this way, even if the signal is input and output through the common line, different identification codes are stored in each chip, and when the transmission and reception are performed, the identification code is transmitted together with the test result, and the external test device can recognize exactly Test results for one wafer. Next, the development and manufacturing sequence of the system L S I of Fig. 6 which is an example of a semiconductor integrated circuit device will be described using Fig. 10. The development of the semiconductor integrated circuit device first carries out the semiconductor to be developed-------------------CPlease read the back of the note first and then fill in this page) China National Standard (CNS) A4 Specification (210 X 297 mm) -19- 1246735 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed Β7 Β7 V. Invention Description (17) Logic design of integrated circuit (step S 1 1 ). This logic function design is generally performed using H D L. Further, regarding the H D L description, the support tool (program) for automatically generating the H D L description from the state transition diagram or the flowchart is provided by the E D Α supplier, and can be efficiently used in the case of using it. Further, the design data described by H D L is subjected to a hypothetical test for verifying whether or not the operation is appropriate by generating a verification program called a test vector test form. The H D L description is corrected by finding a bad situation by a hypothetical test. Next, based on the data designed in step S11, the circuit design of the logic gate level is performed (step S1 2). Specifically, a cell such as a logic gate or a flip-flop that constitutes a circuit having a desired function is designed. Further, based on the design data, logical synthesis is performed, and design information describing the connection information between the logic gates and the units in the form of a net order is prepared (step s 1 3 ). Further, as in the case of the gate array, in the case where the desired logic function is formed on the L S I of the circuit design of the logic gate, the circuit design of the step S 12 can be omitted. Further, here, the ED supplier supplies the design data which is converted into the logic gate level by the design data described by H D L, and synthesizes a program called a logic synthesis tool, which can be used. Again, the design data for the generated logic gate level is again verified by the test vector (hypothetical tester). The design data of the logic gate level is corrected in the case where the imaginary tester finds a bad condition. Next, based on the design data of the above-described logic gate level described in the form of a net order, the arrangement data of the component level is generated by a program called an automatic placement tool (step S1 4). This automatic placement tool is also applicable to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) from multiple paper scales -20- -------- order--------- Please read the notes on the back and fill out this page.) Ministry of Economic Affairs, Intellectual Property Office, Staff Consumer Cooperative, Printed 1246735 A7 B7 V. The invention (18) provided by the EDA supplier. Thereafter, the arrangement of the wafers on the wafer is determined (step S15). At this time, the arrangement of the spiral pattern of the coil formed on each wafer and the arrangement of the wiring connecting the coil and the transfer receiving circuit in the wafer are also determined. Further, the reticle pattern data is generated by the original image (a r t w 〇 r k ) according to the determined arrangement data, and a reticle is produced based on the data (step S 16). Thereafter, the semiconductor integrated circuit is formed by performing a process such as diffusion processing or formation of a wiring pattern on the semiconductor wafer by the prior art (step S17). Thereafter, the wafer is set on the test apparatus to face the probe cards, and the test is started (step S18). In this embodiment, the test apparatus shown in Fig. 2 is used for this wafer test. At this time, the probes of the probe cards are brought into contact with the power pads of the respective wafers on the wafer, and the coils are faced, and the wafer test is performed in a non-contact manner. Further, at the end of the wafer test, the wafer is divided into individual wafers (step S1 9). The divided wafer is sealed in the package by a sealing material such as resin (step S20). At this time, the wafer which is determined to be defective in the wafer test in step S18 is previously removed. Thereafter, the packaged semiconductor integrated circuit device is placed at a high temperature by the aging device, and the test by the test device is again performed in the package state (steps S 2 1 , S 2 2 ). The test content at this time is almost the same as the content of the wafer test performed in step S18, and, similarly to the wafer test, only the power supply voltage is supplied to the device under test by the socket mounted on the test substrate, The transmission of the test data of the device under test or the reception of the test results by the device under test is performed by the coils facing each other. Moreover, in this test, the paper size is determined by the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -21 - ϋ ϋ ϋ ϋ ϋ 1 ϋ ϋ ϋ . ϋ -ϋ I 1 ϋ I ϋ J,J ϋ H 1 HI ϋ II (Please read the note on the back and fill out this page) 1246735 Ministry of Economic Affairs Intellectual Property Office Staff Consumer Cooperative Printed A7 B7 V. Invention Description (19) Marked on the package surface (step S 2 3 ), the screening project is removed, and only the good products are bundled for shipment (step S 2 4 ). Figure 1 1 shows a more detailed test sequence for the wafer test of step S 18 and the substrate test of step S 2 2 . In each test, first, it is checked whether or not F P G A 1 2 0 is normally operated, and it is judged whether or not the defect is present. If there is a defect, the avoidance of the defective place is performed (steps S101 to S103). Then, the test circuit (ALPG) for testing the SRAMs 1 4 and 150, the SRAM 140 and the 150 test are sequentially executed in the part of the above-mentioned defective places in the FPGA 120 (step S1 0 4, S). 1 0 5 )° In the case where no bad places were found in SR Α Μ 1 4 0 and 1 50, part of the above-mentioned bad places in FP GA 1 2 0 was removed to test the custom logic circuit 1 1 0 and CPU 1 3 The test circuit (logic tester) used for 0 performs the test of the custom logic circuit 1 10 and the CPU 1 3 0 (steps S 1 〇 6 to S 1 〇 8 ). At this time, the test pattern or test pattern generation program is stored by checking the already completed S R A Μ. In the case where no defect is found, the test circuit (ALPG) for testing DR Α Μ 1 6 0~1 8 0 is constructed in part of removing the above-mentioned bad places in FPGA 10, DR Α Μ 1 6 0~1 8 0 The tests are carried out in sequence (steps S1, S11). Moreover, in the case where it is found in a bad place, it is memorized in SR Α Μ 4 1 1 0 or 1 50 or the external memory device is thick, and the use is set to DR Α Μ 1 6 0~ This paper scale applies to the Chinese national standard ( CNS) A4 size (210 X 297 mm) -2Z- (Please read the notes on the back and fill out this page)
A7 1246735 B7_ 五、發明說明（2〇 ) 1 8 0之冗餘電路，救濟不良位元用之救濟程式被讀入 CPU130，藉由CPU130該程式被實行，進行位 元救濟（步驟S 1 1 1、S 1 1 2 )。 之後，關於良品，在去除F PGA 1 2 0內之上述不 良地方之部份，構成使用者邏輯等之定做邏輯之一部份， 完成系統L S I (步驟S 1 1 3 )。在此步驟S 1 1 3中 ，利用顯示在步驟S 1 〇 1所獲得之不良地方之資訊，避 免該不良地方地將構成使用者邏輯之資料寫入F P GA 1 2 0內之接續資訊記憶用記憶體單元，構成所期望之邏 輯。 藉由以上之順序，具有所期望之機能之系統L S I被 構築完成。如此被構築之L S I藉由避免不良地方被構成 在FPGA1 20內之測試電路，實行RAM或DRAM 、C P U以及A D轉換電路之測試之故，不使用高機能之 外部測試機，可以獲得信賴性高之測試結果之同時，成品 率也提升。又，測試以非接觸進行之故，不須於晶片預先 設置測試用之端子，可以減少外部端子（銷）數。進而， 藉由被構成於F P G A 1 2 〇內之測試電路之自我測試終 了後’於F P G A 1 2 0構成定做邏輯之故，無謂之電路 變少，可以抑制多餘之晶片尺寸之增加。 以上’雖然依據實施例具體說明由本發明者所完成之 發明’但是本發明並不限定於上述實施例，在不脫離其要 旨之範圍內’不用說可以有種種變更可能。 例如，在上述實施例中，設置T A P，進行晶片內部 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） --------^--------- (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 1246735 A7 B7 五、發明說明（21 ) 之測試電路與外部之控制裝置之間的信號之輸入輸出，但 是本發明並不限定於此，不設置T A P，由測試電路藉由 直接傳送接收電路藉由線圈或天線輸入輸出晶片內部之掃 描路徑之信號而構成亦可。又，將前述實施例之渦卷狀之 導電層圖案當成天線以電波傳送接收信號之情形，傳送接 收電路之輸入輸出端子非圖案之兩端而是被接續於一方之 端部即可。又，以電波傳送接收信號之情形，成爲天線之 導電層圖案非渦卷狀而爲環狀或S狀等亦可。 又，於前述實施例中，雖就利用晶圓或晶片側之線圈 與探針卡側之線圏之間之相互感應現象以傳送接收信號、 利用電波以進行傳送接收者進行說明，但是其以外，例如 也可以組合發光二極體與受光元件，藉由光信號以傳送接 收，或透過使2片之電極相隔適當之間隔之靜電電容耦合 以傳送接收信號地構成。 產業上之利用可能性 本發明不單只是系統L S I ，也可以廣泛利用於內藏 測試電路之半導體積體電路及其之檢查方法以及製造方法 圖面之簡單說明 圖1係顯示本發明之半導體積體電路被形成之晶圓等 級之構成例之平面圖。 圖2係顯示檢查晶圓上之各半導體晶片之裝置之一構 (請先閱讀背面之注意事項再填寫本頁)A7 1246735 B7_ V. Description of the invention (2〇) The redundant circuit of the 180, the relief program for the relief bit is read into the CPU 130, and the program is executed by the CPU 130 to perform bit relief (step S 1 1 1 , S 1 1 2 ). Thereafter, with respect to the good product, part of the above-mentioned bad place in the removal of F PGA 1 2 0 constitutes a part of the custom logic of the user logic and the like, and the system L S I is completed (step S 1 1 3 ). In this step S1 1 3, the information of the bad place obtained in step S1 〇1 is displayed, and the information constituting the user logic is prevented from being written into the continuation information memory in the FP GA 1 2 0 in the bad place. The memory unit constitutes the desired logic. With the above sequence, the system L S I having the desired function is constructed. The LSI thus constructed can perform the test of the RAM or the DRAM, the CPU, and the AD conversion circuit by avoiding the defective test circuit formed in the FPGA 1 20, and can obtain the high reliability without using the high-performance external tester. At the same time as the test results, the yield is also improved. Further, since the test is performed in a non-contact manner, it is not necessary to previously set a terminal for testing on the wafer, and the number of external terminals (pins) can be reduced. Further, since the self-test of the test circuit formed in the F P G A 1 2 终 is completed, the F P G A 1 2 0 constitutes a custom logic, and the unnecessary circuit is reduced, and the increase in the excess wafer size can be suppressed. The present invention has been described with reference to the embodiments, but the invention is not limited to the above-described embodiments, and various modifications may be made without departing from the scope of the invention. For example, in the above embodiment, the TAP is set to apply the Chinese National Standard (CNS) A4 specification (210 X 297 mm) to the internal paper scale of the wafer --------^-------- - (Please read the notes on the back and fill out this page.) Ministry of Economic Affairs Intellectual Property Bureau Staff Consumer Cooperatives Printed Economy Ministry Intellectual Property Bureau Staff Consumer Cooperatives Printed 1246735 A7 B7 V. Inventions (21) Test Circuits and External Controlling the input and output of signals between the devices, but the present invention is not limited thereto, and the TAP is not provided, and the test circuit can be configured by the direct transmission and reception circuit by the signal of the scan path inside the input/output chip of the coil or the antenna. . Further, in the case where the spiral-shaped conductive layer pattern of the above-described embodiment is used as an antenna to transmit and receive signals by radio waves, the input/output terminals of the transmission/reception circuit are not connected to both ends of the pattern but are connected to one end portion. Further, in the case where the reception signal is transmitted by radio waves, the conductive layer pattern of the antenna may be non-vortexed, and may be annular or S-shaped. Further, in the above-described embodiment, the mutual induction phenomenon between the coil on the wafer side or the wafer side and the coil on the probe card side is used to transmit and receive signals, and radio waves are used to transmit the receiver. However, the description will be made. For example, the light-emitting diode and the light-receiving element may be combined, transmitted or received by an optical signal, or configured to transmit and receive signals by electrostatically coupling the electrodes of the two electrodes at appropriate intervals. INDUSTRIAL APPLICABILITY The present invention is not only a system LSI, but also a semiconductor integrated circuit which is widely used in a built-in test circuit, an inspection method thereof, and a description of a manufacturing method. FIG. 1 shows a semiconductor integrated body of the present invention. A plan view of a configuration example of a wafer level in which a circuit is formed. Figure 2 shows the structure of the device for inspecting each semiconductor wafer on the wafer (please read the notes on the back and fill out this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -24- 1246735 Α7 Β7 五、發明說明（22 ) 成例之斜視圖。 (請先閱讀背面之注意事項再填寫本頁) 圖3係顯示檢查晶圓上之各半導體晶片之裝置之其它 構成例之斜視圖。 圖4係顯示檢查晶圓上之各半導體晶片之順序之槪略 的流程圖。 圖5係顯示顯示檢查晶圓上之各半導體晶片之結果之 情形的表示例之說明圖。 圖6係顯示適用本發明合適之半導體積體電路之一例 之系統L S I之第1實施例之方塊圖。 圖7係顯示使用被顯示於圖6之ΤΑ P之介面電路2 〇 〇之構成例之方塊圖。 圖8係顯示被設置於上述TAP 2 0 〇之傳送接收電 路之其它之構成例之方塊圖。 圖9係顯示重疊如快閃記憶體或S R A Μ之類的不同 之半導體記憶體作成C S Ρ (晶片尺寸封裝）構造之半導 體裝置之情形之實施例之裝置構造之平面圖以及剖面圖。 經濟部智慧財產局員工消費合作社印製 圖1 0係顯示作爲半導體積體電路裝置之一例之圖6 之系統L S I之開法以及製造順序之流程圖。 圖1 1係顯示於圖1 0之步驟S 1 8之晶圓測試以及 步驟S 2 2之基板測試之更詳細之測試順序之流程圖。 主要元件對照 11 渦卷狀圖案 21、22 電源銲墊 -25^ 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） 1246735 A7 B7 五、發明說明（23 100 120 130、 140 150〜170 217、 218 220 221 222 223 231 233 300 320 321 322 500 520 530 半導體積體電路 CPU 靜態RAM 動態RAM 選擇器電路 傳送接收部 開關電路 解調電路 時脈產生電路 源振盪器 倍增電路 控制裝置 探針卡 探針 線圈 絕緣基板 第1記憶體 第2記憶體 經濟部智慧財產局員工消費合作社印製 (請先閱讀背面之注意事項再填寫本頁)This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -24-1246735 Α7 Β7 5. Inventive Note (22) Oblique view of the example. (Please read the precautions on the back and fill out this page.) Figure 3 is a perspective view showing another configuration example of the device for inspecting each semiconductor wafer on the wafer. Fig. 4 is a flow chart showing the procedure for inspecting the order of the respective semiconductor wafers on the wafer. Fig. 5 is an explanatory view showing an example of a display showing a result of inspecting each semiconductor wafer on a wafer. Fig. 6 is a block diagram showing a first embodiment of a system L S I which is an example of a suitable semiconductor integrated circuit of the present invention. Fig. 7 is a block diagram showing a configuration example using the interface circuit 2 〇 被 shown in Fig. 6 . Fig. 8 is a block diagram showing another configuration example of the transmission/reception circuit provided in the above TAP 200. Fig. 9 is a plan view and a cross-sectional view showing the configuration of an apparatus in which an embodiment of a semiconductor device in which a different semiconductor memory such as a flash memory or a RAM memory is formed into a C S Ρ (wafer size package) structure is stacked. Printed by the Intellectual Property Office of the Ministry of Economic Affairs, the Consumers' Cooperatives. Figure 10 shows a flow chart of the opening and manufacturing sequence of the system L S I of Figure 6 as an example of a semiconductor integrated circuit device. Figure 1 is a flow chart showing a more detailed test sequence of the wafer test of step S18 of Figure 10 and the substrate test of step S2 2. Main component comparison 11 Scroll pattern 21, 22 Power pad-25^ This paper size applies to China National Standard (CNS) A4 specification (210 X 297 mm) 1246735 A7 B7 V. Invention description (23 100 120 130, 140 150~170 217, 218 220 221 222 223 231 233 300 320 321 322 500 520 530 Semiconductor integrated circuit CPU static RAM dynamic RAM selector circuit transmission receiving section switching circuit demodulation circuit clock generation circuit source oscillator multiplication circuit control device Probe card probe coil insulation substrate 1st memory 2nd memory economic department intellectual property bureau employee consumption cooperative printing (please read the back note first and then fill this page)
本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公釐） -26^-This paper scale applies to the Chinese National Standard (CNS) A4 specification (210 X 297 mm) -26^-