經濟部智慧財產局員工消費合作社印製 4 6 641 Ο 53l2twf.doc/006 八？ ______Β7____ 五、發明說明（f ) 本發明是有關於一種快取(cache)裝置及其與外界之資 料同步方法，且特別是有關於一種週邊元件介面控制晶片 內部之快取裝置及其與外界之資料同步方法。 習知對於週邊元件介面讀取資料的處理，雖然會在週 邊元件介面控制晶片組中加入資料緩衝區，但是卻沒有提 供快取(cache)的功能。因此，每當週邊裝置需要從記憶體 讀取資料的時候，週邊元件介面控制晶片組就會執行讀取 指令，並到記憶體中讀取相關的資料。 請參考第1圖，其顯示了習知在週邊裝置讀取資料 時，週邊元件匯流排中部分信號的時序圖（Timing diagram)。由此圖中可以得知’在此週邊元件匯流排中共傳 輸了兩筆資料，此兩筆資料的傳輸啓始時間則分別是CLK1 以及CLK20。 在第1圖中，首先在CLK1的時候，FRAME信號線就 設定在動作(asserted)狀態，用以指出週邊元件匯流排要開 始進行資料的傳輸。而同時，AD信號線也將資料傳輸目的 地的位址擺置在匯流排上。在CLK2的時候，IRDY信號線 就已經設定在動作狀態，表示開始此次傳輸的週邊裝置已 經準備好開始資料傳輸，但是TRDY信號線則到CLK8的 時候才設定爲動作狀態。因此，資料就必須從CLK9開始 進行傳輸。而這一段從IRDY信號線設定爲動作狀態，一 直到TRDY信號線設定爲動作狀態的時間，就稱爲延遲時 間（latency)。 而在第1圖中的第二筆資料傳輸，是從CLK20的時 本紙張尺度適用中國國家標準（CNS)A4規格（2]〇χ 297公釐） (請先閱讀背面之注f項再填寫本頁) 裝 -- - ----訂--------- ί； ；410 5312twf . doc/00β Α7 --- Β7 五、發明說明（X) 候’ FRAME信號線設定爲動作狀態時開始。而且此第二筆 資料傳輸’是與第一筆資料相同，或是相差在一條線（1 line) ’也就是32個位元組(byte)，的位址以內。於是週邊 元件介面控制器對匯流排的控制，以及信號線的時序，都 會和第一筆資料傳輸時相同。 所以’第二筆資料傳輸，首先在CLK20的時候，:FRAME 信號線就設定在動作狀態，用以指出週邊元件匯流排要開 始進行資料的傳輸。而同時，AD信號線也將資料傳輸目的 地的位址擺置在匯流排上。在CLK21的時候，IRDY信號 線就已經設定在動作狀態，表示開始此次傳輸的週邊裝置 已經準備好開始資料傳輸，但是TRDY信號線則到CLK27 的時候才設定爲動作狀態。因此，資料就必須從CLK28才 能開始進行傳輸。 綜上所述，習知在週邊元件介面傳輸的時候，縱使相 鄰兩筆資料的傳輸標的(Target)位址相同，或者位址相差在 一條線以內，仍然還會產生一段延遲時間。而這一段傳輸 時存在的延遲時間，就會造成整個週邊元件介面，包括週 邊元件匯流排以及週邊裝置，在使用效率上的降低。 有鑒於此，本發明提出一種週邊元件介面控制晶片內 部之快取裝置及其與外界之資料同步方法’其可以減少週 邊裝置讀取資料時所產生的延遲時間，增加週邊裝置以及 週邊元件匯流排的使用效率。藉由資料同步的方法，使得 在減少延遲時間之外，也能同時確保資料的正確性。 本發明提出一種週邊元件介面控制晶片內部之快取裝 本紙張义度適用中國國家標準（CNS)A4規格（210 X 297公髮） (請先閲讀背面之注意事項再填寫本頁)Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 641 Ο 53l2twf.doc / 006 ______ Β7 ____ 5. Description of the Invention (f) The present invention relates to a cache device and a method for synchronizing data with the outside world, and in particular, to a cache device inside a peripheral device interface control chip and its connection with the outside world. Data synchronization method. It is known that for the processing of reading data from the peripheral component interface, although a data buffer is added to the peripheral component interface control chipset, it does not provide a cache function. Therefore, whenever the peripheral device needs to read data from the memory, the peripheral component interface control chipset will execute the read command and read the relevant data into the memory. Please refer to Figure 1, which shows the timing diagram of some signals in the buses of peripheral components when reading data from peripheral devices. From this figure, it can be known that a total of two pieces of data are transmitted in the peripheral component bus, and the transmission start times of these two pieces of data are CLK1 and CLK20, respectively. In the first figure, at CLK1, the FRAME signal line is set to an asserted state to indicate that the peripheral component bus is to start data transmission. At the same time, the AD signal line also places the address of the data transmission destination on the bus. At CLK2, the IRDY signal line is already set to the operating state, which indicates that the peripheral device that started the transmission is ready to start data transmission, but the TRDY signal line is not set to the operating state until CLK8. Therefore, data must be transferred starting from CLK9. The period from when the IRDY signal line is set to the operating state until the TRDY signal line is set to the operating state is referred to as the latency. The second data transmission in Figure 1 is from CLK20 when the paper size is in accordance with the Chinese National Standard (CNS) A4 specification (2) 0 × 297 mm. (Please read the note f on the back before filling (This page) Install --- ---- Order --------- ί; 410 5312twf .doc / 00β Α7 --- Β7 V. Description of the invention (X) When the 'FRAME signal line is set to action Start at the time. In addition, the second data transmission is the same as the first data transmission, or the difference is within a line of 1 line, that is, within 32 bytes. Therefore, the control of the bus by the peripheral component interface controller and the timing of the signal lines will be the same as when the first data was transmitted. Therefore, the second data transmission, first at CLK20, the: FRAME signal line is set in the operating state, which indicates that the peripheral component bus is to start data transmission. At the same time, the AD signal line also places the address of the data transmission destination on the bus. At CLK21, the IRDY signal line is already set to the operating state, which indicates that the peripheral device that started the transmission is ready to start data transmission, but the TRDY signal line is not set to the operating state until CLK27. Therefore, data must be transmitted from CLK28. In summary, it is known that when the peripheral device interface is transmitting, even if the target addresses of two adjacent data transmissions are the same, or the addresses differ within a line, a delay time will still be generated. However, the delay time during this period of transmission will cause the entire peripheral component interface, including peripheral component buses and peripheral devices, to reduce the use efficiency. In view of this, the present invention proposes a cache device inside a peripheral device interface control chip and a method for synchronizing data with the outside world, which can reduce the delay time generated by the peripheral device when reading data, and increase the peripheral device and the peripheral component bus. Use efficiency. With the method of data synchronization, in addition to reducing the delay time, it can also ensure the accuracy of the data. The present invention proposes a quick loading device inside the peripheral component interface control chip. The paper is suitable for Chinese National Standard (CNS) A4 specifications (210 X 297) (please read the precautions on the back before filling this page)
> tl· n I * I* If I 迻！ 經濟部智慧財產局員工消費合作社印製 4 6 6 4 1 0 5312twfdoc/〇〇6 A7 B7 經濟部智慧財產局員工消費合作社印製 五、發明說明（9) 置，其運作於一個控制晶片中，使用於包括一組記憶體， 一個CPU匯流排’一個中央處理器，一個週邊兀件匯流排 以及至少一個週邊裝置的電腦系統中。此快取裝置包括一 個資料緩衝區以及一個週邊元件介面控制器。其中，資料 緩衝區位於控制晶片中’用以儲存自記億體所讀取之資料 串，以提供週邊裝置所需的資料。此外，並在此資料串與 此資料串在記憶體內之對應位址上的資料同步時，保留此 資料串；當任一週邊裝置需要此資料串所包括之資料時， 可立即提供此資料串所包括之資料，以減少自記憶體再度 讀取此資料串所須之時間。 而週邊元件介面控制器也位於控制晶片中，用以偵測 上述之資料串是否包括週邊裝置所需要的資料；偵測此資 料串是否與上述對應位址上之資料同步；自記憶體中取得 此資料串置入於資料緩衝區；以及轉換資料緩衝區包括此 資料串之部分的狀態。 本發明還提出一種週邊元件介面內部快取系統與外界 之資料同步方法，應用於包括一組記憶體，至少一個中央 處理器，一個控制晶片，一個週邊元件匯流排，一個CPU 匯流排以及至少一個週邊裝置的電腦系統中。其中’控制 晶片包括一個週邊元件介面控制器以及一個資料緩衝區° 且當記憶體中的記憶體資料串讀入於資料緩衝區中，會成 爲一個緩衝資料串。 此資料同步方法包括下列步驟。首先，當資料緩衝區 在初始化的時候，就設定爲空虛(Empty)狀態。 -------------f 裝--------訂---------線{ I (請先閱讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4蜆格（2丨ϋχ297公笼） 經濟部智慧財產局員工消費合作社印製 4 . 0。。/。。6 A7 _ B7 五、發明說明（十） 接下來，當週邊元件介面控制器根據週邊裝置的需 求，讀取緩衝資料串進入資料緩衝區時，就將資料緩衝區 包含此緩衝資料串的緩衝資料部分設定爲乾淨未取用 (Clean-no accessed)狀態。 而當上述之緩衝資料部分處於乾淨未取用狀態時，若 經由週邊元件介面控制器，在CPU匯流排中偵測到對上述 之對應位址進行寫入或讀取的動作時，就將此緩衝資料部 分設定爲不潔未取用（Dirty-no accessed)狀態。 此外，當此緩衝資料部分處於乾淨未取用狀態時，若 經由週邊元件介面控制器，在週邊元件匯流排中偵測到對 此對應位址進行寫入的動作，就將此緩衝資料部分設定爲 不潔未取用狀態。 而當此緩衝資料部分處於乾淨未取用狀態時，若需求 此緩衝資料串的週邊裝置從上述之緩衝資料部分中讀取緩 衝資料串，就將此緩衝資料部分設定爲乾淨已取用（Clean-accessed)狀態。 當此緩衝資料部分處於不潔未取用狀態時’若需求此 緩衝資料串的週邊裝置從此緩衝資料部分中讀取此緩衝資 料串後，則會將此緩衝資料部分設定爲上述的空虛狀態° 此外，當上述之緩衝資料部分處於乾淨已取用狀態 時，若經由週邊元件介面控制器’在CPU匯流排中偵測到 對上述之對應位址進行寫入或讀取的動作時’就將此緩衝 資料部分設定爲上述之空虛狀態。 而當緩衝資料部分處於乾淨已取用狀態時’若經由週 本紙張尺度適用中國國家標準（CNS)A4規格（210 X 297公爱） (請先閱讀背面之注意事項再填寫本頁) 裝------訂------ ---線1 經濟部智慧財產局員工消費合作社印製 ά 6 6 4 1 Ο 7 5312twf.doc/006 Α/ _ Β7___ 五、發明說明（^ ) 邊元件介面控制器，在週邊元件匯流排中偵測到對此對應 位址進行寫入的動作，就將此緩衝資料部分設定爲上述之 空虛狀態。 本發明也提出一種週邊元件介面內部快取系統與外界 之資料同步方法，應用於包括一組記憶體’至少一個中央 處理器，一個控制晶片’ 一個週邊兀件匯流排，一個CPU 匯流排以及至少一個週邊裝置的電腦系統中°其中控制晶 片包括一個週邊元件介面控制器以及一個資料緩衝區，且 中央處理器使用MOESI程序（MOESI protocol)，與MOESI相 關的技術及原理說明文件，可以由以下網址中得知槪要： http://www.sun.com/microelectronics/datasheets/stpl 030/lO.ht ml。當記憶體中的記憶體資料串讀入於中央處理器中，則 成爲一個快取資料串，而當記憶體資料串讀入於資料緩衝 區中，則成爲一個緩衝資料串。 此資料同步方法包括下列步驟：當快取資料串處於修 改(Modified)狀態時，若資料緩衝區對此快取資料串在記憶 體中相對應的對應位址執行讀取動作，則週邊元件介面控 制器會使中央處理器將此快取資料串設定於擁有者(Owner) 狀態。 而當此快取資料串處於除外(Exclusive)狀態時，若資料 緩衝區對此對應位址執行讀取動作，則週邊元件介面控制 器會使中央處理器將此快取資料串設定於分享（Shared)狀 態。 綜上所述，本發明藉由在控制晶片中加入資料緩衝 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） illilllllllA 裝 i — !!訂---------I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 ；：> 5 4 10 53l2twf. doc/006 A7 —_____li? 五、發明說明（< ) 區，除了儲存此次讀取之資料以外，也同時儲存此次讀取 之資料附近位址的其他資料，減少週邊裝置讀取資料時所 產生的延遲時間，增加週邊裝置以及週邊元件匯流排的使 用效率。此外’並藉由資料同步的方法，使得在減少延遲 時間之外’也能同時確保資料的正確性。 爲讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂’下文特舉較佳實施例，並配合所附圖式，作詳細 說明如下： 圖式之簡單說明： 第1圖繪示的是一時序圖，其顯示了在習知中，週邊 裝置自記憶體中讀取兩筆資料時，部分信號的時脈； 第2圖繪示的是一裝置圖，其顯示了根據本發明之一 較佳實施例的裝置連結方式； 第3圖繪示的是一時序圖，其顯示了在根據本發明之 一較佳實施例中’週邊裝置自記億體中讀取兩筆資料時， 部分信號的時脈； 第4圖繪示的是一狀態改變圖，其顯示了根據本發明 之一較佳實施例中’資料緩衝區內的資料狀態改變流程； 以及 第5圖繪示的是一狀態改變圖，其顯示了根據本發明 之一較佳實施例，在一中央處理器中之資料，依照MOESI 程序的狀態變化流程。 雷要元件標號 10 :控制晶片 本紙張尺度適用中國國家標準（CNS)A··!規樁（21〇x 297公釐） -----------认't-------—訂--------- (請先間讀背面之注意事項再填寫本頁) 06 06 A7 B7 64 10 53l2twf.d〇c/0 五、發明說明（9 ) 15 :週邊元件匯流排 2〇 :週邊元件介面控制器 25 :資料緩衝區 3〇 :記憶體 35 :記憶體匯流排 40 :中央處理器(CPU) 45 : CPU匯流排 50 :週邊裝置 較佳實施例 請參照第2圖，其繪示的是依照本發明之一較佳實施例 的一種裝置連結方式。在本實施例中，包括了記憶體30 ’ 控制晶片10，週邊裝置50，中央處理器40，週邊元件匯流 排15，CPU匯流排45，記憶體匯流排35，週邊元件介面控制 器20以及資料緩衝區25。 其中，資料緩衝區25位於控制晶片1〇之中，用以儲存 自記憶體30所讀取之資料串，以提供週邊裝置50所需的資 料。而週邊元件介面控制器20也位於控制晶片10之中，用 以偵測資料緩衝區25之中的資料串是否包括週邊裝置5〇所 需要的資料。此外’週邊元件介面控制器20也偵測週邊元 件匯流排15以及CPU匯流排45中，對於此資料在記憶體3〇 相對應的位址上之動作’以判別此資料串是否仍爲有效杳 料。週邊元件介面控制器20會將此資料串保留，直到有其 他的資料串必須使用到這一部份的空間，或是此資料串已 經與正確的資料不同步爲止。 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） ------------f 裝-------訂· —-------線5 I (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作杜印製 Λ7 B7 53l2twf.doc/006 五、發明說明（f ) 另外，週邊元件介面控制器20還能根據週邊裝置50的 需求，自記憶體30中取得資料串，並置入控制資料緩衝區 25中；而且，週邊元件介面控制器20會傳送一個探測讀取 命中信號(ProbeHitRd)至中央處理器40。除此之外’對於上 述偵測對於相對應位址之動作，包括接納週邊元件匯流排 15對此相對應位址進行寫入動作時所發出之信號，接納 CPU匯流排45進行寫入動作時所發出之信號，以及接納CPU 匯流排45進行讀取動作時所發出之信號。另外’週邊元件 介面控制器20也同時根據偵測的結果，控制資料緩衝區25 的狀態轉換。 在本實施例中，資料緩衝區25包括了八條線(line)，而 每一條線的容量爲32個位元組(Byte)。所以在此處，資料緩 衝區25的總容量爲256個位元組。此外，在本實施例中，每 兩條線被區分爲一個傳輸區塊，而每個傳輸區塊則儲存一 次傳輸所讀取的資料。由於在本實施例中以兩條線爲一個 傳輸區塊，所以一次傳輸所讀取的資料，除了週邊裝置50 需要的資料之外，也同時讀取了自此資料之後，包括此資 料共兩條線的資料。也就是說，總共讀取了 64個位元組的 資料。 請合倂參考第2圖以及第3圖，其中，第3圖顯示了在根 據本發明之一較佳實施例中，週邊裝置50自記憶體30中讀 取兩筆資料時，在週邊元件匯流排15上部分信號的時脈變 化。比較第1圖與第3圖可以得知，在讀取第1筆資料的時 候，在時脈上並沒有不同。但是，在讀取第1筆資料之後， 本紙張尺度適用中國國家標準（CNS)A4規格（2,10 X 297公釐） --nil —-----*·^--------訂—------ (請先閲讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員Η消費合作社印製 46 64 1 Ο 5312twf.doc/006 五、發明說明（7 ) 週邊兀件介面控制描20會目買入包括此桌1筆資料在內，總共 64個位元組的資料，並將這些資料都存入在資料緩衝區25 的一個傳輸區塊中。於是，當週邊裝置5〇要讀取第2筆資 料，而且此第2筆資料的位址與第1筆資料的位址相同，或 是位址包含的資料包含在此傳輸區塊中，也就是64個位元 組之內，的時候，就會如第3圖所示，讀取第2筆資料的情 況一樣，其延遲就只從CLK21到CLK22，僅—個CLK的時 間。而習知讀取同樣的第2筆資料，卻需花費六個CLK的時 間。所以，根據上述資料可以輕易得知’本發明能使得週 邊元件介面在傳輸資料上有極大的效率成長。 接下來請合倂參照第2圖以及第4圖，其顯示了根據本 發明之一較佳實施例。其中，第4圖顯示了在本實施例中， 控制晶片10中之資料緩衝區25內的資料狀態改變流程。其 包括四種狀態，分別爲空虛（Empty)狀態400，乾淨未取用 (Clean-no accessed)狀態410，不潔未取用（Dirty-no accessed) 狀態430以及乾淨已取用（Clean-accessed)狀態420。 其中，記憶體30中的任一個記憶體資料串，經由中央 處理器40讀入後，會形成一個快取資料串，而此記憶體資 料串讀入於資料緩衝區25中，會形成一個緩衝資料串。而 此記憶體資料串，快取資料串以及緩衝資料串皆對應於記 憶體30中一個相同的對應位址。 首先，資料緩衝區25在初始化的時候’會被設定爲空 虛狀態400。 而當週邊元件介面控制器20根攄週邊裝置50的需求’ ί請先閱讀背面之注意事項再填寫本頁)> tl · n I * I * If I shift! Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 6 4 1 0 5312twfdoc / 〇〇6 A7 B7 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs. 5. Description of the Invention (9), which operates in a control chip. It is used in a computer system including a set of memory, a CPU bus, a central processing unit, a peripheral hardware bus, and at least one peripheral device. The cache device includes a data buffer and a peripheral component interface controller. Among them, the data buffer is located in the control chip, which is used to store the data string read by the self-recording body to provide the data required by the peripheral device. In addition, when the data string is synchronized with the data of the corresponding address of the data string in the memory, the data string is retained; when any peripheral device needs the data included in the data string, the data string can be provided immediately Included data to reduce the time required to read this data string from memory again. The peripheral component interface controller is also located in the control chip, and is used to detect whether the above-mentioned data string includes data required by the peripheral device; to detect whether this data string is synchronized with the data at the corresponding address; obtained from the memory The data string is placed in a data buffer; and the state of the data buffer including a portion of the data string is converted. The invention also provides a method for synchronizing the internal cache system of the peripheral component interface with external data, which is applied to a group of memory, at least one central processing unit, a control chip, a peripheral component bus, a CPU bus, and at least one Computer system of peripheral devices. The control chip includes a peripheral component interface controller and a data buffer. When the memory data string in the memory is read into the data buffer, it becomes a buffered data string. This data synchronization method includes the following steps. First, when the data buffer is initialized, it is set to Empty. ------------- f Pack -------- Order --------- Line {I (Please read the notes on the back before filling this page) This The paper size is in accordance with Chinese National Standard (CNS) A4 蚬 (2 丨 ϋχ297). Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 4.0. . /. . 6 A7 _ B7 V. Description of the invention (ten) Next, when the peripheral component interface controller reads the buffered data string into the data buffer according to the requirements of the peripheral device, the data buffer contains the buffered data of the buffered data string. Some are set to Clean-no accessed. When the above-mentioned buffered data part is in a clean and unused state, if a write or read operation to the corresponding address is detected in the CPU bus through the peripheral component interface controller, The buffer data part is set to Dirty-no accessed. In addition, when the buffered data part is in a clean and unretrieved state, if a write operation to the corresponding address is detected in the peripheral component bus through the peripheral device interface controller, the buffered data part is set Unclean and unused. When the buffered data part is in a clean and unretrieved state, if the peripheral device that requires the buffered data string reads the buffered data string from the buffered data part described above, the buffered data part is set to clean and taken (Clean -accessed) status. When this buffered data part is in an unclean and unretrieved state, 'If the peripheral device that requires this buffered data string reads this buffered data string from this buffered data part, it will set this buffered data part to the above-mentioned empty state. When the above-mentioned buffered data part is in a clean and retrieved state, if the operation of writing or reading the corresponding address is detected in the CPU bus through the peripheral component interface controller, The buffer data part is set to the above-mentioned empty state. And when the buffer data part is in a clean and ready-to-receive state, if the Chinese National Standard (CNS) A4 specification (210 X 297 public love) is applied through the paper size of this week (please read the precautions on the back before filling this page). ----- Order ------ --- Line 1 Printed by the Consumer Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs 6 6 4 1 Ο 7 5312twf.doc / 006 Α / _ Β7 ___ V. Description of the Invention (^) The edge component interface controller detects a write operation to the corresponding address in the peripheral component bus, and sets the buffer data part to the above-mentioned empty state. The invention also proposes a method for synchronizing the internal cache system of the peripheral component interface with the external data, which is applied to a group of memory 'at least one central processing unit, one control chip', one peripheral hardware bus, one CPU bus and at least In a computer system of a peripheral device, the control chip includes a peripheral component interface controller and a data buffer, and the central processing unit uses the MOESI protocol (MOESI protocol). The MOESI-related technology and principle documentation can be downloaded from the following URL Learned from: http://www.sun.com/microelectronics/datasheets/stpl 030 / lO.ht ml. When the memory data string is read into the CPU, it becomes a cache data string, and when the memory data string is read into the data buffer area, it becomes a buffered data string. This data synchronization method includes the following steps: When the cached data string is in a Modified state, if the data buffer performs a read operation on the corresponding address of the cached data string in memory, the peripheral component interface The controller causes the central processing unit to set the cached data string to the owner state. When the cached data string is in an Exclusive state, if the data buffer performs a read operation on the corresponding address, the peripheral component interface controller will cause the central processing unit to set the cached data string to share ( Shared) status. To sum up, by adding data buffer to the control chip, the present invention applies the Chinese National Standard (CNS) A4 specification (210x297 mm). IllilllllllA Pack i — !! Order --------- I (Please read the notes on the back before filling out this page) Printed by the consumer cooperation department of the Intellectual Property Bureau of the Ministry of Economic Affairs: > 5 4 10 53l2twf. Doc / 006 A7 —_____ li? V. Description of Invention (&); In addition to storing the data read this time, it also stores other data at addresses near the data read this time, reducing the delay time caused by peripheral devices to read data, and increasing the efficiency of the use of peripheral devices and peripheral component buses. . In addition, “the data synchronization method is used to reduce the delay time” to ensure the correctness of the data. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, the following describes a preferred embodiment in conjunction with the accompanying drawings, which are described in detail as follows: Brief description of the drawings: FIG. 1 Shows a timing diagram, which shows the clock of some signals when the peripheral device reads two pieces of data from the memory in the known; Figure 2 shows a device diagram, which shows A preferred embodiment of the invention is a device connection mode. FIG. 3 is a timing chart showing a case where two pieces of data are read from a peripheral device's self-recording device according to a preferred embodiment of the present invention. The timing of some signals; FIG. 4 shows a state change diagram, which shows the flow of data state change in the “data buffer” according to a preferred embodiment of the present invention; and FIG. 5 shows It is a state change diagram, which shows a state change flow of data in a central processing unit according to a MOESI program according to a preferred embodiment of the present invention. Lei Yao component number 10: Control chip The paper size is applicable to the Chinese National Standard (CNS) A · !! gauge pile (21 × x297 mm) ----------- Recognize 't ---- ----- Order --------- (Please read the precautions on the back before filling this page) 06 06 A7 B7 64 10 53l2twf.d〇c / 0 V. Description of the invention (9) 15: Peripheral component bus 20: Peripheral component interface controller 25: Data buffer 30: Memory 35: Memory bus 40: Central processing unit (CPU) 45: CPU bus 50: Peripheral device Referring to FIG. 2, it illustrates a device connection method according to a preferred embodiment of the present invention. In this embodiment, a memory 30 ′ control chip 10, a peripheral device 50, a central processing unit 40, a peripheral component bus 15, a CPU bus 45, a memory bus 35, a peripheral component interface controller 20, and data are included. Buffer 25. The data buffer 25 is located in the control chip 10 and is used to store the data string read from the memory 30 to provide the data required by the peripheral device 50. The peripheral component interface controller 20 is also located in the control chip 10 to detect whether the data string in the data buffer 25 includes data required by the peripheral device 50. In addition, the “peripheral component interface controller 20 also detects the movement of this data at the corresponding address of the memory 30 in the peripheral component bus 15 and the CPU bus 45” to determine whether the data string is still valid. material. The peripheral component interface controller 20 will keep this data string until other data strings must use this part of space, or this data string has not been synchronized with the correct data. This paper size is applicable to China National Standard (CNS) A4 specification (210x297 mm) ------------ f Packing --------- Order · --------- Line 5 I (Please read the precautions on the back before filling this page) Printed by the Intellectual Property Bureau of the Ministry of Economic Affairs on consumer cooperation Du Λ7 B7 53l2twf.doc / 006 V. Description of the invention (f) In addition, the peripheral component interface controller 20 can also be based on According to the requirements of the peripheral device 50, the data string is obtained from the memory 30 and placed in the control data buffer 25; In addition, the peripheral component interface controller 20 sends a probe read hit signal (ProbeHitRd) to the central processing unit 40. In addition to this, for the above-mentioned detection of the corresponding address, including receiving the signal sent by the peripheral component bus 15 when writing to the corresponding address, and accepting the CPU bus 45 for the writing operation The signal sent out and the signal sent out when the CPU bus 45 is accepted for reading. In addition, the peripheral device interface controller 20 also controls the state transition of the data buffer 25 according to the detection result. In this embodiment, the data buffer area 25 includes eight lines, and the capacity of each line is 32 bytes. So here, the total capacity of the data buffer area 25 is 256 bytes. In addition, in this embodiment, every two lines are divided into one transmission block, and each transmission block stores data read for one transmission. Since two lines are used as a transmission block in this embodiment, in addition to the data required by the peripheral device 50, the data read in one transmission is also read at the same time. Information about the lines. That is, a total of 64 bytes of data were read. Please refer to FIG. 2 and FIG. 3 together. FIG. 3 shows that in a preferred embodiment of the present invention, when the peripheral device 50 reads two pieces of data from the memory 30, it converges on the peripheral components. The clock of some signals on row 15 changes. Comparing Figure 1 and Figure 3, it can be seen that when reading the first data, there is no difference in the clock. However, after reading the first data, the paper size is applicable to the Chinese National Standard (CNS) A4 specification (2,10 X 297 mm) --nil ------- * · ^ ------ --Order ------- (Please read the precautions on the back before filling out this page) Printed by the Consumers' Cooperative of the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Intellectual Property Bureau of the Ministry of Economic Affairs and printed by the Consumer Cooperatives 46 64 1 Ο 5312twf.doc / 006 V. Description of the invention (7) Peripheral element interface control drawing 20 will buy a total of 64 bytes of data including this table of data, and store these data in the data buffer 25 In a transmission block. Therefore, when the peripheral device 50 wants to read the second piece of data, and the address of the second piece of data is the same as the address of the first piece of data, or the data contained in the address is included in this transmission block, It is within 64 bytes. When the second data is read as shown in Figure 3, the delay is only from CLK21 to CLK22, which is only one CLK time. It takes six CLKs to read the same second data. Therefore, according to the above data, it can be easily known that the present invention can make the peripheral component interface have a great efficiency growth in transmitting data. Next, please refer to FIG. 2 and FIG. 4 together, which show a preferred embodiment according to the present invention. FIG. 4 shows a data state changing process in the data buffer 25 in the control chip 10 in this embodiment. It includes four states: Empty state 400, Clean-no accessed state 410, Dirty-no accessed state 430, and Clean-accessed State 420. Among them, any memory data string in the memory 30 is read into the cache data string after being read in by the central processing unit 40, and this memory data string is read into the data buffer 25 to form a buffer. Data string. The memory data string, the cache data string, and the buffer data string all correspond to a same corresponding address in the memory 30. First, the data buffer 25 is set to the empty state 400 when it is initialized. And when the peripheral device interface controller 20 needs the peripheral device 50 ’, please read the precautions on the back before filling this page)
裝-------—訂---II 本紙張尺度適用中囤國家標準（CNS)A4規格（210x 297公釐） 經濟部智慧財產局員工消費合作社印製 4 6 64 1 Ο 5 312 twf . doc /0 0 6 ^ _____B7________五、發明說明（~) 自記憶體3〇中讀取記憶體資料串進入資料緩衝區25時’就 經由流程440，將資料緩衝區25中包含此記憶體資料串’也 就是緩衝資料串的緩衝資料部分’設定爲乾淨未取用狀態 410。 接下來，當上述的緩衝資料部分處於乾淨未取用狀態 410的時候，若經由週邊元件介面控制器2〇 ’在CPU匯流排 45中偵測到對上述的對應位址進行寫入或者讀取的動作； 或是經由週邊元件介面控制器20，在週邊元件匯流排15中 偵測到對此對應位址進行寫入的動作時，就經由流程450 ’ 將此緩衝資料部分設定爲不潔未取用狀態430。 此外，當緩衝資料部分處於乾淨未取用狀態410的時 候 > 若需求此緩衝資料串的週邊裝置50從資料緩衝區25中 讀取此緩衝資料串，則週邊元件介面控制器20就經由流程 460，將緩衝資料部分設定爲乾淨已取用狀態420。 接下來，當緩衝資料部分處於不潔未取用狀態430的時 候，若需求此緩衝資料串的週邊裝置50從資料緩衝區25中 讀取此緩衝資料串，則經由流程470,將上述的緩衝資料部 分設定爲空虛狀態400。 除此之外，當緩衝資料部分處於乾淨已取用狀態420 的時候，若經由週邊元件介面控制器20，在CPU匯流排45 中偵測到對上述之對應位址進行寫入或者讀取的動作；或 是經由週邊元件介面控制器20，在週邊元件匯流排15中偵 測到對此對應位址進行寫入的動作時，則經由流程480，將 上述之緩衝資料部分設定爲空虛狀態4〇〇。 ---- ^ I ----—1 訂-------線 (請先間讀背面之注意事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（2】0 X 297公餐） 5 3 12 twf. doc /0 0 6 Λ7 Π7 經濟部智慧財產局員工消費合作社印製 五、發明說明（//) 接下來請參照第5圖，其顯示了根據本發明之一較佳實 施例，在一中央處理器中快取記憶體(cache memory)內部之 資料，依照MOESI程序(MOESI Protocol)的狀態變化流程。 有關於MOESI的運作方法，現簡述如下。 所謂的MOESI，就是包含修改狀態（M，Modif丨ed)510， 擁有者狀態（〇，〇wner)540，除外狀態（E，Exclusive)520， 分享狀態（S，Shared)530以及無效狀態（I，Invalid)500。此 MOESI程序是用來保持中央處理器內部之快取記憶體與外 部快取記憶體之間資料的一致性。 其中，當中央處理器內部之快取記憶體處於無效狀態 500時，若有資料自記憶體中讀入，且其他的快取記憶體中 並沒有包括此資料的部分，則中央處理器內部之快取記憶 體就會轉換爲除外狀態520(I-E轉換）。此外，若是自記憶體 中讀入的資料在其他的快取記憶體中有另一份備份的話’ 則中央處理器內部之快取記憶體就會轉換爲分享狀態 530(I-S轉換）。另外，當在此快取記憶體中產生寫入失誤 (Write miss)時，則資料會自動從記憶體中讀入’並且將狀 態轉換爲修改狀態510(I-M轉換）。 而當中央處理器內部之快取記憶體資料處於除外狀態 520時，若在此快取記憶體中對此資料有修改的動作’則會 轉換爲修改狀態51〇(E-M轉換）。而若是自系統傳來要求這 一份處於除外狀態520的資料’則此資料就會轉換爲分享狀 態530(E-S轉換）。而當資料需要淸除，或是要儲存其他資料 的時候，就會自除外狀態520轉換爲無效狀態5〇〇(E-I轉 本紙張尺度適用中國國家標準（CNS)A4規格（210 X的7公楚） -----------f 裝—!^—----竣 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印製 466410 5312twf.doc/006 五、發明說明（A) 換）。 另外，當中央處理器內部之快取記憶體資料處於分享 狀態530的時候，若是對此資料有儲存的動作，就會轉換爲 修改狀態510(S-M轉換）。而若是資料需要淸除，要儲存其 他資料，或是其他保有這份資料之備份的快取記憶體要對 備份資料進行更動，則這一份資料就會轉換爲無效狀態 500(S-I轉換）。 而當中央處理器內部之快取記憶體資料處於修改狀態 510時，若是有從其他的快取記憶體傳來讀取信號，要讀取 此內部之快取記憶體之資料，則此資料會從修改狀態510 轉換爲擁有者狀態540(M-O轉換）。而若是資料需要淸除， 要儲存其他資料，或是其他的快取記憶體要對此資料進行 寫入動作時，就會使此資料自修改狀態510轉換爲無效狀態 500(M-I轉換）。此外，若是其他的快取記憶體要對此資料進 行讀取的動作，則此資料會從修改狀態510轉換爲分享狀態 530(M-S轉換）。 最後，當中央處理器內部之快取記憶體資料處於擁有 者狀態540時，若是對此資料有寫入的動作，則此資料的狀 態將轉換爲修改狀態510(〇-Μ轉換）。 接下來，介紹由週邊元件介面控制器傳來的探測讀取 命中信號(ProbeHitRd)。此探測讀取命中信號的產生’是當 資料緩衝區自記憶體內執行讀取動作的時候，就會藉由週 邊元件介面控制器發出此探測讀取命中信號到中央處理器 裡。而此探測讀取命中信號，包括了資料緩衝區到記憶體 — till—-----γ1--------訂·-------- (請先閱讀背面之沒恚事項再填寫本頁) 本紙張尺度適用中國國家標準（CNS)A4規格（210x297公釐） 經濟部智慧財產局員工消費合作社印製 一 ο ϋ 4 1 Ο 5312twf.doc/006 五、發明說明（Ρ ) 中讀取之資料在記憶體內對應的位址。 請合倂參照第2圖，第4圖以及第5圖，其顯示了根據本 發明之另外一個較佳實施例。其中，當中央處理器使用上 述的MOESI程序，且中央處理器的快取記憶體內部之資料 處於除外狀態520的時候，若是從週邊元件介面控制器傳來 一個探測讀取命中信號，且此信號中包含的位址與中央處 理器裡快取記憶體內部之資料的位址相同’則中央處理器 裡快取記憶體內部之資料就會從除外狀態520，經過E-S轉 換程序560而轉換成分享狀態530。 而當中央處理器使用MOESI程序’且中央處理器的快 取記憶體內部之資料處於修改狀態510時’若是從週邊元件 介面控制器傳來一個探測讀取命中信號’且此信號中包含 的位址與中央處理器裡快取記憶體內部之資料的位址相 同，則中央處理器裡快取記憶體內部之資料就會從修改狀 態510，經過M-0轉換程序550而轉換爲擁有者狀態540。 綜上所述，將本發明的優點略述如下。本發明藉由在 北橋晶片組中加入資料緩衝區，減少週邊裝置讀取資料時 所產生的延遲時間，增加週邊裝置以及週邊元件匯流排的 使用效率。此外，並藉由資料同步的方法，使得在減少延 遲時間之外，也能同時確保資料的正確性。 雖然本發明已以較佳實施例揭露如上，然其並非用以 限定本發明，任何熟習此技藝者，在不脫離本發明之精神 和範圍內，當可作各種之更動與潤飾，因此本發明之保護 範圍當視後附之申請專利範圍所界定者爲準。 本紙張尺度適用中國國家標準（CNS)A4規格（210 x 297公釐） -----------t--------訂---------族 (請先閲讀背面之注意事項再填寫本頁)Packing -------- Order --- II This paper size applies to the national standard (CNS) A4 specification (210x 297 mm) printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 4 6 64 1 Ο 5 312 twf .doc / 0 0 6 ^ _____B7________ V. Description of the invention (~) When the memory data string is read from the memory 30 and entered into the data buffer 25, the flow buffer 440 is used to include this memory in the data buffer 25 The volume data string 'that is, the buffered data portion of the buffered data string' is set to the clean unretrieved state 410. Next, when the above-mentioned buffered data part is in a clean and unretrieved state 410, if the corresponding address is written or read in the CPU bus 45 through the peripheral component interface controller 20 ′, Or the peripheral device interface controller 20 detects a write operation on the corresponding address in the peripheral component bus 15, and then sets the buffer data part to be unclean and unprocessed through flow 450 '. With state 430. In addition, when the buffered data part is in a clean unretrieved state 410> If the peripheral device 50 that requires the buffered data string reads the buffered data string from the data buffer 25, the peripheral component interface controller 20 passes the flow 460. Set the buffer data part to a clean and taken state 420. Next, when the buffered data portion is in an unclean and unretrieved state 430, if the peripheral device 50 that requires the buffered data string reads the buffered data string from the data buffer 25, the above-mentioned buffered data is transferred through the process 470 Partially set to emptiness 400. In addition, when the buffered data portion is in the clean and taken state 420, if the corresponding address is written or read in the CPU bus 45 through the peripheral component interface controller 20, Or when a write operation to the corresponding address is detected in the peripheral component bus 15 via the peripheral component interface controller 20, then the above-mentioned buffered data portion is set to an empty state 4 through flow 480 〇〇. ---- ^ I ----— 1 order ------- line (please read the precautions on the back before filling out this page) This paper size applies to China National Standard (CNS) A4 specifications (2) 0 X 297 公 餐) 5 3 12 twf. Doc / 0 0 6 Λ7 Π7 Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 5. Description of the invention (//) Next, please refer to FIG. 5, which shows a diagram according to the present invention In a preferred embodiment, the data inside the cache memory in a central processing unit is in accordance with the state change process of the MOESI protocol (MOESI Protocol). The method of operation of MOESI is briefly described below. The so-called MOESI includes a modified state (M, Modifed) 510, an owner state (0, 0 owner) 540, an excluded state (E, Exclusive) 520, a shared state (S, Shared) 530, and an invalid state (I , Invalid) 500. This MOESI program is used to maintain the consistency of data between the internal cache of the CPU and the external cache. Among them, when the cache memory inside the central processing unit is in an invalid state 500, if data is read from the memory and the other cache memory does not include the data, the internal memory of the central processing unit The cache memory will be transitioned to the exclusion state 520 (IE transition). In addition, if the data read from the memory has another backup in another cache memory ’, the cache memory inside the CPU will be converted to the shared state 530 (I-S transition). In addition, when a write miss occurs in the cache memory, the data will be automatically read into the memory 'and the state will be changed to the modified state 510 (I-M transition). When the cache memory data in the central processing unit is in the excluded state 520, if there is an action of modifying this data in the cache memory, it will be converted to the modified state 51 (E-M transition). And if it comes from the system requesting this piece of data that is in the excluded state 520 ’, this data will be converted to the shared state 530 (E-S transition). And when the data needs to be deleted or other data needs to be stored, it will be changed from the excluded state 520 to the invalid state 500 (EI converted to this paper size applies the Chinese National Standard (CNS) A4 specification (210 X 7mm) (Chu) ----------- f Pack —! ^ —---- End (Please read the notes on the back before filling out this page) Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs 466410 5312twf. doc / 006 V. Description of Invention (A) Change). In addition, when the cache memory data in the central processing unit is in the sharing state 530, if there is a storage action on this data, it will be changed to the modification state 510 (S-M transition). If the data needs to be erased, other data needs to be stored, or other backup caches that hold this data need to change the backup data, this data will be converted to the invalid state 500 (S-I conversion). When the cache memory data in the central processing unit is in the modified state 510, if there is a read signal transmitted from other cache memory, and the data in this internal cache memory is to be read, this data will be Transition from modified state 510 to owner state 540 (MO transition). If the data needs to be erased, other data needs to be stored, or other cache memory needs to write to this data, the data will be changed from the modified state 510 to the invalid state 500 (M-I transition). In addition, if other cache memory is to read this data, the data will be changed from the modified state 510 to the shared state 530 (M-S transition). Finally, when the cache memory data in the CPU is in the owner state 540, if there is a write operation on this data, the state of this data will be changed to the modified state 510 (0-M transition). Next, the probe read hit signal (ProbeHitRd) from the peripheral device interface controller is introduced. The generation of the detection and read hit signal ’is when the data buffer performs a read operation from the memory, the peripheral component interface controller sends out the detection and read hit signal to the central processing unit. And this detection reads the hit signal, including the data buffer to the memory — till —----- γ1 -------- order · -------- (Please read the恚 Please fill in this page again for this matter.) This paper size is in accordance with China National Standard (CNS) A4 (210x297 mm). Printed by the Consumer Cooperatives of the Intellectual Property Bureau of the Ministry of Economic Affairs. Ϋ 4 1 Ο 5312twf.doc / 006 5. Description of the invention ( (P) The corresponding address of the data read in the memory. Please refer to FIG. 2, FIG. 4 and FIG. 5, which show another preferred embodiment according to the present invention. Among them, when the CPU uses the above-mentioned MOESI program and the data in the cache memory of the CPU is in an excluded state 520, if a probe read hit signal is transmitted from the peripheral component interface controller, and this signal The address contained in it is the same as the address of the data in the cache memory in the CPU. Then the data in the cache memory in the CPU will be removed from the state 520 and shared by the ES conversion process 560. State 530. When the CPU uses the MOESI program 'and the data in the cache memory of the CPU is in a modified state 510,' If a probe read hit signal is transmitted from the peripheral component interface controller ', and the bit contained in this signal The address is the same as the data in the cache memory in the CPU. The data in the cache memory in the CPU will be changed from the modified state 510 to the owner state through the M-0 conversion process 550. 540. In summary, the advantages of the present invention are briefly described as follows. By adding a data buffer to the Northbridge chipset, the present invention reduces the delay time generated by peripheral devices when reading data, and increases the use efficiency of peripheral devices and peripheral component buses. In addition, by using the method of data synchronization, in addition to reducing the delay time, the accuracy of the data can be ensured at the same time. Although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications and retouches without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection shall be determined by the scope of the attached patent application. This paper size applies to China National Standard (CNS) A4 (210 x 297 mm) ----------- t -------- Order --------- Family (Please read the notes on the back before filling this page)