TW449784B - Alignment monitoring method - Google Patents

Abstract

The present invention discloses an alignment monitoring method, which uses the formation of simple structured step-type resistor to not only estimate the allowance of mis-alignment range between pairs of overlays but also further adjust each condition of the processes. If the method is applied between the metal wires, it can detect if there is a short circuit between metal wires and further determine the resolution of component process with significant effect and wide variety of application. The method can be applied to a semiconductor substrate to form an overlay pair on the semiconductor substrate, which comprises the following steps: providing n step-type resistors with resistance R, each having one end connected with the overlay pair, and the displacement between the overlay pairs being 0, 1, 2, ...n units respectively; and, measuring the resistance of those step-type resistance to determine the allowance of overlay mis-alignment range.

Description

449784 Case No. 891105.¾¾ V. Description of the invention (1) The present invention relates to a method for monitoring alignment, and in particular to a metal interconnection using laminated resistors on a stacked pair or on the same plane. Monitoring of misalignment tolerance. In the application of integrated circuits (ICs), materials such as conductors, semiconductors and insulation layers have been widely used, and thin film deposition (1; hin film deposition), lithography (Photolithography), and etching procedures (Etching) is the main semiconductor technology β, in which the thin film deposition is layered deposition of the above materials on the wafer surface, and the lithography process is to copy the desired element or circuit pattern and pass through In the etching step, the patterns are transferred to each layer on the surface of the wafer to be formed to form a semiconductor element, such as a transistor or a capacitor. Because the general lithography process must first coat a layer of photoresist on the surface of the wafer to be processed, and then hand it over to the exposure machine for exposure, and then develop the pattern after the layer is exposed with a developing solution. Connected. For semiconductor devices under the (mu 架构 1-level interconnects) three-dimensional architecture, it is necessary to repeat the lithography process in an overlay manner. Among them, in the process of stack alignment, it must be ensured that the alignment value of the current layer and the previous layer is within an allowable range. For example, each jacket of a semiconductor device has its own mask.

Therefore, each photomask must be designed right when designing W: there are * layers of alignment patterns available on the shoulder and targets for alignment measurement (tarwn, s ^ Λ class π days), It is usually used as an alignment check ^ β 7 (frame Couter frame) is called another layer, which represents the pattern left by the layer to be used for the alignment of m, and the inner frame is

0503-5076TWl.ptc Page 4 ^ 449784 V. Description of the Invention (2) When the pattern is defined by the layer, the two overlap each other for alignment check. The purpose of the alignment check is to verify the pros and cons of the alignment capability of the exposure machine. A wafer pattern generally consists of dozens of identical repeated exposure fields, and each exposure area is provided with a stack of targets (〇veriay target ) 'Analyze the alignment capability of the exposure machine based on the measured values of the X and Y directions of the exposure area by the monitor system. In the manufacturing process of the integrated circuit factory, the alignment capability of the exposure machine is mostly checked during the PM Workstation preventative maintenance. However, most of the inspection methods are to monitor the matching degree between the exposure machine and the test wafer. The problem is that the test wafer used as the alignment inspection of the exposure machine is generally provided by the mask manufacturer. It is not easy to maintain and cannot be inspected at any time. Therefore, if the exposure machine generates errors before the next monitoring, it will not be known 'and the process yield will be reduced. And as the component size decreases, in the sub-micron (subiiCron) integrated circuit manufacturing process, the shrinkage of the photoresist pattern after exposure is more serious, which results in poor pattern transfer. Overlay is becoming increasingly important. In view of this, the object of the present invention is to provide a method for alignment monitoring. Its principle and implementation method are simple, and its reliability (reliabiHty) is good. It can also be used as a laminated pair, metal interconnects, and interlayer windows. For misalignment or short break of contact t0 metai ... etc, the application range is wide. Judgment of the situation In order to achieve the purpose of the present invention, a stepped resistor is provided.

449784

Use resistance to connect a laminated pair with another wire, or people, to make a connection. “Make a step forward-measure its resistance value” w to determine whether its error is ^ 2 疋 is within its allowable range. This method is applicable to a semiconductor, and a stacked pair is formed on the semiconductor substrate. Step: Provide n step resistors with a resistance value of only, and-Di, the stacked pair is connected, and the The displacements between the stacked pairs are 0, z, 2 ... η = :: cabinet and the resistance values of these stepped resistors are measured, α judges the allowable value of the stacked "quasi-target range. The method of the present invention It can also be used to determine the minimum distance between metal interconnects. It is suitable for a semiconductor substrate, and a plurality of metal interconnects are formed on the semiconductor substrate, including the following steps: providing n step resistors to make it The two ends are respectively connected to two of the metal interconnects, and the stepped resistors have a resistance value r, and the distances between one end and the alignment points of the metal interconnects are 0, 1, 2 ... !! Units; and measure the resistance values of these stepped resistors to determine the allowable value of the minimum distance range between the metal interconnects. In order to make the above-mentioned objects, features, and advantages of the present invention more obvious and easier to understand, one of the following is enumerated. The preferred embodiment, and cooperates with The diagram is explained in detail as follows: Brief description of the diagram: FIG. 1 is a schematic diagram of the connection between a laminated pair and a stepped resistor according to the first embodiment of the present invention; FIG. 2 is a diagram when η resistors are connected in parallel Happening;

449784 V. Description of Invention Case No. 8911t) 5R? T ⑷ Modified stack 3 is a statistical chart of the measured resistance value versus layer alignment displacement according to the embodiment of the present invention; Figure 4 is along the first FIG. 5 is a structural cross-sectional view of the A-Λ cut plane; FIG. 5 is a structural cross-sectional view according to a second embodiment of the present invention; and FIG. 6 is a structural cross-sectional view according to a third embodiment of the present invention. Explanation of symbols 1 0, 50, 60 Silicon substrates 111, 112, 113, 114, 115, 511, 631, 632, 633 Step resistors' 1 2, 5 2 1, 5 2 2, 6 1 Element area 14, 531, 532 Insulating layer window laminated M3 metal wire C51 'contact window j 541, 5 42 metal wire |

I r Embodiment 1 1 First, please refer to FIG. 1, which shows the first according to the present invention! Schematic diagram of the connection between the laminated pair and the step resistor in the embodiment; as shown in the figure, the laminated pair Mn and the core + 1 are formed on a silicon substrate 10, where Mn can be

0503-5076TWFl.ptc Page 7 449784 V. Description of the invention (5) Various required metals such as aluminum and steel. In the lower part, the same order as the general process is + interlayer window (or contact window), metal layer 'dielectric layer, ... and other interconnect structures (not shown) to be electrically connected to the component area (not labeled) below. Sexual connection. A laddef resistor ill ~ 115 ′ is connected to one end of the metal ^, which has a resistance value of r. Above the stepped resistors 11 and 115 is the dielectric window%, which is a plan view as shown in FIG. 1 and is electrically connected to another metal layer thereon. It should be noted here that for ease of explanation, this embodiment takes five stepped resistors 111 to 115 as an example, and the metal Mn at one end of the stepped resistor i is completely aligned with the interlayer window. That is, the stacking alignment between the end of the stepped resistor and the interlayer window Vn (0verlay) is 0; the same, now suppose that the metal Mω at one end of the stepped resistor 114 is parallel to the interlayer window 1. If it is not completely aligned, the gap between them is determined as &, and the metal Mn at one end of the stepped resistor 5 is not completely aligned with the interlayer window, and the gap between them is determined as 仏. If the contact between the metal Mn at one end of the stepped resistor 114 and the interlayer window is valid, then based on the simple parallel resistance principle, the resistance value can be measured to be about R / 2. In the same state, we can connect more stepped resistors in parallel, for example, to n resistors. The condition is as shown in Figure 2. At the same time, the distance between the stack and the interlayer window is changed, such as sequentially a, 2a. , 3a, ..., and even na, as mentioned above, if the measured resistance value is R / n, the degree of ^ is still within the allowable range. In this way, you can further determine the maximum contact deviation # (shift) the distance, and make various adjustments to the process conditions for that distance. On the other hand, this method can be used to determine the position of the interlayer window.

449784 Five, "Explanation of the invention ^ The direction of the shift; for example, 'see the stepped resistor shown in Figure 1 丨 J 2, whose offsets are -a and -2a (ie, offset to the left)' Then, the resistance when the right deviation is R 'can be fixed as R'. The resistance when the left deviation is 2R. The range of the measured resistance value is used to determine whether the direction of the offset is left or right, so the direction of the offset is determined. Based on the above, the offset is made into a statistical chart of the measured resistance value, as shown in Figure 3. Therefore, in practice, it can be measured from the statistical chart. The resistance will infer the translation amount 'to judge the alignment of the interlayer window. Next, please refer to FIG. 4, which is a cross-sectional view of the structure along the AA cut plane in FIG. 1; in which “the element region 1 2 C is formed on the surface of the silicon substrate” (not shown in detail in the figure). A metal layer Mn having a defined pattern is sequentially formed thereon, and the metal layers Mn are connected in a stepped manner. On top of the metal layer & an insulating layer 14 is formed, such as an oxide layer, and a via window Vn is formed therein, which is filled with a metal such as tungsten, and another surface is formed on the surface of the oxide layer 14-a metal layer Mn + 1 such as Aluminum 'to enable the components in the component area to make external electrical contact. It should be noted here that the alignment system in this embodiment is a metal-to-interlayer window (Mn vs. Vn), so the material of Mn can be various metals, such as aluminum, steel, and the like. In addition, the form of the stepped resistor is not limited to the straight line shown in the first figure. In order to adjust the change of the resistance value, the stepped resistor can be made into a zigzag shape, a waveform, etc. as required. In this embodiment, The “Zhuang” shown in the figure is one of the examples, and it will not create the arrangement of this kind of resistance.

Page 9 449784 Case No. 89110553 V. Description of the invention (7) For the second embodiment, please refer to FIG. 5, which shows another kind of response made in accordance with the principle of the present invention, as shown in the figure. The surface forming material of 50 is drawn in the figure) 52 522 ′ and a stepped resistor 5 ^ 1 is formed thereon, for example, a wire 5n formed of polycrystalline silicon (poly) silicon. An insulating layer 53i, 532 is formed on the surface of the conducting wire 511, for example, a silicon oxide layer 5 formed by a PECVD method is used to form a contact window filled with metal tungsten. (C0ntact) C5i, ^ are connected to the metal wires 5 41, 5 4 2, for example, are chain wires. It should be noted here that the biggest difference between this embodiment and the first embodiment is that the stepped resistor alignment is the pair between the contact window and the polycrystalline silicon wire. Therefore, the resistor can be more dependent on the component. The design needs to form an insulating metal layer 'is not the form of a stepped resistor formed on the surface of all elements as shown in the first embodiment. __, such as 'the form of the stepped resistor is not limited to the line shown in Figure 1.' In order to adjust the change of the resistance value, the stepped resistor can be made into a zigzag shape, waveform ... The situation shown in the figure of this embodiment is just one example, and it does not limit the arrangement of such resistors. Embodiment 3 丨 In addition, this stepped resistor structure can also be applied to the same plane | judging the allowable value of the minimum distance between two adjacent metal lines (that is, determining whether the two metal wires are short-circuited); for example, t Referring to FIG. 6, a device region 61 (not shown in the figure) is formed on a silicon substrate 60, and the device region S 1 \

449784

V. Description of the invention (8) 6 The components in 1 are connected to the two metal wires M3 through a contact window (not shown). Then 'in order to determine whether a short circuit occurs between the two metal wires M3, a stepped resistor 631, 632' 633 is used for similar reasons, and we can connect multiple stepped resistors in parallel (the resistance value is R ), For example, the status of η resistors is also shown in Figure 2, and the distances between them are calculated, such as d, 2d '3d, ... and even nd in sequence. As mentioned above, if the measured resistance value is R When / n, it means that the distance between the two metal wires (spac i ng) is still within the allowable range, and it is not short-circuited. Therefore, * the distance between the metal wires can be reduced, and the lithography can be gradually improved. Resolution of photolithography. According to the present invention, with the simple structure of the stepped f but the misalignment between superimposed pairs can be estimated Uis_alignmein) F Fan's Garden \ Chengxu worthless, and further adjust the conditions of its process, if applied to gold detection: Whether there is a short circuit between the metal wires, the resolution of the process of breaking the parts is 'significantly effective' and its application range has been disclosed as above with a preferred embodiment, but it is not familiar with this skill by L 3Γ For example, * does not depart from the essence of the present invention = = can be modified and retouched 'Therefore, although the scope of protection of the present invention is defined by the scope of the attached patent application.

Claims (1)

丨 I Amendment No. 89110553 4497§4 VI. Application for Patent Scope 1. An alignment monitoring method is applicable to—on a semiconductor substrate, and a stacked pair is formed on the semiconductor substrate ', including the following steps: providing η having A stepped resistor with a resistance value of R, so that one end is connected to the laminated pair 'and the displacement between the laminated pair is 0, 1, 2 ... η units; and the resistance of the stepped resistors is measured. Value 'to determine the allowable value of the misalignment range of the stack. 2. The alignment monitoring method as described in item 1 of the scope of patent application, wherein when the measured resistance value of the stepped resistor is R / n, the misalignment distance of the table stack is still within its allowable range within. Among the n early bits of the table 3. The alignment monitoring method described in item 2 of the scope of patent application, the method for forming the stepped resistor includes the following steps: 1. forming a contact pad on the surface of the stacked pair; Forming an insulating layer on the surface of the contact pad; forming a first interlayer window and a second interlayer window to make electrical contact with the insulating layer contact pad; and forming a conductive layer to connect the first and second dielectric layers window. Medium 4. The controller as described in item 3 of the scope of the patent application, the controller 苴 The substance deposited in the second and second interlayer windows is tungsten, medium 5. As described in the scope of patent application, item 3 Alignment H The insulating layer is an oxide layer. Method 6. Alignment monitoring as described in item 3 of the patent application. The conductive layer is a polycrystalline silicon layer. Method ’its several metal interconnects: = 0503-5076TWF2.ptc Page 12 7. An alignment monitoring method, applicable to half of 449784 ___ plug number 89110553 month __§-ίΕί 6. Application scope of patent: Provide n step resistors with two ends respectively Connected to two of the metal interconnects, and the stepped resistors have a resistance value R, and the distances between the metal interconnects are 0, 1, 2 ... n units; and The threshold value of the step resistance is used to judge the allowable value of the minimum distance range between the metal interconnects. 8. The alignment monitoring method as described in item 7 of the scope of patent application, wherein when the resistance value of the stepped resistance measured is R / η, the minimum distance between the pair of metal interconnects is still within this range. Within tolerance. 9. The alignment monitoring method according to item 8 of the scope of patent application, wherein the method for forming the stepped resistor includes the following steps: forming a contact pad on the surface of the metal interconnect; forming an insulating layer on the surface; A surface of the contact pad; forming a first interlayer window and a second interlayer window in the insulating layer to make electrical contact with the contact pad; and forming a conductive layer to connect the first and second interlayer windows. 1 0. The alignment monitoring method described in item 9 of the scope of patent application, wherein the metal interconnects are located on the same plane. 11. The alignment monitoring method according to item 9 of the scope of patent application, wherein the insulating layer is an oxide layer. 12. The method for alignment monitoring as described in item 9 of the scope of the patent application, wherein 'the conductive layer is a multicrystalline fractured layer.