TW202512695A - Computational task processing method and device - Google Patents

Abstract

The invention provides a computing task processing method and device. The method comprises the steps that a computing task is received, the computing task comprises an original version field, and the following processing steps are executed: the original version field is modified to obtain a plurality of modified version fields; and based on the plurality of modified version fields, performing a hash operation on the calculation task to generate a plurality of intermediate state values, the plurality of intermediate state values being used for proof-of-work calculation. By means of the method, the calculation space of Hash operation is increased, the task receiving frequency is reduced, the purpose of improving the calculation efficiency is achieved, the calculation hardware area can be reduced, and the purpose of reducing power consumption is achieved.

Description

Computational task processing method and device

The present invention belongs to the field of computing processing technology, and specifically relates to a computing task processing method and device. This application claims priority to a Chinese patent application filed on September 8, 2023, with application number CN202311161624.7 and titled "Computing Task Processing Method and Device", the disclosure of which is incorporated herein by reference.

This section is intended to provide a background or context for the implementation of the invention described in the claims. The description herein is not admitted to be prior art by inclusion in this section.

Proof of Work (POW) is a consensus mechanism used by some cryptographic calculations. Its basic feature is that it requires a large number of hash operations to find a hash value that meets the conditions under a specific difficulty value, that is, block calculation. In essence, it performs a large number of SHA-256 operations on a given block header to solve a set of hash values that meet the expected difficulty. As shown in Figure 1, a block header used by an encryption algorithm includes a 4-byte version field; a 32-byte previous block hash; a 32-byte hash Merkle root field; a 4-byte timestamp; a 4-byte target value; and a 4-byte random number. The above block header is divided into two parts. The first part includes: a 4-byte version field; a 32-byte previous block hash and the first 28-byte hash Merkle root field (the first area of the hash Merkle root); the second part includes: the last 4 bytes of the hash Merkle root field (the second area of the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. The encryption algorithm stipulates that the first part needs to be calculated by SHA-256 first, and the result is the intermediate state value. Based on the intermediate state value and the second part, SHA-256 calculation is performed. Finally, based on the result, another SHA-256 calculation is performed to obtain a calculation result.

In traditional block calculations, the version field, the hash value of the previous block, and the difficulty target value are all fixed, so it is necessary to constantly modify the random number for calculation. However, the random number is only 4 bytes and can only be used to Therefore, it is usually necessary to modify the Merkle root to find a larger computing space. From the block header structure in Figure 1, it can be seen that the hash Merkle root is divided into two parts. The existing technology usually searches for block headers with the same last 4 bytes of multiple hash Merkle roots through a large number of hash collisions, so as to save computing efficiency to the greatest extent and thus achieve the purpose of reducing power consumption. However, it is necessary to perform hash collisions to find the same last 4 bytes of hash Merkle roots, which is costly and may not be supported.

Therefore, how to implement proof-of-work calculations in a less costly and power-efficient manner is an urgent problem to be solved.

In view of the problems existing in the above-mentioned prior art, a computing task processing method and device are proposed to save computing efficiency to the maximum extent, and can solve the problems of high computing cost and high power consumption of the above-mentioned proof of work.

The present invention provides the following solutions.

In a first aspect, a computing task processing method is provided, comprising:

Receive a calculation task, wherein the calculation task includes an original version field, and perform the following processing steps:

Modifying the original version field to obtain a plurality of modified version fields;

Based on the multiple modified version fields, a hash operation is performed on the computing task to generate multiple intermediate state values, and the multiple intermediate state values are used for proof of work calculation.

In some embodiments, the processing steps are repeatedly performed, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version field in the 1st to nth rounds of processing steps.

In some embodiments, it also includes:

Another computing task is received, and the processing step is executed based on the original version field of the another computing task.

In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of the modified version fields.

In some embodiments, the bits of the remaining fields are modified randomly or in a fixed order to modify the original version fields to obtain multiple modified version fields.

In some embodiments, the original version field is 32 bits and the remaining field is 16 bits.

In some embodiments, the computation task further includes a message field, wherein the message field includes a first region of a hash of a previous block and a hash Merkle root.

In some embodiments, it also includes:

Based on the intermediate state value, a plurality of sub-intermediate state values are obtained;

Outputting a serial data flow consisting of a plurality of sub-intermediate state values for use in proof of work calculation.

In some embodiments, based on the intermediate state value, it is split into multiple sub-intermediate state values.

In some embodiments, the intermediate state value is 256 bits, and the sub-intermediate state value is 32 bits.

In some embodiments, the computing task further includes a message field, and based on the plurality of modified version fields, performing a hash operation on the computing task to generate a plurality of intermediate state values includes:

The plurality of modified version fields are respectively combined with the message fields to obtain a plurality of first block fields, and based on the plurality of first block fields, a hash operation is performed to generate a plurality of the intermediate state values.

In some embodiments, each first block field is split into a plurality of sub-first block fields, and a hash operation is performed based on a serial data flow consisting of the plurality of sub-first block fields of each first block field to generate the intermediate state value.

In some embodiments, based on the sequence values of the plurality of modified version fields, each modified version field and the message field are combined to obtain a corresponding first block field.

In some embodiments, a pulse level corresponding to the sequence value is output, and in response to the pulse level, a modified version field corresponding to the sequence value and the message field are locked as the first block field.

In some embodiments, after performing a hash operation on the mth first block field to generate the intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field.

In some embodiments, it also includes:

A hash operation is performed based on the plurality of intermediate state values and a second block field of the computation task to obtain a proof of work; the second block field includes a second area of the hash Merkle root, a timestamp, a target value, and a random number.

In some embodiments, performing a hash operation based on the plurality of intermediate state values and the second block field of the computing task includes:

Performing a first expansion operation on the second block field to obtain first expansion data;

Performing a plurality of first compression operations based on the plurality of intermediate state values and the first expansion operation results to obtain a plurality of first compressed data;

Performing a plurality of second expansion operations based on a plurality of the first compressed data to obtain a plurality of the second expanded data;

A plurality of second compression operations are performed based on the plurality of second extended data to obtain the proof of work.

In some embodiments, the intermediate state value is generated in a high voltage region. After generating a plurality of the intermediate state values, the plurality of the intermediate state values are converted from the high voltage region to the low voltage region for proof of work calculation.

In some embodiments, the intermediate state value is generated in a top region of a wafer.

In some embodiments, the hashing operation is a SHA-256 operation.

In a second aspect, a computing task processing device is provided, comprising:

A receiving module, used for receiving a computing task, wherein the computing task includes an original version field;

A modification module modifies the original version field to obtain a plurality of modified version fields;

A computing module is used to perform a hash operation on the computing task based on the multiple modified version fields to generate multiple intermediate state values, and the multiple intermediate state values are used for proof of work calculation.

In some embodiments, the modification module is further used to repeatedly calculate and modify a plurality of the modified version fields.

In some embodiments, the receiving module is further used to receive a new computing task, and the modifying module is further used to modify the original version fields of the new computing task to obtain a plurality of modified version fields.

In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of the modified version fields.

In some embodiments, the computation task further includes a message field, wherein the message field includes a first region of a hash of a previous block and a hash Merkle root.

In some embodiments, a bit width conversion module is also included, which is used to split the intermediate state value of the first bit width generated by the calculation module into multiple sub-intermediate state values of the second bit width; the serial data flow composed of the multiple sub-intermediate state values is used for proof of work calculation.

In some embodiments, the computing task also includes a message field, the computing module includes a first register, the first register is used to store a first block field composed of a single modified version field and the message field combination, and the computing module performs a hash operation based on multiple first block fields to generate multiple intermediate state values.

In some embodiments, the computing module includes a shift register, which is used to split the first block field into multiple sub-first block fields, and the serial data flow composed of the multiple sub-first block fields is used to perform a hash operation to generate the intermediate state value.

In some embodiments, the calculation module includes a counter, which is used to generate a count value. The calculation module combines the modified version field corresponding to the count value and the message field to obtain the corresponding first block field based on the count value and the sequence values of the multiple modified version fields.

In some embodiments, the calculation module includes a level generation module, which generates a corresponding pulse level according to the count value, and the calculation module locks the modified version field corresponding to the count value and the message field as the first block field in response to the pulse level.

In some embodiments, the calculation module generates a completion signal when generating a single intermediate state value, the counter updates the count value in response to the completion signal, and restores the count value to the initial value after all the hash operations are performed on multiple first block fields.

In some embodiments, a proof-of-work calculation module is further included, which is used to perform hash operations based on multiple intermediate state values and a second block field of the computing task to obtain a proof of work; the second block field includes a second area of the hash Merkle root, a timestamp, a target value, and a random number.

In some embodiments, it also includes multiple second registers for receiving multiple intermediate state values; a first expander for performing a first expansion operation on the second block field to obtain first expanded data; multiple first compressors for performing multiple first compression operations based on the multiple intermediate state values and the first expansion operation results to obtain multiple first compressed data; multiple second expanders for performing multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data; multiple second compressors for performing multiple second compression operations based on the multiple second expanded data to obtain the workload proof.

In some embodiments, the computing module is disposed in the top layer area of the chip.

In some embodiments, a level converter is further included to convert the plurality of intermediate state values from a high voltage region to a low voltage region.

In some embodiments, the hashing operation is a SHA-256 operation.

At least one of the above technical solutions adopted in the embodiment of the present application can achieve the following beneficial effects: In the present embodiment, by adding the modification of the version field, the computing space of the hash operation is increased, the frequency of receiving tasks is reduced, and the purpose of improving computing efficiency is achieved. In addition, the present application does not require additional storage space to store the block header with the same 4 bytes after the hash Merkle root generated by the hash collision operation, nor does it require additional storage space to store the calculated intermediate state value. The multiple intermediate state values generated based on multiple modified version fields are pipelined and input to the next level for workload proof calculation, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

It should be understood that the above description is only an overview of the technical solution of the present invention, so that the technical means of the present invention can be more clearly understood and implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the following examples are given to illustrate the specific implementation of the present invention.

Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments described herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

In the description of the embodiments of the present application, it should be understood that terms such as "including" or "having" are intended to indicate the existence of features, numbers, steps, behaviors, components, parts or combinations thereof disclosed in this specification, and are not intended to exclude the possibility of the existence of one or more other features, numbers, steps, behaviors, components, parts or combinations thereof.

Unless otherwise specified, “/” means or. For example, A/B can mean A or B. The “and/or” in this article is only a description of the association relationship between related objects, indicating that three relationships can exist. For example, A and/or B can mean: A exists alone, A and B exist at the same time, and B exists alone.

The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, the meaning of "plurality" is two or more.

All codes in this application are exemplary, and those skilled in the art may think of various modifications based on the programming language used, specific needs, personal habits, etc. without departing from the concept of this application.

It should also be noted that, in the absence of conflict, the embodiments and features of the embodiments of the present invention can be combined with each other. The present invention will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

Referring to Figure 1, it can be seen from the block header structure that the hash Merkle root is divided into two parts, the first 28 bytes of the Head (the first area of the hash Merkle root), and the last 4 bytes of the Tail (the second area of the hash Merkle root). The calculation of the intermediate state value depends only on the first 512 bits of the block header. The traditional method is to find multiple Merkle root candidate values with the Head part changed and the Tail part unchanged through hash collision, and then calculate the Mid based on this for subsequent calculations. This can increase the computing space of SHA-256, but changing the Head part of the Merkle root will bring a surge in the amount of calculation. Therefore, if other fields in the first part can be changed to traverse the values therein, more computing space may be available.

The first part of the block header includes the version field, the previous block hash, and the first 28 bytes of the Merkle root. The 4-byte version field is 32 bits in total, of which the first 3 bits are fixed, and the remaining bits are used for voting during technical upgrades or soft forks. However, in actual applications, there will not be so many soft fork votes at the same time. Therefore, some of these bits can be ignored by modifying the node software, so that these bits can be used for general use without issuing error warnings during soft forks. Refer to the BIP320 protocol, which stipulates that the 13-28-bit space of the version field can be occupied, that is, 0x1fffe000. If this 16-bit space can be used, then there will be more The next computer will receive the same task and then proceed Rounds of calculations, and each round of calculations can be performed The operation of traversing the random number, that is, Based on this, this application uses the version field in the first part of the block header as a modification item.

FIG2 is a flow chart of a computing task processing method according to an embodiment of the present application. As shown in FIG2, the method provided by the present embodiment may include the following steps:

Step 210: receiving a calculation task, the calculation task including an original version field; then, executing the following processing steps:

Step 220: modify the original version field to obtain multiple modified version fields;

Step 230: Based on the multiple modified version fields, perform a hash operation on the computing task to generate multiple intermediate state values, and the multiple intermediate state values are used for workload proof calculation.

In the above scheme, after the front end of the computing device receives the computing task, it can use software to modify the configuration of the original version field to obtain multiple modified version fields. The back end of the computing device, namely the computing chip, can receive multiple modified version fields through the APB bus. The computing task also includes a message field. Multiple modified version fields and message fields are combined to obtain multiple first blocks. The computing chip performs a hash operation on them to obtain an intermediate state value. The intermediate state value is output to the next level for subsequent hash operations, and finally the proof of work is obtained.

The hash operation includes a pre-hash operation, which includes an expansion operation and a compression operation. The data used in the expansion operation is the first 512-bit field of the block header, including the modified version field and the message field. The message field includes the first area of the pre-block hash and the hash Merkle root. The data used in the compression operation is the 256-bit constant field and the output of the expansion operation, and the final output is the intermediate state value.

Referring to Figure 3, the generation of the intermediate state value can be done in the top layer area of the computing chip. The top layer area can also be understood as the main control area of the computing chip. The top layer area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The computing core uses the intermediate state value and the second part of the block header, that is, the last 4 bytes of the hashed Merkle root field (the second area of the hashed Merkle root), a 4-byte timestamp, a 4-byte difficulty target value, and a 4-byte random number to complete the proof of work calculation. The top layer works in the high voltage region and can issue operation instructions to the operation region and receive data from the operation region. The operation region works in the low voltage region and works at a high frequency to calculate the random number generated. times the computational space.

In this embodiment, by adding the modification of the version field, the computing space of the hash operation is increased, the frequency of receiving tasks is reduced, and the purpose of improving computing efficiency is achieved. In addition, this application does not require additional storage space to store the block header with the same 4 bytes after the hash Merkle root generated by the hash collision operation, nor does it require additional storage space to store the calculated intermediate state value. Based on multiple modified version fields, multiple intermediate state values are pipelined and input to the next level for workload proof calculation, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

In some embodiments, the processing steps are repeatedly performed, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version field in the 1st to nth rounds of processing steps.

In the above scheme, after receiving a calculation task, the modification space of the original version field is 16 bits, which can be In each round of operation, multiple modified version fields are generated, and multiple intermediate state values are generated accordingly. Then, the next round of original version fields are modified to obtain new modified version fields.

In some embodiments, the method further includes: receiving another computing task, and executing a processing step based on the original version field of the other computing task.

In the above scheme, the computational space of the computational task is After the calculation is completed, or after the calculation task generates the target result, or after the previous round of calculation tasks is stopped, the front end of the computing device receives a new calculation task, and then modifies the original version field of the new calculation task to obtain multiple modified version fields, and then generates intermediate status values based on the modified version fields, and finally performs proof of work calculation based on the intermediate status values.

In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

In the above scheme, the 4-byte version field has a total of 32 bits, of which the first 3 bits are fixed, i.e., fixed fields, and the remaining bits are used for voting during technology upgrades or soft forks, i.e., soft fork voting fields. However, in actual applications, there will not be so many soft fork votes at the same time. Therefore, some of these bits can be ignored by modifying the node software, so that these bits, i.e., the remaining fields, can be used for general use without issuing error warnings during soft forks. Referring to the BIP320 protocol, it is stipulated that the 13-28 bits of the version field can be occupied, i.e., 0x1fffe000.

In some embodiments, the bits of the remaining fields are modified in a random or fixed order to modify the original version field to obtain multiple modified version fields.

In the above scheme, the bits of the remaining field occupy 13-28 bits of the version field, and each bit can be modified to 0 or 1 in a random or fixed order, thereby modifying the original version field to obtain multiple modified version fields.

In some embodiments, the original version field is 32 bits and the remaining fields are 16 bits.

In the above scheme, the original version field is the first 4 sections of the block header, that is, 32 bits, and the bits of the remaining fields occupy 13-28 bits of the version field. Modifications.

In some embodiments, the computation task further includes a message field, the message field including the first region of the previous block hash and the hash Merkle root.

In the above scheme, the calculation task is the block header, which includes the first part, which includes: a 4-byte version field; a 32-byte pre-block hash and the first 28-byte hash Merkle root field (the first zone of the hash Merkle root), and the modified version field and the message field are combined to form the first block field. The first block field is used to perform the pre-hash operation to obtain the intermediate state value.

In some embodiments, it also includes:

Based on the intermediate state value, multiple sub-intermediate state values are obtained;

Output the serial data flow consisting of multiple sub-intermediate state values for proof-of-work calculation.

In the above scheme, the pre-hashing operation occurs in the high voltage region, and the subsequent hashing operation occurs in the low voltage region. The data bit width of the generated intermediate state value can be 256 bits. In order to reduce the wiring bit width requirement from the high voltage region to the low voltage region, a bit width conversion operation can be used.

In some embodiments, based on the intermediate state value, it is split into multiple sub-intermediate state values.

In the above scheme, the intermediate state value is evenly split from the lowest bit to the highest bit, and finally a plurality of sub-intermediate state values of the same length are obtained.

In some embodiments, the intermediate state value is 256 bits and the sub-intermediate state value is 64 bits.

In the above scheme, each intermediate state value of the output 256 bits can be divided into 64-bit sub-intermediate state values, which are defined as {mid＜n＞_3, mid＜n＞_2, mid＜n＞_1, mid＜n＞_0} (n=0,1,2,3), where n is the identifier of the intermediate state value. Each intermediate state value is transmitted in sequence according to the 64-bit data bit width through 4 loops. If there are 4 intermediate state values, they are transmitted to the next level for use in a serial data flow similar to the sequence shown in Figure 4 according to the sequence of the identifiers of the intermediate state values.

In some embodiments, the computing task further includes a message field, and based on the multiple modified version fields, a hash operation is performed on the computing task to generate multiple intermediate state values, including:

The plurality of modified version fields are respectively combined with the message field to obtain a plurality of first block fields, and a hash operation is performed based on the plurality of first block fields to generate a plurality of intermediate state values.

In the above scheme, the first block field is the first part of the block header, which includes: a 4-byte version field; a 32-byte pre-block hash and a 28-byte hash Merkle root field (the first area of the hash Merkle root), and the first block field is 512 bits. Each time multiple modified version fields are received, each modified version field needs to be mapped to the message field combination to form the first block field, and then a pre-hashed operation is performed to generate an intermediate state value.

In some embodiments, each first block field is split into a plurality of sub-first block fields, and a hash operation is performed based on a serial data flow consisting of the plurality of sub-first block fields of each first block field to generate an intermediate state value.

In the above scheme, the first block field can be 512 bits. In order to meet the routing width requirements and facilitate the top layer of the computing chip to perform pre-hashing operations, the data is split into 32-bit fine sub-block fields for SHA-256 pipeline calculations. After 64 rounds of expansion and compression operations, the intermediate state value is finally generated.

In some embodiments, based on the sequence values of multiple modified version fields, each modified version field and the message field are combined to obtain the corresponding first block field.

In the above scheme, multiple modified version fields have an identifier, i.e., a sequence value, when generated. Each modified version field is combined with the message field according to the sequence value to form the first block field, and then a pre-hashed operation is performed to generate an intermediate state value.

In some embodiments, a pulse level corresponding to a sequence value is output, and in response to the pulse level, a modified version field and a message field corresponding to the sequence value are locked as first block fields.

In the above scheme, the pulse level corresponding to the sequence value is output, and then the corresponding modified version field and message field are latched to form the first block field for performing the prefix hash operation.

In some embodiments, after performing a hash operation on the mth first block field to generate an intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field.

In the above scheme, in order to save the hardware circuit area of the computing chip, only one pre-hashing operation unit is set to perform a single expansion operation and compression operation, so only a single first block field operation can be performed each time. After generating a single intermediate state value, the next first block field is locked to perform the next pre-hashing operation. The multiple intermediate state values generated in sequence form a serial pipeline data that can be directly given to the next level for workload proof calculation without storage, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

In some embodiments, it also includes:

A hash operation is performed based on multiple intermediate state values and the second block field of the computational task to obtain a proof of work; the second block field includes the second block of the hash Merkle root, a timestamp, a target value, and a random number.

In the above scheme, the second part of the block header, i.e., the second block field, includes: the last 4 bytes of the hash Merkle root field (the second area of the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. The final generation of the proof of work occurs in multiple computing areas of the computing chip, and each computing area performs two hash operations, including the first hash operation and the second hash operation.

In some embodiments, referring to FIG. 5 , performing a hash operation based on a plurality of intermediate state values and a second block field of a computing task includes:

Step 510: Perform a first expansion operation on the second block field to obtain first expansion data;

Step 520: performing a plurality of first compression operations based on the plurality of intermediate state values, the first expansion operation result and the second block field to obtain a plurality of first compressed data;

Step 530: performing a plurality of second expansion operations based on the plurality of first compressed data to obtain a plurality of second expanded data;

Step 540: Perform multiple second compression operations based on the multiple second extended data to obtain a workload proof.

In the above scheme, the first hash operation includes a first expansion operation and multiple first compression operations, and the second hash operation includes multiple second expansion operations and multiple second compression operations.

When executing the first hash operation, a single operation area, i.e., an operation core, includes a single first expander and multiple first compressors. The first expander uses the second block field to perform the first expansion operation to obtain the first expansion data, and multiple first compressors can share the first expansion data of the single expander. Multiple first compressors correspond to multiple intermediate state values and the second block field to perform multiple first compression operations to obtain multiple first compressed data. Because multiple first expanders do not need to be arranged and do not need to correspond one-to-one with multiple first compressors, the layout area of the operation core is saved, and power consumption is further reduced.

When executing the second hash operation, a single operation area, i.e., an operation core, includes multiple second expanders and multiple second compressors. The multiple second expanders perform multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data. The multiple second compressors perform multiple second compression operations based on the multiple second expanded data and a 256-bit constant field to obtain proof of work.

Each time a round of the first hash operation and the second hash operation is completed, in the next round of hash operation, the random number in the second block field must be The computation space of the block header is switched to another one to complete the proof-of-work calculation.

In some embodiments, the intermediate state values are generated in the top layer area of the chip, and the intermediate state values are generated in the high voltage area. After generating multiple intermediate state values, the multiple intermediate state values are converted from the high voltage area to the low voltage area for workload proof calculation.

In the above scheme, the generation of the intermediate state value can be done in the top layer area of the computing chip. The top layer area can also be understood as the main control area of the computing chip. The top layer area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top layer area works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area and the computing area works at a high frequency to calculate the random number formation. The top layer performs pre-hashing operations to generate intermediate state values for multiple operation regions. The first and second hash operations are performed in the computational space of the operation area. Therefore, the computational area works in a low voltage and high frequency environment to speed up the computational efficiency. During the computational area traversal, the top layer area does not have to keep calculating and generating intermediate state values. Instead, it waits until the computational area is traversed before setting the intermediate state values in the version field. The next round of intermediate state values is generated within the modifiable range, so the top layer works in a high voltage and low frequency environment to complete the pre-hashing operation. Converting the intermediate state value from the high voltage area to the low voltage area is conducive to high-speed calculation in the calculation area and improves calculation efficiency.

In some embodiments, the hash operation is a SHA-256 operation.

In the above scheme, the hash operation is a SHA operation, specifically a SHA-256 operation. This scheme can also be applied to the SHA-1, SHA-2 and RIPEMD families, which all use schemes similar to SHA-256. Therefore, if the variable domain can be increased, the number of tasks to accept inputs will be reduced, and the computational efficiency can also be improved.

Based on the same technical concept, the embodiment of the present invention also provides a computing task processing device for executing the computing task processing method provided by any of the above embodiments. FIG6 is a schematic diagram of the structure of a computing task processing device provided by the embodiment of the present invention.

The computing task processing device comprises:

The receiving module 610 is used to receive a computing task, wherein the computing task includes an original version field;

A modification module 620 modifies the original version field to obtain a plurality of modified version fields;

The computing module 630 is used to perform hash operations on the computing tasks based on multiple modified version fields to generate multiple intermediate state values, and the multiple intermediate state values are used for workload proof calculation.

In the above scheme, the receiving module 610 and the modifying module 620 can be set at the front end of the computing device, and the original version field can be modified and configured using software to obtain multiple modified version fields. The computing module 630 can be set at the back end of the computing device, specifically the top layer area of the computing chip, and the top layer area can also be understood as the main control area of the computing chip. The computing module 630 is used to complete the pre-hashing operation to generate the intermediate state value, and the generated intermediate state value is pipelined to multiple computing areas of the computing chip for workload proof calculation. Of course, the receiving module 610 and the modifying module 620 can also be set in the computing chip, and the computing module 630 can also be set at the front end of the computing device, and this application does not make specific restrictions on this. The receiving module 610 and the modifying module 620 can be arranged at the front end of the computing device, and the computing module 630 can be arranged at the back end of the computing device, which is just one of the preferred embodiments.

In this embodiment, by adding the modification of the version field, the computing space of the hash operation is increased, the frequency of receiving tasks is reduced, and the purpose of improving computing efficiency is achieved. In addition, this application does not require additional storage space to store the block header with the same 4 bytes after the hash Merkle root generated by the hash collision operation, nor does it require additional storage space to store the calculated intermediate state value. Based on multiple modified version fields, multiple intermediate state values are pipelined and input to the next level for workload proof calculation, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

In some embodiments, the modification module 630 is further configured to repeatedly modify multiple revision fields.

In the above scheme, in a computing chip, the top layer area of the computing chip receives multiple modified version fields in each round, and generates multiple intermediate state values accordingly. The generated intermediate state values are pipelined to all or part of the computing areas of the computing chip for workload proof calculation. The computing areas are traversed. Then, the top layer of the computing chip receives the next round of multiple modified version fields, and the cycle continues, continuously generating intermediate state values and transmitting them to the computing area of the computing chip until the computing task is completed or stopped.

In some embodiments, the receiving module 620 is further used to receive a new computing task, and the modifying module 620 is further used to modify the original version fields of the new computing task to obtain multiple modified version fields.

In the above scheme, the computational space of the computational task is After the calculation is completed, or after the calculation task generates the target result, or after the previous round of calculation tasks is stopped, the receiving module 610 receives a new calculation task, the modifying module 620 modifies the original version fields of the new calculation task to obtain multiple modified version fields, and the calculation module 630 generates an intermediate state value based on the modified version fields, and finally performs proof of work calculation based on the intermediate state values.

In some embodiments, the original version field includes a fixed field, a soft fork voting field, and a remaining field, and the remaining field is used to modify the original version field to obtain multiple modified version fields.

In the above scheme, the 4-byte version field has a total of 32 bits, of which the first 3 bits are fixed, i.e., fixed fields, and the remaining bits are used for voting during technology upgrades or soft forks, i.e., soft fork voting fields. However, in actual applications, there will not be so many soft fork votes at the same time. Therefore, some of these bits can be ignored by modifying the node software, so that these bits, i.e., the remaining fields, can be used for general use without issuing error warnings during soft forks. Referring to the BIP320 protocol, it is stipulated that the 13-28 bits of the version field can be occupied, i.e., 0x1fffe000. The bits of the remaining fields occupy 13-28 bits of the version field. Each bit can be modified to 0 or 1 in a random or fixed order, thereby modifying the original version field to obtain multiple modified version fields.

In some embodiments, the computation task further includes a message field, the message field including the first region of the previous block hash and the hash Merkle root.

In the above scheme, the calculation task is the block header, and the block header includes the first part, which includes: a 4-byte version field; a 32-byte front block hash and the first 28-byte hash Merkle root field (the first zone of the hash Merkle root), and the modified version field and the message field are combined to form the first block field. The first block field is used by the calculation module to perform the pre-hash operation to obtain the intermediate state value.

In some embodiments, a bit width conversion module is also included, which is used to split the intermediate state value of the first bit width generated by the calculation module into multiple sub-intermediate state values of the second bit width; the serial data flow composed of the multiple sub-intermediate state values is used for proof of work calculation.

In the above scheme, the pre-hashing operation occurs in the high voltage region, and the subsequent hashing operation occurs in the low voltage region. The data bit width of the generated intermediate state value can be 256 bits. In order to reduce the wiring bit width requirement from the high voltage region to the low voltage region, a bit width conversion operation can be used. The bit width conversion module can be used to divide each 256-bit intermediate state value of the output into 64-bit sub-intermediate state values, which are defined as {mid＜n＞_3, mid＜n＞_2, mid＜n＞_1, mid＜n＞_0} (n=0,1,2,3), where n is the identifier of the intermediate state value. Each intermediate state value is transmitted in sequence according to the 64-bit data bit width through 4 loops. If there are 4 intermediate state values, they are transmitted to the next level for use in a serial data flow similar to the sequence shown in Figure 4 according to the sequence of the intermediate state value identifiers.

In some embodiments, the computing task also includes a message field. Referring to FIG. 7 , the computing module 630 includes a first latch 631, and the first latch 631 is used to store a first block field composed of a single modified version field and a message field. The computing module 630 performs a hash operation based on multiple first block fields to generate multiple intermediate state values.

In the above scheme, the first block field is the first part of the block header, and the first part includes: a 4-byte version field; a 32-byte front block hash and a first 28-byte hash Merkle root field (the first area of the hash Merkle root), and the first block field is 512 bits. Each time multiple modified version fields are received, the first latch 631 needs to correspond each modified version field to the message field combination to form the first block field, and then perform a pre-hash operation to generate an intermediate state value.

In some embodiments, still referring to FIG. 7 , the computing module 630 includes a shift register 632, and the shift register 632 is used to split the first block field into a plurality of sub-first block fields, and the serial data flow formed by the plurality of sub-first block fields is used to perform a hash operation to generate an intermediate state value.

In the above scheme, the first block field can be 512 bits. In order to meet the routing width requirements and facilitate the top layer of the computing chip to perform pre-hashing operations, the data is split into 32-bit sub-block fields using shift registers for SHA-256 pipeline calculations. After 64 rounds of expansion and compression operations, the intermediate state value is finally generated.

In some embodiments, still referring to FIG. 7 , the computing module 630 includes a counter 633, which is used to generate a count value, so that the computing module 630 combines the modified version field and the message field corresponding to the count value to obtain the corresponding first block field based on the count value and the sequence values of multiple modified version fields.

In the above scheme, multiple modified version fields have an identification or sequence value when generated, and the first latch 631 responds to the count value. Each modified version field is combined with the message field to form a first block field according to the sequence value, and then a pre-hash operation is performed to generate an intermediate state value.

In some embodiments, still referring to FIG. 7 , the calculation module 630 includes a level generation module 634, which generates a corresponding pulse level according to the count value, and the calculation module locks the modified version field and the message field corresponding to the count value as the first block field in response to the pulse level.

In the above scheme, the level generation module 634 outputs a pulse level corresponding to the count value according to the count value output by the counter 633, and the pulse level corresponds to the sequence value. Then the first latch 631 latches the corresponding modified version field and the message field to form the first block field, which is used to perform the pre-hash operation.

It can be understood that a latch is a storage unit circuit that is sensitive to pulse levels and can change state under the action of a specific input pulse level. Latching is to temporarily store a signal to maintain a certain level state. In this embodiment, multiple count values of the counter 633 are associated with multiple pulse levels, and the count value itself and the sequence value of the version field also have a one-to-one correspondence, and then the version field and message field corresponding to the current count value can be latched as the first block field using the generated pulse level. This embodiment sets the coordinated operation of the latch and the counter, so that the first block field corresponding to multiple version fields can be generated in an orderly and pipelined manner.

In some embodiments, the calculation module 630 generates a completion signal when generating a single intermediate state value, and the counter 633 updates the count value in response to the completion signal, and restores the count value to the initial value after all the hash operations are performed on the multiple first block fields.

In the above scheme, in order to save the hardware circuit area of the computing chip, the computing module only sets up one pre-hashing operation unit to perform a single expansion operation and compression operation, so only a single first block field operation can be performed each time. After generating a single intermediate state value, it starts to lock the next first block field to perform the next pre-hashing operation. After the calculation module receives multiple modified version fields and message fields, the value of the counter 633 is 0. At this time, the first latch 631 locks the modified version fields and message fields with a sequence value of 0. The pre-hash operation unit generates the 0th intermediate state value and generates a completion signal. The counter 633 updates the count value to 1, and the first latch 631 starts to lock the modified version fields and message fields with a sequence value of 1. After all the multiple first block fields are hashed, the count value of the counter 633 is restored to the initial value, and the calculation module waits to receive the next round of multiple modified version fields and message fields. The multiple intermediate state values generated in sequence form a serial pipeline data that can be directly given to the next level for workload proof calculation without storage, thereby reducing the computing hardware area and achieving the purpose of reducing power consumption.

In some embodiments, a proof-of-work calculation module is also included, which is used to perform hash operations based on multiple intermediate state values and a second block field of the computational task to obtain a proof of work; the second block field includes a second block of a hash Merkle root, a timestamp, a target value, and a random number.

In the above scheme, the second part of the block header, i.e., the second block field, includes: the last 4 bytes of the hash Merkle root field (the second area of the hash Merkle root); a 4-byte timestamp; a 4-byte difficulty target value; and a 4-byte random number. The final generation of the proof of work occurs in multiple computing areas of the computing chip, i.e., the proof of work computing module, also known as the computing core. Each computing core must perform two hash operations, including the first hash operation and the second hash operation.

In some embodiments, it also includes multiple second registers for receiving multiple intermediate state values; a first expander for performing a first expansion operation on a second block field to obtain first expanded data; multiple first compressors for performing multiple first compression operations based on the multiple intermediate state values and the first expansion operation results and the second block field to obtain multiple first compressed data; multiple second expanders for performing multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data; multiple second compressors for performing multiple second compression operations based on the multiple second expanded data to obtain proof of work.

Referring to FIG8 , the workload proof computing module, i.e., the computing core, includes: a plurality of second registers arranged in parallel, such as second register_0, second register_1, second register_2, and second register_3; a plurality of first compressors arranged in parallel, such as first compressor_0, first compressor_1, first compressor_2, and first compressor_3, wherein the plurality of first compressors are electrically connected to the plurality of second registers in a one-to-one correspondence; a first expander , multiple first compressors are electrically connected to the first expander in common; multiple second expanders arranged in parallel, such as second expander_0, second expander_1, second expander_2, and second expander_3, are electrically connected to the multiple first compressors in a one-to-one correspondence; multiple second compressors, such as second compressor_0, second compressor_1, second compressor_2, and second compressor_3, are electrically connected to the multiple second expanders in a one-to-one correspondence.

The first latch and the second latch in this embodiment refer to electronic devices with a latch function, and are not limited to dedicated latches. Therefore, other devices with a latch function can also be used as the first latch or the second latch, such as a register.

In the above scheme, the first hash operation includes a first expansion operation and multiple first compression operations, and the second hash operation includes multiple second expansion operations and multiple second compression operations.

When executing the first hash operation, a single operation area, i.e., an operation core, includes a single first expander and multiple first compressors. The first expander uses the second block field to perform the first expansion operation to obtain the first expansion data, and multiple first compressors can share the first expansion data of the single expander. Multiple first compressors correspond to multiple intermediate state values and the second block field to perform multiple first compression operations to obtain multiple first compressed data. Because multiple first expanders do not need to be arranged to correspond one to one with multiple first compressors, the layout area of the operation core is saved, and power consumption is further reduced.

When executing the second hash operation, a single operation area, i.e., an operation core, includes multiple second expanders and multiple second compressors. The multiple second expanders perform multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data. The multiple second compressors perform multiple second compression operations based on the multiple second expanded data and a 256-bit constant field to obtain proof of work.

Each time a round of the first hash operation and the second hash operation is completed, in the next round of hash operation, the random number in the second block field must be The computation space of the block header is switched to another one to complete the proof-of-work calculation.

In some embodiments, the computing module is disposed in the top layer region of the chip and further includes a level converter for converting a plurality of intermediate state values from a high voltage region to a low voltage region.

In the above scheme, the generation of the intermediate state value can be done in the top layer area of the computing chip. The top layer area can also be understood as the main control area of the computing chip. The top layer area works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top layer area works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area and the computing area works at a high frequency to calculate the random number formation. The top layer performs pre-hashing operations to generate intermediate state values for multiple operation regions. The first and second hash operations are performed in the computational space of the operation area. Therefore, the computational area works in a low voltage and high frequency environment to speed up the computational efficiency. During the computational area traversal, the top layer area does not have to keep calculating and generating intermediate state values. Instead, it waits until the computational area is traversed before setting the intermediate state values in the version field. The next round of intermediate state values is generated within the modifiable range, so the top layer works in a high voltage and low frequency environment to complete the pre-hashing operation. The intermediate state value is converted from the high voltage area to the low voltage area using a level converter, which is conducive to high-speed calculation in the calculation area and improves calculation efficiency.

In some embodiments, the hash operation is a SHA-256 operation.

The following is one specific embodiment of this application:

The receiving module and the modifying module can be arranged at the front end of the computing device, and the software can be used to modify the configuration of the original version fields to obtain multiple modified version fields. The computing module can be arranged at the back end of the computing device, specifically the top layer area of the computing chip, and the top layer area can also be understood as the main control area of the computing chip.

The computing module receives multiple revision fields and message fields of the software configuration via the APB bus, such as 4 revision fields, and the message field includes the first 28 bytes of the previous block hash value and the hash Merkle root. Since there are 4 revision fields, a set of 2-bit counters can be maintained, and the 2-bit counter has 4 count values {0, 1, 2, 3}, wherein the 4 count values of the counter {0, 1, 2, 3} can correspond one-to-one to the sequence values of the 4 revision fields.

Furthermore, according to the current count value of the counter, the modified version field and the message field corresponding to the current count value can be spliced and locked using the first register, thereby obtaining the first block field {modified version field, message field} corresponding to the current count value, that is, the first 512 bits of the block header shown in Figure 1.

Then, after obtaining the first block field, the locked first block field can be used for pre-hashing operations. In order to meet the routing width requirements and facilitate the top layer of the computing chip to perform pre-hashing operations, the data is split into 32-bit sub-block fields using shift registers for use in SHA-256 pipeline calculations. Of course, the sub-block fields are not limited to 32 bits, but can also be any other bits.

Specifically, the expansion operation and compression operation may be performed repeatedly on the first block field to obtain a 256-bit intermediate state value Mid and generate a completion signal. The 256-bit intermediate state value Mid will be immediately output to the next-level computing core for subsequent shuffling operations. The 256-bit intermediate state value may be placed on the intermediate state value bus and output to the next-level computing core through the intermediate state value bus.

The completion signal is output to the counter, and the counter responds to the completion signal by adding 1 to the current count value; thereafter, according to the updated current count value of the counter, the first block field corresponding to the next modification version field is locked and the pre-hashing operation unit is used to perform the hash operation. The loop repeatedly calculates multiple intermediate state values until the technical value of the counter overflows, which means that the first block fields corresponding to the four modification version fields have been calculated.

See Figure 4. In this way, the 256-bit intermediate state values corresponding to the four version fields can be sequentially generated in the repeated calculation process, such as Mid (0) [255:0], Mid (1) [255:0], Mid (2) [255:0], Mid (3) [255:0]. After the calculation of the multiple intermediate state values of the previous round is completed, the counter is cleared. Alternatively, the counter can be cleared when a new calculation task arrives, thereby recalculating the new task.

The pre-hashing operation occurs in the high voltage region, and the subsequent hashing operation occurs in the low voltage region. The data bit width of the generated intermediate state value can be 256 bits. In order to reduce the routing bit width requirement from the high voltage region to the low voltage region, a bit width conversion operation can be used. Each 256-bit output intermediate state value can be divided into 64-bit sub-intermediate state values, which are defined as {mid＜n＞_3, mid＜n＞_2, mid＜n＞_1, mid＜n＞_0} (n=0,1,2,3), where n is the identifier of the intermediate state value. Each intermediate state value is transmitted in sequence according to the 64-bit data bit width through 4 loops. If there are 4 intermediate state values, they are transmitted to the next-level computing core for use in a serial data flow similar to the sequence shown in Figure 4 according to the sequence of the intermediate state value identifiers. Of course, the sub-intermediate state value is not limited to 64 bits, but can also be any other bit.

The generation of intermediate state values can be done in the top layer of the computing chip. The top layer can also be understood as the main control area of the computing chip. The top layer works in the high voltage area and can issue computing instructions to the computing area. The computing chip also includes multiple computing areas, each of which can be understood as the computing core of the computing chip. The top layer works in the high voltage area and can issue computing instructions to the computing area and receive data from the computing area; the computing area works in the low voltage area and the high frequency of the computing area is used to calculate the random number formation. The level converter is used to convert the intermediate state value from the high voltage area to the low voltage area, which is conducive to high-speed calculation in the calculation area and improves the calculation efficiency.

The next-level computing core receives the transmitted serial data flow, for example, the serial data flow is a 64-bit serial data flow shown in FIG. 4, and uses a plurality of second latches to restore the serial data flow with the second bit width to a plurality of intermediate state values of the first bit width, and respectively inputs them into a plurality of first compressors, for example, Mid(0)_0, ..., Mid(0)_3 in FIG. 4 is sequentially input. The first compressor _0 is input into the second lock register _0, which is restored to the 256-bit intermediate state value Mid (0), and then input into the corresponding first compressor _0. The second lock register _1 is sequentially input into the Mid (1) _0, ..., Mid (1) _3 in FIG. 4, which is restored to the 256-bit intermediate state value Mid (1), and then input into the corresponding first compressor _1, and so on.

The next-level computing core also receives the second block field, wherein the second block field includes the second area of the hashed Merkle root, a timestamp, a target value, and a random number, a total of 128 bits. The next-level computing core also receives the estimated data of the computing module, wherein the estimated data can be 1408 bits, which is composed of 4 groups of 352 bits of data. The estimated data is not limited to this, and can also be any other bit. The estimated data is calculated by the estimated calculation module in the top layer area of the computing chip for the first block field and/or the intermediate state value. The 4 groups of 352 bits of data can be used by the first expander and/or the 4 first compressors and/or the 4 second expanders and/or the 4 second compressors. While generating the intermediate state value, using the pre-calculation module to calculate the pre-calculation data first can reduce the amount of calculation of the computing core, improve the computing efficiency, reduce the computing layout area of the computing core, and reduce power consumption. When the second block field and the pre-calculation data are transmitted from the top layer of the computing chip to the computing core, they can also be transmitted through the bit width conversion module and the level converter. The computing core is equipped with a latch for restoring the serial data flow of the second block field and the pre-calculation data.

A first expander is used to perform a first expansion operation on the second block field, and the result of the first expansion operation is shared with multiple first compressors, so that only one expansion operation needs to be performed; multiple first compressors each perform a first compression operation based on the input intermediate state value and the expansion operation result, and input the first compression operation result to multiple second expanders respectively; multiple second expanders each perform a second expansion operation based on the first compression operation result, and output the second expansion operation result to each electrically connected second compressor; the second compressor performs a second compression operation based on the second expansion result to obtain a workload certificate.

In the description of this specification, the descriptions with reference to the terms "some possible implementations", "some embodiments", "examples", "specific examples", or "some examples" etc. mean that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily need to be directed to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in an appropriate manner. In addition, a person skilled in the art may combine and combine different embodiments or examples described in this specification and features of different embodiments or examples, without contradiction.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

Any process or method description in a flowchart or otherwise described herein may be understood to represent a module, segment or portion of code that includes one or more executable instructions for implementing specific logical functions or process steps, and the scope of the preferred embodiments of the present invention includes alternative implementations in which functions may not be performed in the order shown or discussed, including performing functions in a substantially simultaneous manner or in a reverse order according to the functions involved, which should be understood by a technician in the technical field to which the embodiments of the present invention belong.

Regarding the method flow chart of the embodiment of the present application, certain operations are described as different steps performed in a certain sequence. Such a flow chart is illustrative and not restrictive. Certain steps described in this article can be grouped together and performed in a single operation, certain steps can be divided into multiple sub-steps, and certain steps can be performed in a different order than shown in this article. Each step shown in the flow chart can be implemented in any way by any circuit structure and/or tangible mechanism (for example, by software running on a computer device, hardware (for example, a logical function implemented by a processor or chip), etc., and/or any combination thereof).

It should be noted that the device in the embodiment of the present application can implement each process of the embodiment of the aforementioned method and achieve the same effect and function, which will not be elaborated here.

Each embodiment in this application is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the device, equipment, and computer-readable storage medium embodiments, since they are basically similar to the method embodiment, their descriptions are simplified, and the relevant parts can be referred to the partial description of the method embodiment.

It will be appreciated by those skilled in the art that embodiments of the present invention may be provided as methods, systems or computer program products. Thus, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk memory, CD-ROM, optical memory, etc.) containing computer-usable program code.

The present invention is described with reference to the flowchart and/or block diagram of the method, apparatus (system), and computer program product according to the embodiment of the present invention. It should be understood that each process and/or box in the flowchart and/or block diagram, as well as the combination of the processes and/or boxes in the flowchart and/or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operation steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

In a typical configuration, a computing device includes one or more processors (CPUs), input/output interfaces, network interfaces, and memory.

Memory may include non-permanent memory in a computer-readable medium, in the form of random access memory (RAM) and/or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.

Computer-readable media include permanent and non-permanent, removable and non-removable media that can be used to store information by any method or technology. Information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic tape cartridges, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information that can be accessed by a computing device. In addition, although the operations of the method of the present invention are described in a specific order in the accompanying drawings, this does not require or imply that these operations must be performed in this specific order, or that all the operations shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and/or one step may be decomposed into multiple steps.

Although the spirit and principle of the present invention have been described with reference to several specific embodiments, it should be understood that the present invention is not limited to the disclosed specific embodiments, and the division of various aspects does not mean that the features in these aspects cannot be combined to benefit. Such division is only for the convenience of expression. The present invention is intended to cover various modifications and equivalent arrangements included in the spirit and scope of the attached patent application.

The advantages and benefits described herein and other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the exemplary embodiments below. The accompanying drawings are only used for the purpose of illustrating exemplary embodiments and are not to be considered as limiting the present invention. Also, the same reference numerals are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:

FIG1 is a schematic diagram of a block header structure in the prior art; FIG2 is a schematic diagram of a flow chart of a calculation method for proof of work according to an embodiment of the present invention; FIG3 is a schematic diagram of a structure of a computing chip according to an embodiment of the present invention; FIG4 is a schematic diagram of a transmission state of an intermediate state value according to an embodiment of the present invention; FIG5 is a schematic diagram of a flow chart of a calculation method for proof of work according to another embodiment of the present invention; FIG6 is a schematic diagram of a structure of a calculation device for proof of work according to an embodiment of the present invention; FIG7 is a schematic diagram of a structure of a calculation module of a calculation device for proof of work according to an embodiment of the present invention; FIG8 is a schematic diagram of a structure of a next-level computing core according to an embodiment of the present invention.

In the drawings, the same or corresponding reference numerals indicate the same or corresponding parts.

Claims (36)

A computing task processing method includes: Receiving a computing task, the computing task including an original version field, and performing the following processing steps: Modifying the original version field to obtain multiple modified version fields; Based on the multiple modified version fields, performing a hash operation on the computing task to generate multiple intermediate state values, and the multiple intermediate state values are used for proof of work calculation. A computing task processing method as described in claim 1, wherein the processing steps are repeatedly performed, and the modified version field in the (n+1)th round of processing steps is inconsistent with the modified version field in the 1st to nth rounds of processing steps. The computing task processing method as described in claim 1 or 2 further includes: receiving another computing task, and executing the processing step based on the original version field of the other computing task. A computing task processing method as described in any one of claim 1-3, wherein the original version field includes a fixed field, a soft fork voting field and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of modified version fields. A computing task processing method as described in claim 4, wherein the bits of the remaining fields are modified in a random or fixed order to modify the original version fields to obtain a plurality of modified version fields. A computing task processing method as described in claim 4 or 5, wherein the original version field is 32 bits and the remaining field is 16 bits. A computing task processing method as described in any one of claim 1-6, wherein the computing task further includes a message field, and the message field includes a first area of a previous block hash and a hash Merkle root. A computing task processing method as described in any one of claim items 1-7, further comprising: Based on the intermediate state value, a plurality of sub-intermediate state values are obtained; A serial data flow consisting of the plurality of sub-intermediate state values is output for workload proof calculation. A computing task processing method as described in claim 8, wherein, based on the intermediate state value, it is split into multiple sub-intermediate state values. A computing task processing method as described in claim 8 or 9, wherein the intermediate state value is 256 bits and the sub-intermediate state value is 32 bits. A computing task processing method as described in any one of claim items 1-10, wherein the computing task further includes a message field, and the performing of a hash operation on the computing task based on the multiple modified version fields to generate multiple intermediate state values comprises: Combining the multiple modified version fields with the message field to obtain multiple first block fields, and performing a hash operation based on the multiple first block fields to generate multiple intermediate state values. A computing task processing method as described in claim 11, wherein each first block field is split into multiple sub-first block fields, and based on a serial data flow composed of multiple sub-first block fields of each first block field, a hash operation is performed to generate the intermediate state value. A computing task processing method as described in claim 11 or 12, wherein, based on the sequence values of multiple modified version fields, each modified version field and the message field are combined to obtain the corresponding first block field. A computing task processing method as described in claim 13, wherein a pulse level corresponding to the sequence value is output, and in response to the pulse level, a modified version field corresponding to the sequence value and the message field are locked as the first block field. A computing task processing method as described in claim 13 or 14, wherein after performing a hash operation on the mth first block field to generate the intermediate state value, the m+1th modified version field and the message field are combined to obtain the m+1th first block field. The computing task processing method as described in claim 1 further comprises: Performing a hash operation based on a plurality of the intermediate state values and the second block field of the computing task to obtain a proof of work; the second block field includes the second block of the hash Merkle root, a timestamp, a target value, and a random number. A computing task processing method as described in claim 16, wherein the hash operation based on the plurality of intermediate state values and the second block field of the computing task comprises: Performing a first expansion operation on the second block field to obtain first expansion data; Performing a plurality of first compression operations based on the plurality of intermediate state values and the first expansion operation results to obtain a plurality of first compression data; Performing a plurality of second expansion operations based on the plurality of the first compression data to obtain a plurality of the second expansion data; Performing a plurality of second compression operations based on the plurality of the second expansion data to obtain the workload proof. A computing task processing method as described in claim 1, wherein the intermediate state value is generated in a high voltage region, and after generating a plurality of the intermediate state values, the plurality of the intermediate state values are converted from the high voltage region to a low voltage region for use in proof of work calculations. A computing task processing method as described in any one of claims 1-18, wherein the intermediate state value is generated in a top layer area of a chip. A computing task processing method as described in any one of claim 1-19, wherein the hash operation is a SHA-256 operation. A computing task processing device includes: A receiving module for receiving a computing task, wherein the computing task includes an original version field; A modifying module for modifying the original version field to obtain multiple modified version fields; A computing module for performing a hash operation on the computing task based on the multiple modified version fields to generate multiple intermediate state values, wherein the multiple intermediate state values are used for workload proof calculation. A computing task processing device as described in claim 21, wherein the modification module is further used to repeatedly calculate and modify multiple modified version fields. A computing task processing device as described in claim 21 or 22, wherein the receiving module is further used to receive a new computing task, and the modifying module is further used to modify the original version field of the new computing task to obtain multiple modified version fields. A computing task processing device as described in any one of claim 21-23, wherein the original version field includes a fixed field, a soft fork voting field and a remaining field, and the remaining field is used to modify the original version field to obtain a plurality of modified version fields. A computing task processing device as described in any one of claim 21-24, wherein the computing task further includes a message field, and the message field includes a first area of a hash of a previous block and a hash Merkle root. A computing task processing device as described in any one of claim items 21-25, which also includes a bit width conversion module, used to split the intermediate state value of the first bit width generated by the computing module into multiple sub-intermediate state values of the second bit width; the serial data flow composed of the multiple sub-intermediate state values is used for proof of work calculation. A computing task processing device as described in any one of claim items 21-26, wherein the computing task also includes a message field, the computing module includes a first register, the first register is used to store a first block field composed of a single modified version field and a message field combination, and the computing module performs a hash operation based on multiple first block fields to generate multiple intermediate state values. A computing task processing device as described in claim 27, wherein the computing module includes a shift register, and the shift register is used to split the first block field into multiple sub-first block fields, and the serial data flow composed of the multiple sub-first block fields is used to perform a hash operation to generate the intermediate state value. A computing task processing device as described in claim 27 or 28, wherein the computing module includes a counter, the counter is used to generate a count value, and the computing module combines the modified version field corresponding to the count value and the message field to obtain the corresponding first block field based on the count value and the sequence values of the plurality of modified version fields. A computing task processing device as described in claim 29, wherein the computing module includes a level generating module, the level generating module generates a corresponding pulse level according to the count value, and the computing module locks the modified version field corresponding to the count value and the message field as the first block field in response to the pulse level. A computing task processing device as described in claim 29 or 30, wherein the computing module generates a completion signal when generating a single intermediate state value, the counter updates the count value in response to the completion signal, and restores the count value to the initial value after all the multiple first block fields have performed the hash operation. A computing task processing device as described in any one of claim items 21-31, which also includes a proof of work calculation module, which is used to perform a hash operation based on a plurality of the intermediate state values and a second block field of the computing task to obtain a proof of work; the second block field includes a second area of the hash Merkle root, a timestamp, a target value, and a random number. The computing task processing device as described in claim 32 further includes multiple second registers for receiving multiple intermediate state values; a first expander for performing a first expansion operation on the second block field to obtain first expanded data; multiple first compressors for performing multiple first compression operations based on the multiple intermediate state values and the first expansion operation results to obtain multiple first compressed data; multiple second expanders for performing multiple second expansion operations based on the multiple first compressed data to obtain multiple second expanded data; and multiple second compressors for performing multiple second compression operations based on the multiple second expanded data to obtain the workload proof. A computing task processing device as described in any one of claims 21-33, wherein the computing module is arranged in the top layer area of the chip. A computing task processing device as described in any one of claim items 21-34, which also includes a level converter for converting multiple intermediate state values from a high voltage area to a low voltage area. A computing task processing device as described in any one of claim 21-35, wherein the hash operation is a SHA-256 operation.

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