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TW201819655A - 使用pvd釕的方法與裝置 - Google Patents

使用pvd釕的方法與裝置 Download PDF

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TW201819655A
TW201819655A TW106133053A TW106133053A TW201819655A TW 201819655 A TW201819655 A TW 201819655A TW 106133053 A TW106133053 A TW 106133053A TW 106133053 A TW106133053 A TW 106133053A TW 201819655 A TW201819655 A TW 201819655A
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layer
ruthenium
silicide
gate stack
temperature
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喬瑟林簡 拉瑪林簡
羅斯 馬歇爾
雷建新
先敏 唐
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美商應用材料股份有限公司
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Abstract

描述了含釕的閘極堆疊和形成含釕閘極堆疊的方法。含有釕的閘極堆疊包含：多晶矽層，在基板上；矽化物層，在多晶矽層上；阻擋層，在矽化物層上；釕層，在阻擋層上； 及間隔層，包含在釕層的側面上的氮化物，其中釕層在形成間隔層之後基本上不包含氮化釕。形成釕層包含以下步驟：在氪環境中在包含高電阻率陶瓷材料的高電流靜電卡盤上濺射釕。濺射的釕層在大於或等於約500℃的溫度下退火。

Description

使用PVD釕的方法與裝置
本揭露書一般關於結合物理氣相沉積（PVD）釕的方法和電子裝置。特定地，本揭露書關於其中以PVD Ru層替代PVD鎢，以提供較低電阻率膜的方法和電子裝置。
半導體積體電路的持續小型化已迫使許多傳統結構發生變化，且已需要隨之而來的需求，以改進用以創建新結構的製程。用於較大特徵尺寸的傳統MOS（金屬氧化物半導體）電晶體閘極結構包括沉積的氮化鎢阻擋層和鎢通孔層。濺射是沉積WN阻擋層和W通孔層的通常優選方法。然而，隨著薄膜厚度的降低，鎢電阻率增加，導致在位線應用中未來節點DRAM的有用性降低。
因此，本領域存在有用於薄膜和用以沉積具有較低的位線電阻率和對氧化不敏感的薄膜的方法的需求。
本揭露書的一個或多個實施例涉及形成閘極堆疊的方法。提供了一種電漿濺射腔室，包括靶和基座，靶包含釕，基座用於支撐與靶相對而濺射沉積的基板。基座包含大於或等於約350℃的溫度的高電流靜電卡盤。氪流到腔室中並激發成電漿，以在基板上沉積釕層。提供退火腔室，且在大於或等於約500℃的溫度下對基板上的釕層進行退火。
本揭露書的另外的實施例涉及閘極堆疊，包含：多晶矽層，在基板上；矽化物層，在多晶矽層上；阻擋層，在矽化物層上；釕層，在阻擋層上；及間隔層，包含在釕層的側面上的氮化物。釕層在形成間隔層之後基本上不包含氮化釕。
本揭露書的進一步的實施例涉及形成閘極堆疊的方法。在基板上形成多晶矽層。在多晶矽層上形成矽化物層。矽化物層包含具有約20Å的厚度的矽化鈦。在矽化物層上形成阻擋層。阻擋層包含TiN，TaN，WN，或TiSiN的一種或多種。在阻擋層上形成任選的界面層。PVD Ru層沉積在阻擋層或任選的界面層上。PVD Ru層在氪環境中，以大於或等於約350℃的溫度，在包含高電阻率陶瓷的高電流靜電卡盤上沉積在基板上。PVD Ru層具有約100Å到約300Å的範圍中的厚度。PVD Ru層在大於或等於約500℃的溫度下進行退火。在退火的PVD Ru層的側面上形成間隔層。間隔層包含SiN並基本上不形成氮化釕。
在描述本發明的幾個示例性實施例之前，應當理解本發明不限於以下的描述中所闡述的構造或製程步驟的細節。本發明能夠具有其他實施例並且能夠以各種方式實踐或執行。
本文所用的「基板」是指在製造過程中在其上進行膜處理的任何基板或形成在基板上的材料表面。例如，可進行處理的基板表面包括諸如矽、氧化矽、應變矽、絕緣體上矽（SOI）、碳摻雜氧化矽、非晶矽、摻雜矽、鍺、砷化鎵、玻璃、藍寶石的材料，及諸如金屬、金屬氮化物、金屬合金和其它導電材料的任何其它材料，這取決於應用。基板包括(但不限於) 半導體晶圓。基板可曝露於預處理製程以拋光、蝕刻、還原、氧化、羥基化、退火及/或烘烤基板表面。除了直接在基板本身的表面上進行膜處理之外，在本發明中，所揭露的膜處理步驟的任何一個也可在如下面更詳細揭露的基板上形成的下層上進行，術語「基板表面」意欲包括上下文所指示的此類下層。因此，例如，當將膜/層或部分膜/層沉積在基板表面上時，新沉積的膜/層的曝露表面成為基板表面。
如在本說明書和所附隨的申請專利範圍中所使用的，術語「前驅物」、「反應物」、「反應性氣體」及類似者可互換使用，以指能夠與基板表面反應的任何氣體物質。
在本揭露書的一個或多個實施例中，較低電阻率的Ru膜用高溫偏壓靜電卡盤（ESC）沉積。一些實施例在約190℃至約550℃的溫度範圍中使用Kr濺射Ru製程。在一些實施例中可使用兩步驟製程來改善Ru電阻率以及膜表面形態。隨著製程溫度在約190℃至約550℃的範圍中升高，Ru電阻隨著ESC溫度的升高而降低，並在約680℃至約900℃的範圍中的溫度退火。藉由組合高溫Ru製程和較高溫度退火製程，與W膜相比可形成較低電阻率的Ru膜。
參考第1圖，本揭露書的一個或多個實施例涉及金屬氧化物半導體電晶體閘極堆疊40。電晶體閘極堆疊40包括形成為較低摻雜的矽層基板14的高摻雜源極/汲極（S/D）區域10、12 ，其可在矽晶圓上外延地形成或甚至在絕緣體上矽（SOI））結構中形成。可能在S/D區域10、12的佈植和退火步驟之前，可在整個MOS區域之上方形成薄的閘極氧化物層16。閘極堆疊40形成在閘極氧化物層16之上方。各種實施例的閘極堆疊40包含多晶矽層20、矽化物層42、阻擋層44和釕層46。氧化物-氮化物-氧化物（ONO）結構可夾在多晶矽層20內。
源極/汲極孔26可光刻地蝕刻到S/D區域10、12之上方的閘極氧化物層16，以限定閘極堆疊40。可由氧化矽製成的間隔物28可形成在閘極堆疊40的側面上。在形成閘極堆疊40之後，可使用堆疊40作為佈植遮罩而佈植S/D區域10、12。
隨後的處理步驟可在S/D孔26的底部打開閘極氧化物層16，如有必要，提供歐姆接觸層，並用多晶矽或金屬去填充S/D孔26，以電接觸S/D區域10、12。可移除覆蓋層24以在形成MOS閘極的S/D區域10、12之間提供與閘極氧化物層16的頂部的電接觸。
各種實施例的釕層46直接形成在阻擋層44上。如就這一點而使用的，術語「直接」表示在釕層46和阻擋層44之間不存在界面層。
本揭露書的一個或多個實施例涉及包含在基板14上的多晶矽層20的閘極堆疊。多晶矽層20可具有合適的厚度並且可藉由任何合適的技術形成。一些實施例的多晶矽層20包含氧化物-氮化物-氧化物（ONO）結構。
矽化物層42形成在多晶矽層20上。一些實施例的矽化物層42包含矽化鈦（TiSi）。矽化物層42的厚度可為任何合適的厚度。在一些實施例中，矽化物層42具有在約10Å到約50Å的範圍中的厚度，或在約15Å至約40Å的範圍中，或在約20Å至約30Å的範圍中。
矽化物層42可藉由任何合適的技術或製程形成。例如，矽化物層42可藉由化學氣相沉積（CVD），電漿增強化學氣相沉積（PECVD），原子層沉積（ALD），電漿增強原子層沉積（PEALD），或物理氣相沉積(PVD）而形成。
阻擋層44形成在矽化物層42上。阻擋層可由任何合適的材料和任何合適的技術製成。在一些實施例中，阻擋層包含氮化物。在一個或多個實施例中，氮化物包含TiN，TaN，WN，或TiSiN的一種或多種。
阻擋層的厚度可為任何合適的厚度。在一些實施例中，阻擋層44具有在約20Å至約200Å的範圍中的厚度，或在約30Å至約150Å的範圍中，或在約50Å至約100Å的範圍中。
阻擋層44可藉由任何合適的技術或製程形成。例如，阻擋層44可藉由化學氣相沉積（CVD），電漿增強化學氣相沉積（PECVD），原子層沉積（ALD），電漿增強原子層沉積（PEALD），或物理氣相沉積(PVD）而形成。
釕層46形成在阻擋層44上。釕層46藉由物理氣相沉積形成，並可稱為PVD Ru層。釕層46可直接形成在阻擋層44上而沒有界面層。如就這一點而使用的，「界面層」是在阻擋層44和釕層46之間分開並有意形成的層。在一些實施例中，釕層46形成在任選的界面層（未顯示）上。
釕層46可形成為任何合適的厚度。在一些實施例中，釕層46具有在約100Å至約300Å的範圍中的厚度，或在約100Å至約200Å的範圍中，或在約150Å至約300Å的範圍中，或在約200Å至約300Å的範圍中。
在一些實施例中，形成釕層46包含提供電漿濺射腔室，電漿濺射腔室包括靶和基座，靶包含釕，基座用於支撐與靶相對的待被濺射沉積的基板。一些實施例的基座包含保持在大於或等於約350℃的溫度的高電流靜電卡盤。在一些實施例中，靜電卡盤保持在約450℃至約550℃的範圍中的溫度。在一些實施例中，高電流靜電卡盤包含高電阻率陶瓷。
電漿處理氣體（如，氪氣）流到電漿濺射腔室中並退出到電漿中。電漿使得釕原子從釕靶濺射到基板上，以沉積釕層46。在一些實施例中，電漿處理氣體基本上僅包含氪。如就這一點而使用的，術語「基本上只有」表示活性電漿物質大於或等於約90原子％的Kr。
在第2圖的橫截面圖中示意性地顯示了可用於濺射釕層46的濺射腔室50的實例。濺射腔室50包括圍繞中心軸線54佈置的真空腔室52，釕靶56通過隔離器58被支撐在真空腔室52上，隔離器58將靶56真空密封到真空腔室52，並將靶56與電接地真空腔室52電隔離。真空泵系統（未顯示）將真空腔室52的內部抽吸到低毫托範圍中的壓力。
釕靶56的前表面的形狀可為平面的或大體上凹的，具有比內徑部分更厚的外周邊邊緣。釕靶56包括面向真空腔室52內部且通常含有不超過5原子％的釕以外的元素的釕層，以提供濺射釕源。
DC功率源60相對於接地的真空腔室52或接地的側壁屏蔽（未顯示）將靶負偏壓到約600至1000VDC，以將電漿處理氣體激發成電漿。
通常，氬是電漿處理氣體，並通過質流控制器從氬氣源供應到真空腔室52中。然而，本發明人已經發現，氬原子可能嵌入沉積的釕層46中，而使用氪氣源62作為電漿處理氣體不會導致氪原子的嵌入。因此，各種實施例的電漿處理氣體基本上由氪組成，或由氪組成。在一些實施例中，電漿處理氣體基本上僅包含氪原子。氪氣源62通過質流控制器64連接到真空腔室52。
靶功率將電漿處理氣體激發成電漿，且電漿的正電荷離子朝向靶54加速並從其中濺射釕原子。電漿的密度藉由放置在靶56的背面的磁控管66而增加，磁控管66具有一種磁極性的內部磁極68，內部磁極68藉由相對磁極性的外部磁極70所包圍。極68、70將平行於靶56的表面的磁場投射到真空腔室52中，以捕獲電子，並從而增加電漿密度和所得到的濺射速率。為了提高濺射均勻性和靶利用率，磁極68、70圍繞中心軸線54而不對稱，但是支撐在連接到沿著中心軸線54延伸的軸74的臂72上。馬達76使軸74旋轉，且從而磁控管66圍繞中心軸線54提供至少方位均勻性。
真空腔室52內的基座80支撐與靶56相對的晶圓82或其它基板，以塗覆從靶56濺射的釕。除了對準標記之外，晶圓通常是平面的和圓形的。任選地，RF功率源84通過電容耦合電路86而偏壓基座80。基座80是導電的，使得它用作為電極。在真空腔室52內的電漿存在下的RF偏壓導致基座80上產生負DC自偏壓，使得濺射的釕離子朝向晶圓82加速，並且它們的軌跡進入形成在晶圓82中的任何高深寬比的孔。
在濺射釕層46之後，提供退火腔室來退火釕層46。退火腔室可為適於將具有釕層46的基板的溫度升高到大於或等於約500ºC的溫度的任何腔室。合適的退火腔室包括(但不限於)熱處理腔室、快速熱退火（RTA）腔室，尖峰退火腔室和雷射退火腔室。在一些實施例中，在氮氣環境中，在約900℃的溫度下退火釕層約30秒。在一些實施例中，退火釕層包含將釕層加熱至約500℃，以大於或等於約50℃/秒的速率將溫度升高至約900℃，保持溫度約30秒，並以等於或大於約70℃/秒的速率冷卻溫度。
在形成包括退火的釕層46之後，在釕層46的側面46a上形成包含氮化物的間隔層28。一些實施例的間隔層28包含SiN。在一個或多個實施例中，間隔層28的形成導致在釕層46的側面基本上不形成氮化釕。如以這種方式使用的，「基本上不含氮化釕」是指小於約5％的釕層46的寬度變成氮化釕。在一些實施例中，小於約2％的釕層46的寬度變成氮化釕。
在形成間隔層28之前，期間或之後，可在釕層46的頂部上形成任選的覆蓋層24。覆蓋層24可由與間隔層28相同的材料製成，或者可為不同的材料。
實施例
第3圖顯示了作為膜厚度的函數的沉積的釕，退火的釕和沉積的鎢膜的金屬電阻率（μΩ-cm）的曲線圖。退火後的釕電阻率與沉積的鎢電阻率相似。將釕膜在氮氣環境中在約900℃的溫度下退火約30秒。
第4圖顯示了沉積的釕和退火的釕膜的釕電阻率（μΩ-cm）的曲線圖。膜以約450℃的靜電卡盤溫度沉積，並在氮氣環境中在約825℃或900℃下退火約30秒。
貫穿這份說明書的「一個實施例」，「某些實施例」，「一個或多個實施例」或「實施例」的引用意味著結合實施例描述的特定特徵，結構，材料或特性包括在本發明的至少一個實施例中。因此，貫穿這份說明書的各個地方中的諸如「在一個或多個實施例中」，「在某些實施例中」，「在一個實施例中」或「在實施例中」）的短語的出現不一定指代本發明的相同實施例。此外，特定的特徵，結構，材料或特性可以任何合適的方式結合在一個或多個實施例中。
儘管已經參考特定實施例描述了本發明，但是應當理解這些實施例僅僅是本發明的原理和應用的說明。對於熟悉本領域技術者顯而易見的是，在不背離本發明的精神和範圍的情況下，可對本發明的方法和設備進行各種修改和變化。因此，本發明意圖包括在附隨的申請專利範圍及其等效元件的範圍內的修改和變化。
10‧‧‧區域
12‧‧‧區域
14‧‧‧基板
20‧‧‧多晶矽層
24‧‧‧覆蓋層
28‧‧‧間隔物/間隔層
40‧‧‧閘極堆疊
42‧‧‧矽化物層
44‧‧‧阻擋層
46‧‧‧釕層
46a‧‧‧側面
50‧‧‧濺射腔室
52‧‧‧真空腔室
54‧‧‧中心軸線/靶
56‧‧‧靶
58‧‧‧隔離器
60‧‧‧DC功率源
62‧‧‧氪氣源
64‧‧‧質流控制器6
66‧‧‧磁控管
68‧‧‧極
70‧‧‧極
72‧‧‧臂
74‧‧‧軸
76‧‧‧馬達
80‧‧‧基座
82‧‧‧晶圓
84‧‧‧RF功率源
86‧‧‧電容耦合電路
因此，可詳細了解本發明的上述特徵的方式，簡短摘要於上的本發明的更具體的描述可藉由參考實施例而獲得，其中一些實施例顯示在附隨的圖式中。然而，應當注意附隨的圖式僅顯示了本發明的典型實施例，且因此不應被視為限制其範圍，因為本發明可承認其他同等有效的實施例。
第1圖根據本揭露書的一個或多個實施例的氣體堆疊；
第2圖顯示了根據本揭露書的一個或多個實施例的物理氣相沉積腔室的示意性橫截面圖；
第3圖顯示了作為膜厚度的函數的釕和鎢膜的金屬電阻率的曲線圖；及
第4圖顯示了作為靜電卡盤溫度的函數的釕膜的電阻率的曲線圖。
國內寄存資訊 (請依寄存機構、日期、號碼順序註記) 無
國外寄存資訊 (請依寄存國家、機構、日期、號碼順序註記) 無

Claims (20)

  1. 一種形成一閘極堆疊的方法，該方法包含以下步驟： 提供一電漿濺射腔室，該電漿濺射腔室包括一靶和一基座，該靶包含釕，該基座用於支撐與該靶相對的待被濺射的一基板，該基座包含大於或等於約350℃的一高電流靜電卡盤；將氪氣流到該腔室中，並將該氪氣激發成一電漿，以在該基板上沉積一釕層；提供一退火腔室；及在大於或等於約500℃的溫度下退火在該基板上的該釕層。
  2. 如請求項1所述之方法，其中該靜電卡盤的一溫度在約450℃至約550℃的範圍中。
  3. 如請求項1所述之方法，其中該靜電卡盤包含高電阻率陶瓷。
  4. 如請求項1所述之方法，其中在一氮氣環境中，在約900℃的一溫度下退火該釕層約30秒。
  5. 如請求項1所述之方法，其中退火該釕層包含將該釕層加熱至約500℃，以大於或等於約50℃/秒的速率將該溫度升高至約900℃，將該溫度保持約30℃秒，並以等於或大於約70℃/秒的速率冷卻該溫度。
  6. 如請求項1所述之方法，其中該釕層具有在約100 Å至約300Å的範圍中的一厚度。
  7. 如請求項1所述之方法，其中該釕層直接沉積在一阻擋層上而沒有一界面層。
  8. 如請求項7所述之方法，其中該阻擋層包含TiN，TaN，WN，或TiSiN的一種或多種。
  9. 如請求項8所述之方法，其中該阻擋層形成在一矽化物層上。
  10. 如請求項9所述之方法，其中該矽化物層包含具有約20 Å的一厚度的TiSi。
  11. 如請求項1所述之方法，進一步包含在該釕層的多個側面上形成一間隔層，該間隔層包含SiN。
  12. 如請求項11所述之方法，其中形成該間隔層之步驟基本上不形成氮化釕。
  13. 一種閘極堆疊，包含： 一多晶矽層，在一基板上；一矽化物層，在該多晶矽層上；一阻擋層，在該矽化物層上；一釕層，在該阻擋層上；及一間隔層，包含在該釕層的多個側面上的一氮化物，其中該釕層在形成該間隔層之後基本上不包含氮化釕。
  14. 如請求項13所述之閘極堆疊，其中該矽化物層包含具有約20Å的一厚度的矽化鈦。
  15. 如請求項14所述之閘極堆疊，其中該阻擋層包含TiN，TaN，WN，或TiSiN的一種或多種。
  16. 如請求項15所述之閘極堆疊，其中該釕層直接沉積在一阻擋層上而沒有一界面層。
  17. 如請求項15所述之閘極堆疊，進一步包含在該釕層和該阻擋層之間的一界面層。
  18. 如請求項15所述之閘極堆疊，其中該釕層具有在約100 Å至約300Å的範圍中的一厚度。
  19. 如請求項17所述之閘極堆疊，其中該間隔層包含SiN。
  20. 一種形成一閘極堆疊的方法，包含以下步驟： 在一基板上形成一多晶矽層；在該多晶矽層上形成一矽化物層，該矽化物層包含具有約20Å的一厚度的矽化鈦；在該矽化物層上形成一阻擋層，該阻擋層包含TiN，TaN，WN，或TiSiN的一種或多種；在該阻擋層上任選地形成一界面層；沉積一PVD Ru層在該阻擋層或任選的該界面層上，該PVD Ru層在一氪環境中，以大於或等於約350℃的一溫度，在包含一高電阻率陶瓷的一高電流靜電卡盤上沉積在該基板上，該PVD Ru層具有約100Å到約300Å的範圍中的一厚度；在大於或等於約500℃的一溫度下退火該PVD Ru層；及在經退火的該PVD Ru層的多個側面上形成一間隔層，該間隔層包含SiN並基本上不形成氮化釕。
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