TW201816882A - Hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication - Google Patents

Abstract

In one embodiment, a method for hydrofluorocarbon gas-assisted plasma etch for interconnect fabrication includes providing a layer of a dielectric material and etching a trench in the layer of the dielectric material, by applying a mixture of an aggressive dielectric etch gas and a polymerizing etch gas to the layer of the dielectric material. In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive lines connecting the plurality of semiconductor devices. A pitch of the plurality of conductive lines is approximately twenty-eight nanometers.

Description

 Hydrofluorocarbon gas assisted plasma etching for interconnect manufacturing  

The present invention relates generally to integrated circuits and, more particularly, to metal patterning methods for fabricating integrated circuits.

Integrated circuits typically use metal interconnects (or "wires") to connect the transistors and other semiconductor devices on the IC. These interconnects are typically fabricated during a line back end (BEOL) process after individual semiconductor devices have been formed on the wafer.

These interconnects are typically fabricated using an additive damascene process in which a underlying insulating layer, such as hafnium oxide, is patterned in an open channel. A conductive metal is subsequently deposited on the insulating layer to fill the trench with a metal. The metal is removed until the top of the insulating layer, but remains in the channel to form a patterned conductor. A continuous layer of insulator and metal are formed in accordance with the damascene process to form a multilayer metal interconnect structure.

In one embodiment of the invention, a method of assisting plasma etching of a HFC gas for interconnect fabrication includes providing a dielectric material and applying a strong dielectric etch gas to the layer of dielectric material A mixture of etching gases is polymerized and the channels are etched in the layer of dielectric material.

In another embodiment, a method of interconnecting a hydrofluorocarbon gas-assisted plasma etch for fabrication includes providing a cap layer, providing a layer of dielectric material directly over the cap layer, and providing a layer directly in the layer A mask layer on the electrical material. The mask layer is patterned to expose a portion of the layer of dielectric material, and then a portion of the layer of dielectric material is etched to form a plurality of trenches. The etching is performed using a mixture of a strong dielectric etch gas and a polymeric etch gas, and wherein the etch stops at the cap layer. The plurality of channels are filled with a conductive metal to form a plurality of conductive lines.

In another embodiment, an integrated circuit includes a plurality of semiconductor devices and a plurality of conductive traces connecting the plurality of semiconductor devices. The pitch of the plurality of conductive lines is about 28 nm.

100‧‧‧ integrated circuit

102‧‧‧ front end

104‧‧‧Semiconductor wafer

106‧‧‧ gate

108‧‧‧ Coverage

110‧‧‧ dielectric layer

112‧‧‧Photomask

114‧‧‧ Backend

116‧‧‧ Canal

118‧‧‧ Passivation layer

120‧‧‧ Conductive metal layer

122‧‧‧Interconnection

For a more detailed description of the features of the invention as set forth above, reference may be made to the particular embodiments of the invention,

It is to be understood, however, that the appended claims

1A-1E is a cross-sectional view depicting stages of fabrication of an integrated circuit in accordance with an embodiment of the present invention.

One embodiment of the present invention discloses a method and apparatus for assisting plasma etching of a hydrofluorocarbon gas for interconnect fabrication. Metal interconnects are typically formed during the line back end (BEOL) phase of fabricating integrated circuits. For example, a dry etching process using a fluorocarbon gas can be used to define a channel in the dielectric layer of the integrated circuit. Conductive metals are then deposited in the channels to form interconnects. The use of oligomeric fluorocarbon gases such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), or nitrogen trifluoride (NF ₃ ) can define channels that provide good wire-to-via connections; However, this gas is non-selective to the hard mask layer and tends to be unable to maintain the interconnect pattern size. Use of highly polymerized fluorocarbon gases (eg perfluorocyclobutane (C ₄ F ₈ ), hexafluorobutadiene (C ₄ F ₆ ), octafluorocyclopentene (C ₅ F ₈ ), fluoromethane (CH _{3 )} F), fluoroform (CHF ₃ ), or heptafluorocyclopentene (C ₅ HF ₇ )) may give better selectivity and maintain pattern size; however, these gases tend to be aspect ratio related etching, and The etch stop causes a poor connection of the wire to the via. It can add additional gases to promote dissociation, mixing, and improve the resulting line profile, such as argon (Ar), nitrogen (N ₂ ), carbon monoxide (CO), oxygen (O ₂ ), carbon dioxide (CO ₂ ), and the like.

Embodiments of the present invention etch a channel pattern into a dielectric layer of an integrated circuit using a mixture of a strong dielectric etch gas and a polymeric etch gas. It will be appreciated in the context of the present invention that a strongly dielectric etch gas is a fast acting, non-selective chemical etchant for minimal residual deposition. The polymeric etch gas deactivates the vertical sidewalls of the trench and protects it from damage by strong dielectric etch gases and lateral etch. The resulting channels maintain the target pattern size and sidewall profile and form a small, dense pattern. In addition, the etch can be performed quickly and the reactive ion etch lags from minimal to none.

1A-1E is a cross-sectional view depicting stages of fabrication of integrated circuit 100 in accordance with an embodiment of the present invention. Accordingly, FIG. 1A-1E is also generally a flow chart depicting portions of a particular embodiment of a method of fabricating integrated circuit 100 in accordance with the present invention.

In particular, FIG. 1A depicts the integrated circuit 100 in the intermediate stage of processing, that is, after the line front end processing ends but before the line back end processing ends. In other words, the integrated circuit 100 begins not in the form described in FIG. 1A, but can be developed into the described structure through a number of processing steps that are not described but are well known to those skilled in the art.

The integrated circuit 100 generally includes a front end 102 that may include a semiconductor wafer 104 (eg, formed of crystalline germanium (Si), germanium (Ge), germanium telluride (SiGe), gallium arsenide (GaAs), or other semiconductor materials. And a pattern of individual, unconnected structures formed on the semiconductor wafer 104, such as a pattern of gates 106 _{1 -} 106 _n (hereinafter collectively referred to as "gate 106"). Gate 106 can include a plurality of transistors and/or other semiconductor devices. For the sake of clarity, the front end 102 of the integrated circuit 100 is described in simplified form.

One embodiment of the present invention deposits a cap layer 108 on the front end 102. In a specific embodiment, the cap layer 108 can be formed, for example, of tantalum nitride (SiN), tantalum carbonitride (SiCN), or hafnium carbonitride (SiC _x N _y O _z ). The cap layer 108 can be deposited, for example, via plasma enhanced chemical vapor deposition (PECVD). The dielectric layer 110 is deposited directly on the cap layer 108 and may be formed of a porous dielectric material such as a low-k dielectric, an ultra-low-k dielectric (ULK), cerium oxide (SiO ₂ ), or the like. Dielectric material. Dielectric layer 110 can also be deposited via PECVD. The mask layer 112 is then deposited directly onto the dielectric layer 110. The mask layer 112 may be formed of a metal, a tantalum nitride (SiN), a photoresist, or other materials. In one example, the reticle layer 112 comprises a multilayer reticle, such as a three layer photoresist (which may include, for example, a photoresist layer, a germanium containing anti-reflective coating (SiARC), and a carbon hard mask layer). The photomask layer 112, if formed of a photoresist, can be deposited via spin coating. In summary, the cap layer 108, the dielectric layer 110, and the photomask layer 112 form the beginning of the rear end 114 of the integrated circuit 100.

As depicted in FIG. 1B, the mask layer 112 is patterned to expose portions of the dielectric layer 110. In one embodiment, the mask layer 112 is patterned using lithography techniques such as optical lithography or electron beam direct writing lithography. In one embodiment, the lithography technique includes a positive photoresist to remove the mask layer 112 up to the dielectric layer 110, except for the portion of the mask layer 112 described in FIG. 1B.

Dielectric layer 110 is etched using a mixture of a strong dielectric etch gas and a polymeric etch gas, as depicted in FIG. 1C. Therefore, a strong dielectric etching gas and a polymeric etching gas are simultaneously applied as a mixture. The strongly dielectric etching gas may comprise, for example, a fluorocarbon gas such as carbon tetrafluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), or nitrogen trifluoride (NF ₃ ). The polymeric etching gas may comprise, for example, a hydrofluorocarbon gas compound such as heptafluorocyclopentene (C ₅ HF ₇ ). In other examples, the polymeric etching gas may comprise perfluorocyclobutane (C ₄ F ₈ ), hexafluorobutadiene (C ₄ F ₆ ), octafluorocyclopentene (C ₅ F ₈ ), fluoromethane ( CH ₃ F), or fluoroform (CHF ₃ ). In a specific embodiment, the gas mixture comprises from about 20 to about 40 parts of a strong dielectric etch gas to one part of a polymeric etch gas. This ratio can be adjusted as needed based on design requirements. For example, when a wider interconnect is desired, a higher concentration of strongly dielectric etch gas can be used. Most of the ratio will produce the desired result in the range of -10 ° C to 60 ° C.

The intense etching gas removes portions of the dielectric layer 110 that are not directly under the residual portion of the mask layer 112 until the capping layer 108 acts as a selective etch stop layer. The etch forms one or more channels 116 _{1 -} 116 _m (hereinafter collectively referred to as "channels 116") in the dielectric layer 110. As the etch gas removes the dielectric material, the polymeric etch gas deposits a carbon-rich layer on the exposed vertical sidewalls of the trench 116 (as described by passivation layer 118). Thus, the passivation layer 118 protects a portion of the porous dielectric layer 110 from damage due to prolonged exposure to strong etching gases.

As described in FIG. 1D, the cap layer 112 is next extracted (eg, via plasma etching) and wet cleaned. This also causes the passivation layer 118 to be removed. Conductive metal layer 120 is then deposited directly onto dielectric layer 110. The conductive metal layer 120 fills the trench 116 in the dielectric layer 110, thus forming a pattern of fine lines or interconnects in the rear end 114 of the integrated circuit 100. The conductive metal layer 120 may include, for example, copper (Cu), a copper alloy, gold (Au), nickel (Ni), cobalt (Co), silver (Ag), ruthenium (Ru), or any other that does not easily form a volatile species. material. Depositing the conductive metal layer 120 can be performed via electroplating and/or other deposition techniques, and the barrier layer can be deposited on the dielectric layer 110 with or without prior thereto.

As described in FIG. 1E, the conductive metal layer 120 is then planarized (eg, via chemical mechanical planarization or other techniques) up to the dielectric layer 110. Portions of the remaining conductive metal layers (e.g., portions of the fill channels) form a pattern of thin conductive traces or interconnects 122 _{1 -} 122 _m (hereinafter collectively referred to as "interconnects 122").

Additional layers of integrated circuit 100 can then be formed for additional fabrication steps. Additional layers of interconnects may be formed, for example, using the techniques described above and/or other techniques. In addition, other components of the integrated circuit 100, including vias and contacts, can be fabricated using the fabrication process described above. Thus, the application of the disclosed technology is not limited to the fabrication of interconnects.

Since the sidewalls of the vertical trench are passivated by the polymeric etch gas, the interconnect formed as a result of the described process has a precise, smooth, uniform profile of dimensions (e.g., channel and via width). This makes it possible to make small, dense patterns of high yield interconnects. For example, a pattern density with a pitch as small as about 28 nm can be obtained. In addition, the mixture of polymeric etching gas and strongly dielectric etching gas reduces the occurrence of pattern-dependent etch rates. Since the strong dielectric etch gas forms a majority of the etching gas mixture, the vertical etch rate of the channel is substantially faster; however, the hydrogen in the polymeric etch gas removes some of the fluorine in the strongly dielectric etch gas and can be on the sidewall of the trench Deposit a carbon rich layer.

While the above is a specific embodiment of the invention, other and further embodiments of the invention (such as specific examples of contact and via height etching) are contemplated without departing from the basic scope of the invention. Various specific embodiments or portions thereof set forth herein can be combined to yield further specific embodiments. Further, terms such as top, side, bottom, front, and back are relative or positional terms and are used with respect to the illustrative embodiments described in the drawings, such terms are interchangeable.

Claims (20)

 A method comprising: providing a layer of dielectric material; and etching a trench in the layer of dielectric material by applying a mixture of a strong dielectric etch gas and a polymeric etch gas to the layer of dielectric material.    The method of claim 1, wherein the strongly dielectric etching gas comprises a fluorocarbon gas, and the polymeric etching gas comprises a hydrofluorocarbon gas compound.    The method of claim 2, wherein the mixture comprises from about 20 to 40 parts of a strong dielectric etching gas to one part of the polymeric etching gas.    The method of claim 2, wherein the intense dielectric etch gas comprises carbon tetrafluoride.    The method of claim 2, wherein the strongly dielectric etching gas comprises sulfur hexafluoride.    The method of claim 2, wherein the strongly dielectric etching gas comprises nitrogen trifluoride.    The method of claim 2, wherein the polymeric etching gas comprises perfluorocyclobutane.    The method of claim 2, wherein the polymeric etching gas comprises heptafluorocyclopentene.    The method of claim 1, further comprising depositing a conductive metal in the channel to form a conductive line.    The method of claim 1, further comprising: providing a cover layer under the layer of dielectric material, wherein the etching terminates at the cover layer.    A method comprising: providing a cover layer; providing a layer of dielectric material directly on the cover layer; providing a photomask layer directly on the layer of dielectric material; patterning the mask layer to expose a portion of the layer An electric material; etching a portion of the dielectric material to form a plurality of trenches, wherein the etching is performed using a mixture of a strong dielectric etching gas and a polymeric etching gas, and wherein the etching stops at the cap layer; and the plurality of strips The channel is filled with a conductive metal to form a plurality of conductive lines.    The method of claim 11, wherein the strongly dielectric etching gas comprises a fluorocarbon gas, and the polymeric etching gas comprises a hydrofluorocarbon gas compound.    The method of claim 12, wherein the mixture comprises from about 20 to about 40 parts of a strong dielectric etching gas to one part of the polymeric etching gas.    The method of claim 12, wherein the intense dielectric etch gas comprises carbon tetrafluoride.    The method of claim 12, wherein the intense dielectric etch gas comprises nitrogen trifluoride.   The method of claim 12, wherein the strongly dielectric etching gas comprises sulfur hexafluoride (SF ₆ ).  The method of claim 12, wherein the polymeric etching gas comprises heptafluorocyclopentene.    The method of claim 12, wherein the polymeric etching gas comprises perfluorocyclobutane.    An integrated circuit comprising: a plurality of semiconductor devices; and a plurality of conductive lines connecting the plurality of semiconductor devices, wherein the plurality of conductive lines have a pitch of about 28 nm.    The integrated circuit of claim 19, wherein each of the plurality of conductive lines comprises: a conductive metal line; and a carbon-containing layer directly between the conductive metal and the dielectric material.