TW201428927A - ESD protection circuit - Google Patents

Abstract

An electrostatic discharge (ESD) protection circuit is coupled between first and second pads to protect an internal circuit there between. Under a normal operating condition, a voltage on the first pad is higher than that on the second pad. The ESD protection circuit includes a substrate of a first conductivity type; first well of a second conductivity type in the substrate, wherein the first well is coupled to the first pad; a snapback device housed in the first well; and a diode string in the substrate, connected in series with the snapback device and separated from the first well, wherein the serially connected diode string and snapback device is connected between the first pad and the second pad. With the isolation from the first well, the holding voltage of the ESD protection circuit can be tuned by adjusting the number of diodes in the diode string without using a guard ring.

Description

Electrostatic discharge protection circuit

The invention relates to an electrostatic discharge protection circuit, in particular to an electrostatic discharge protection circuit capable of adjusting a holding voltage.

Protecting internal circuitry from electrostatic discharge has been a challenge for those skilled in the art. The snapback device is one of the devices commonly used in electrostatic discharge protection circuits. When excessive electrical stress occurs, such devices exhibit their turning characteristics. Figure 1 shows a current-voltage graph of a turning device having a turning characteristic. As shown in FIG. 1, when the voltage across the turning device is lower than the trigger voltage V _trig , the turning device will maintain a cutoff state, and when the voltage across the voltage rises to the trigger voltage V _trig , the PN connection in the turning device The surface enters the cumulative collapse state and triggers the parasitic BJT transistor of the turning device to turn on and conduct current. Once the turning device starts to conduct current, the voltage across the voltage drops to the holding voltage _Vhold , that is, after the turning occurs, the rise is resumed. To avoid the turning device remains open or enters latch (Latchup force) when the normal operation state, holding voltage V _hold live voltage V _op be high, preferably should be retained beyond the safe operating voltage V _op of internal circuits operate more Marginal. In addition, different internal circuits may require different operating voltages, so the holding voltage _Vhold should be adjustable.

A conventional method or a diode means connected in series with the transition to drop through to increase the voltage imposed extra hold of the voltage V _hold. However, this attempt not only failed to achieve the goal, but also worsened the above-mentioned low holding voltage problem. Figure 2 shows the current-voltage curve of a single turning device (shown by the dashed line) and the current-voltage curve of the turning device with the diode (shown by the solid line). As shown in FIG. 2, when the turning device is connected in series with the diode, the holding voltage V _{h2 is} much lower than the holding voltage V _h1 of the single turning device, indicating that another current conducting path is activated.

Another conventional method places a guard ring structure between the one or more diodes and the turning device to capture holes and electrons flowing in the substrate, thereby inhibiting the additional current conducting path from being activated. Although the added guard ring structure can assist the one or more diodes to achieve the intended purpose, it may occupy a large amount of layout area for providing the guard ring structure itself and additional layout spacing.

Therefore, how to design an electrostatic discharge circuit with adjustable holding voltage with a small layout area is an important issue.

The object of the present invention is to provide an electrostatic discharge protection circuit having a well embedded in a substrate having a conductivity type opposite to that of the substrate, and the well surrounding is used to dissipate static electricity. A turning device for discharging current. Additionally, a doped region is formed in the well and electrically coupled to a voltage pad that is more likely to introduce an electrostatic discharge current to the protection circuit during forward electrostatic discharge. After the isolation of the well, the holding voltage of the ESD protection circuit can be adjusted by adjusting the number of diodes in the diode string without the protection ring, and the voltage of the self-turning device is increased, thereby saving Layout area.

In order to achieve the above object, the present invention can be electrically coupled between a first pad and a second pad by providing an electrostatic discharge protection circuit. In a normal operating state, the voltage applied to the first pad is higher than the voltage applied to the second pad. The ESD protection circuit includes a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type; a turning device surrounded by the first well; and a diode string located in the substrate. The first well is coupled to the first pad. The diode string is connected in series with the turning device and is separated from the first well. The serially connected diode strings and the turning device are coupled between the first pad and the second pad.

In order to achieve the above object, the present invention can be electrically coupled between a first pad and a second pad by providing an electrostatic discharge protection circuit. In a normal operating state, the voltage applied to the first pad is higher than the voltage applied to the second pad. The ESD protection circuit includes a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type; a device well located in the first well and having a first conductivity type; and one located in the device well and having a first doped region of a second conductivity type; a second doped region in the device well and having a second conductivity type; a first gate between the first and second doped regions and above the device well; And at least one diode region. Each of the diode regions includes a diode well located in the substrate; a third doped region having a first conductivity type in the diode well; and a second conductivity type in the diode well The fourth doping region. The first well is coupled to the first pad. The device well is coupled to the second pad. The second doping region and the first gate are both coupled to the second pad. The at least one diode region is connected in series with the first doped region, and the first doped region is coupled to the first pad.

In order to achieve the above object, the present invention can be electrically coupled between a first pad and a second pad by providing an electrostatic discharge protection circuit. In a normal operating state, the voltage applied to the first pad is higher than the voltage applied to the second pad. The ESD protection circuit comprises a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type; a first device well located in the first well and having a first conductivity type; a second device well having a second conductivity type in the device well; a first doped region having a first conductivity type in the second device well; and a second doping having a second conductivity type in the first device well Zone; and at least one diode region. Each of the diode regions includes a diode well located in the substrate; a third doped region having a first conductivity type in the diode well; and a second conductivity type in the diode well The fourth doping region. The first well is coupled to the first pad. The first device well and the second device well are coupled to the second pad and the first pad, respectively. The first doped region is coupled to the first pad. The at least one diode region is connected in series with the second doped region, and the second doped region is coupled to the second pad.

The invention is described more fully hereinafter with reference to the embodiments of the invention and the accompanying drawings. The various exemplifications set forth herein are intended to be considered as a contin The word "or" used in the specification is a connection term, but is "and/or". In addition, the article "a" can be regarded as singular or plural. The term "coupled" or "connected" may mean direct or indirect transmission between components. Other components are connected.

FIG. 3 is a schematic diagram showing an equivalent circuit of an electrostatic discharge protection circuit 1 according to an embodiment of the present disclosure. The circuit 1 can be incorporated into a semiconductor circuit and electrically coupled to a first pad 110, an internal circuit 120, and a second pad 130. In a normal operating state, the voltage applied to the first pad 110 is higher than the voltage applied to the second pad 130. According to an embodiment, the first pad 110 is an input pad or a high voltage pad, and the second pad 130 is a ground pad. According to other embodiments, the first pad 110 may be a VDD1 pad and the second pad 130 may be a VDD2 pad, or the first pad 110 may be a VSS1 pad and the second pad 130 may be a VSS2 pad. By incorporating the electrostatic discharge protection circuit 1, the internal circuit 120 can be protected from damage by electrostatic discharge or other electrical power. The circuit 1 includes a turning device 11 and a diode string 12 connected in series with the turning device 11 to conduct an electrostatic discharge current introduced from the first pad 110 to the second pad 130. When excessive electrical stress occurs, the turning device 11 exhibits a turning characteristic as described above. In the circuit 1, the turning device 11 is a ground-gate NMOS (ggNMOS), wherein the source of the NMOS is coupled to the second pad 130, and the drain of the NMOS is transmitted through the diode string 12 It is coupled to the first pad 110. By adjusting the number of diodes in the diode string 12, the holding voltage of the ESD protection circuit 1 can be raised from the holding voltage of the turning device 11 to a voltage higher than that applied to the first pad 110 under normal operating conditions, for example 10.5 volts. In addition, the ESD protection circuit 1 may include a reverse diode 13 for conducting an electrostatic discharge current introduced from the second pad 130 to the first pad 110.

FIG. 4 illustrates a semiconductor structure of an electrostatic discharge protection circuit 2 according to another embodiment of the present disclosure. The electrostatic discharge protection circuit 2 is electrically coupled to the first A pad 110 is interposed between the second pad 130. In a normal operating state, the voltage applied to the first pad 110 is higher than the voltage applied to the second pad 130. The ESD protection circuit 2 includes a substrate 100, a first well 200, a turning device 21, and a diode string 12. In this embodiment, the substrate 100 has a first conductivity type; the first well 200 having the second conductivity type is located in the substrate 100, wherein the first well 200 is coupled to the first pad 110; and the turning device 21 is configured by the first well Enclosed by 200; the diode string 12 is disposed in the substrate 100, is connected in series with the turning device 21, and is separated from the first well 200, wherein the serially connected diode strings 12 and the turning device 21 are coupled to the first Between the pad 110 and the second pad 130. In this embodiment, the first conductivity type is opposite to the second conductivity type. In the present embodiment, the first well 200 is coupled to the first pad 110 via a higher concentration doping region 240 having a second conductivity type in the first well 200. The substrate 100 is coupled to the second pad 130 via a higher concentration doping region 250 having a first conductivity type in the substrate 100.

Referring to FIG. 4, in the embodiment, the first conductivity type is P type, and the second conductivity type is N type. In this embodiment, the turning device 21 is a ggNMOS. The turning device 21 includes a first NMOS, wherein the first NMOS includes a device well 211 located in the first well 200 and having a first conductivity type, and a drain 212, a source 214 and a substrate in the device well 211 a terminal 215, and a gate 213 above the device well 211, wherein the first NMOS gate 213, the source 214 and the base end 215 are coupled to the second pad 130, and the first NMOS drain 212 is transmitted through the diode The body string 12 is coupled to the first pad 110.

Referring to FIG. 4, by surrounding the turning device 21 in the first well 200 coupled to the first pad 110, the holding voltage of the ESD protection circuit 2 can be raised from the holding voltage of the turning device 21 to be higher than normal operation. Applied to the state The voltage of a pad 110. FIG. 7 includes an example of a cross-sectional structure of the diode string 12 shown in FIG. Referring to FIG. 4 and FIG. 7 together, if the first well 200 is not present, the P+ doping region 222-1 and the N well 221-1 in the diode string 22, and the PNP BJT battery formed by the P substrate 100. The crystal, and the NPN BJT transistor formed by the N well 221-1, the P substrate 100 and the NMOS source 214, will form a parasitic SCR-Spillar Rectifier (SCR) path. The PNP BJT transistor and the NPN BJT transistor form a positive feedback structure that may enter a state of generating a regenerative current to cause the holding voltage of the turning device 21 to drop. By surrounding the turning device 21 in the first well 200 coupled to the first pad 110, the parasitic SCR path can be blocked, and the holding voltage of the ESD protection circuit 2 can be maintained without using a conventional guard ring structure. The holding voltage of the turning device 21 is raised to a voltage higher than that applied to the first pad 110 under normal operating conditions. If the guard ring structure is used, there will be another N well having an N+ doped region and a P+ doped region disposed in the P substrate 100 region between the diode string 12 and the turning device 21.

Referring to FIG. 4, a contact surface of the substrate 100 and the first well 200 is additionally formed with a diode, wherein the conduction direction of the diode is from the perspective of the first pad 110 and the diode string 12 The conduction direction is opposite. In this embodiment, the first well 200 is directly coupled to the first pad 110 by directly connecting the N+ doping region 240 to the first pad 110.

In this embodiment, a main discharge path of at least two electrostatic discharge currents is provided to dissipate electrostatic discharge currents from different directions. When an electrostatic discharge current is introduced from the first pad 110, it may be referred to as forward electrostatic discharge, static electricity. The discharge path of the discharge current will pass through the diode string 12 and the turning device 21 The first NMOS drain 212, the device well 211 and the source 214 are connected to the second pad 130. Conversely, if the electrostatic discharge current is introduced from the second pad 130 and is referred to herein as a negative voltage electrostatic discharge, the discharge path of the electrostatic discharge current passes through the substrate 100 and the first well 200 to the first pad 110. The present disclosure eliminates the need to additionally reserve an excess area by embedding the first well 200 in the substrate 100 of opposite conductivity type and surrounding the turning device 21, and directly coupling the first well 200 to the first pad 110. To accommodate a reverse diode for negative voltage type electrostatic current discharge.

FIG. 5 illustrates another embodiment of the disclosure. The turning device 21 further includes a second NMOS being overlapped with the first NMOS. The difference between this embodiment and the embodiment shown in FIG. 4 is that the turning device 21 includes a second NMOS other than the first NMOS. The second NMOS is overlapped with the first NMOS, that is, the first NMOS and the second NMOS share device well 211, and one source of the second NMOS is substantially shared with the first NMOS. One of the second NMOS drains 216 is coupled to the first pad 110 through the diode string 12, and one of the second NMOS gates 217 receives a control voltage V _Ctrl to reduce the trigger voltage of the turning device 21. In this embodiment, the control voltage V _Ctrl is equal to VDD.

FIG. 6 illustrates another embodiment of the present disclosure, in which the first well 200 is coupled to the first pad 110 through the diode string 12 . The difference between this embodiment and the embodiment shown in FIG. 4 is that the first well 200 is coupled to the first pad 110 through the diode string 12 instead of being directly coupled to the first pad 110.

FIG. 7 and FIG. 8 respectively illustrate two embodiments of the present disclosure, wherein one of the diode strings 22 includes a single diode, and the other of the diode strings 22 includes a plurality of diodes. body. Please refer to Figure 7 and Figure 8, together with the diode. The string 22 comprises an anode 222-1 at one end and a cathode 223-n at one end, wherein in the example shown in Figure 7, n = 1, in the example shown in Figure 8, n = 3. The terminal anode 222-1 is coupled to the first pad 110, and the terminal cathode 223-n is coupled to the first NMOS drain 212.

FIG. 9 illustrates another embodiment of the present disclosure that surrounds the diode string 32 with a second well 300. The second well 300 having the second conductivity type is embedded in the substrate 100 and coupled to the first pad 110. The diode string 32 is surrounded by the second well 300, and each of the diode strings 32 includes a diode well 321-x having a first conductivity type, and a diode 321-x in a diode body. The anode 322-x; and a cathode 323-x located in the diode well 321-x, where x represents the xth diode in the diode string 32. In the present embodiment, the second well 300 is coupled to the first pad 110 through a higher concentration doping region 340 having a second conductivity type disposed in the second well 300.

The difference between the embodiment shown in FIG. 8 and FIG. 9 is that the diode string 22 in FIG. 8 is directly embedded in the substrate 100, and the diode string 32 in FIG. 9 is surrounded by the second well 300 and embedded in In the substrate 100. In normal operation, a bias is applied to the first pad 110 to drive the internal circuitry, and the protection circuit 2, which is ideally electrically coupled to the first pad 110, should be non-conductive to avoid power consumption. The N well 221-x of each of the diodes 22 shown in FIG. 8 is replaced with a P well 321-x as shown in FIG. 9, and the diode string 32 is coupled to the diode string 32. The N well 300 of the first pad 110 is surrounded, and the potential difference between the P well 321-x and the N well 300 interface can form a barrier to prevent leakage current from the P well 321-x from entering the N well 300. For the first diode in the diode string 32, the potential between the P-well 321-1 and the N-well 300 is comparable, but for the second and other subsequent in the diode string 32 In the case of connected diodes, the potential difference between the P-well 321-x and the N-well 300 interface will have a larger potential difference from each other due to the series voltage drop, and thus a larger barrier will be formed outside the diode. . Additionally, by adjusting the doping concentration or profile in each well, this embodiment can provide a larger barrier to reduce leakage current. Therefore, the embodiment shown in FIG. 9 can not only achieve an adjustable holding voltage without using a guard ring structure, but also reduce energy consumption in normal operation.

Figure 10 is a diagram showing an equivalent circuit diagram of an electrostatic discharge protection circuit 4 in accordance with an embodiment of the present disclosure. The circuit 4 can be added to a semiconductor circuit and electrically coupled to a first pad 110, an internal circuit 120 and a second pad 130. In a normal operating state, the voltage applied to the first pad 110 is higher than the voltage applied to the second pad 130. According to an embodiment, the first pad 110 is an input pad or a high voltage pad, and the second pad 130 is a ground pad. According to other embodiments, the first pad 110 may be a VDD1 pad and the second pad 130 may be a VDD2 pad, or the first pad 110 may be a VSS1 pad and the second pad 130 may be a VSS2 pad. By incorporating the electrostatic discharge protection circuit 4, the internal circuit 120 can be protected from damage by electrostatic discharge or other electrical power. The circuit 4 includes a turning device 41 and a diode string 42 connected in series with the turning device 41 to conduct an electrostatic discharge current introduced from the first pad 110 to the second pad 130. When excessive electrical stress occurs, the turning device 41 exhibits a turning characteristic as described above. In the circuit 4, the turning device 11 is a Low-Voltage Triggered Silicon-Controlled Rectifier (LVTSCR), wherein an anode (P+) region of the low voltage triggering rectifier rectifier is coupled to the second pad 130. The cathode (P+) region of the low voltage triggered chirp rectifier is coupled to the first pad 110 through the diode string 42. Via adjustment diode The number of diodes in the string 42 and the holding voltage of the ESD protection circuit 4 can be raised from the holding voltage of the turning device 41 to a voltage higher than the voltage applied to the first pad 110 in the normal operating state, for example, 10.5 volts. In addition, the ESD protection circuit 4 may include a reverse diode 43 for conducting an electrostatic discharge current introduced from the second pad 130 to the first pad 110.

FIG. 11 illustrates a semiconductor structure of an electrostatic discharge protection circuit 5 according to another embodiment of the present disclosure. The ESD protection circuit 5 is electrically coupled between the first pad 110 and the second pad 130. In a normal operating state, the voltage applied to the first pad 110 is higher than the voltage applied to the second pad 130. The ESD protection circuit 5 includes a substrate 100, a first well 500, a turning device 51, and a diode string 42. In this embodiment, the substrate 100 has a first conductivity type; the first well 500 having the second conductivity type is located in the substrate 100, wherein the first well 500 is coupled to the first pad 110; and the turning device 51 is configured by the first well Surrounded by 500; the diode string 42 is disposed in the substrate 100, is connected in series with the turning device 51, and is separated from the first well 500, wherein the serially connected diode string 42 and the turning device 51 are coupled to the first Between the pad 110 and the second pad 130. In this embodiment, the first conductivity type is opposite to the second conductivity type. In the present embodiment, the first well 500 is coupled to the first pad 110 via a higher concentration doping region 540 having a second conductivity type in the first well 500. The substrate 100 is coupled to the second pad 130 via a higher concentration doping region 250 having a first conductivity type in the substrate 100.

Referring to FIG. 11, in the embodiment, the first conductivity type is a P type, and the second conductivity type is an N type. In this embodiment, the turning device 51 is an LVTSCR. The turning device 51 includes a P well 511 located in the N-type first well 500, an N well 512 located in the P well 511, an anode region 514 located in the N well 512, and a cathode region located in the P well 511. 517. P well 511 and cathode region 517 are coupled to second pad 130, and N well 512 and anode region 514 are coupled to first pad 110. In the present embodiment, the cathode region 517 is coupled to the second pad 130 through the diode string 42. The LVTSCR is formed of a PNP BJT transistor composed of a P+ anode region 514, an N well 512, and a P well 511, and an NPN BJT transistor composed of an N well 512, a P well 511, and an N+ cathode region 517. The base and collector of the PNP BJT transistor are coupled to the collector and base of the NPN BJT transistor, respectively. In addition, in order to make the trigger voltage of the LVTSCR low enough to provide a suitable electrostatic discharge protection, the LVTSCR in this embodiment further includes an NMOS, and the drain 515 is disposed above the interface between the N well 512 and the P well 511. Its gate 516 receives a control voltage V _Ctrl and its source shares the same N+ doped region as the cathode region 517 of the LVTSCR. The higher the control voltage V _Ctrl applied to the gate 516 of the NMOS, the lower the trigger voltage at which the LVTSCR is turned on. In the present embodiment, the N well 512 is coupled to the first pad 110 through an N+ doping region 513 located in the N well 512, and the P well 511 is transmitted through a P+ doping region 518 located in the P well 511. A pad 130 is coupled.

Referring to FIG. 11 , by enclosing the turning device 51 in the first well 500 coupled to the first pad 110 , the holding voltage of the ESD protection circuit 5 can be raised from the holding voltage of the turning device 51 to be higher than normal operation. The voltage applied to the first pad 110 in the state. FIG. 12 includes an example of a cross-sectional structure of the diode string 42 shown in FIG. Referring to FIG. 11 and FIG. 12 together, if the first well 500 is not present, the P+ doping region 514 and the N well 512 in the LVTSCR, and the PNP BJT transistor formed by the P substrate 100, and the N well in the LVTSCR. NP, N substrate 521-1 formed by the P substrate 100 and the diode in the diode string 52 The BJT transistor will form a parasitic SCR path. The PNP BJT transistor and the NPN BJT transistor form a positive feedback structure that may enter a state of generating a regenerative current to cause the holding voltage of the turning device 51 to drop. By surrounding the turning device 51 in the first well 500 coupled to the first pad 110, the parasitic SCR path can be blocked, and the holding voltage of the ESD protection circuit 5 can be maintained without using a conventional guard ring structure. The holding voltage of the turning device 51 is raised to a higher voltage than that applied to the first pad 110 in the normal operating state. If the guard ring structure is used, there will be another N well having an N+ doped region and a P+ doped region disposed in the P substrate 100 region between the turning device 51 and the diode string 42.

Referring to FIG. 11 , a contact surface of the substrate 100 and the first well 500 is additionally formed with a diode, wherein the conduction direction of the diode is from the perspective of the first pad 110 and the diode string 42 . The conduction direction is opposite.

In this embodiment, a main discharge path of at least two electrostatic discharge currents is provided to dissipate the electrostatic discharge current from different directions. When an electrostatic discharge current is introduced from the first pad 110, that is, a positive electrostatic discharge, an electrostatic discharge current The discharge path triggers the anode region 514, the N well 512, the P well 511, and the cathode region 517 of the pilot rectifier, and the diode string 42, to the second pad 130 via a low voltage. Conversely, if the electrostatic discharge current is introduced from the second pad 130, that is, the negative voltage electrostatic discharge, the discharge path of the electrostatic discharge current passes through the substrate 100, the first well 500, to the first pad 110. The present disclosure eliminates the need to additionally reserve an excess area by embedding the first well 500 in the substrate 100 of opposite conductivity type and surrounding the turning device 51, and directly coupling the first well 500 to the first pad 110. To accommodate one for negative pressure type static electricity The reverse diode of current discharge.

12 and FIG. 13 respectively illustrate two embodiments of the present disclosure, wherein one of the diode strings 52 includes a single diode, and the other of the diode strings 52 includes a plurality of diodes. body. Referring to FIG. 12 and FIG. 13 together, the diode string 52 includes an anode 522-1 and an anode 523-n, wherein in the example shown in FIG. 12, n=1, in the example shown in FIG. n=3. The terminal anode 522-1 is coupled to the cathode region 517 of the turning device, and the terminal cathode 223-n is coupled to the second pad 130.

FIG. 14 illustrates another embodiment of the present disclosure that surrounds the diode string 62 with a second well 600. The second well 600 having the second conductivity type is embedded in the substrate 100 and coupled to the first pad 110. The diode string 62 is surrounded by the second well 600, and each of the diode strings 62 includes a diode well 621-x having a first conductivity type, and a diode body 621-x at the diode body. The anode 622-x; and a cathode 623-x at the diode well 621-x, where x represents the xth diode in the diode string 62. In the present embodiment, the second well 600 is coupled to the first pad 110 through a higher concentration doping region 640 having a second conductivity type disposed in the second well 600.

The difference between the embodiment shown in FIG. 13 and FIG. 14 is that the diode string 52 in FIG. 13 is directly embedded in the substrate 100, and the diode string 32 in FIG. 14 is surrounded by the second well 600 and embedded in In the substrate 100. In normal operation, a bias is applied to the first pad 110 to drive the internal circuitry, and the protection circuit 5, which is ideally electrically coupled to the first pad 110, should be non-conductive to avoid power consumption. The N well 521-x of each of the diodes 52 shown in FIG. 13 is replaced with a P well 621-x as shown in FIG. 14, and the diode string 62 is coupled to the diode string 62. the first The N well 600 of the pad 110 is surrounded, and the potential difference between the P well 621-x and the N well 600 interface can form a barrier to prevent leakage current from the P well 621-x from entering the N well 600. For the first diode in the diode string 62, the potential between the P well 621-1 and the N well 600 is comparable, but for the second and other subsequent connections in the diode string 62 In polar body, the difference in potential between the interface of P-well 621-x and N-well 600 may cause a larger potential difference between each other due to the voltage drop in series, and thus a larger barrier is formed outside the dipole. Additionally, by adjusting the doping concentration or profile in each well, this embodiment can provide a larger barrier to reduce leakage current. Therefore, the embodiment shown in FIG. 13 can not only achieve an adjustable holding voltage without using a guard ring structure, but also reduce energy consumption during normal operation.

FIG. 15 illustrates another embodiment of the present disclosure, in which the second well 600 is coupled to the first pad 110 through the turning device 51 (shown in FIG. 11). The difference between this embodiment and the embodiment shown in FIG. 14 is that the second well 600 is coupled to the first pad 110 through the turning device 51 instead of being directly coupled to the first pad 110.

Referring to Figure 7, there is shown a cross-sectional view of an electrostatic discharge protection circuit 2 in one embodiment of the present disclosure. The ESD protection circuit 2 is electrically coupled between the first pad 110 and the second pad 130. In a normal operating state, the voltage applied to the first pad 110 is higher than the voltage applied to the second pad 130. The ESD protection circuit 2 includes a substrate 100 having a first conductivity type; a first well 200 located in the substrate 100 and having a second conductivity type, wherein the first well 200 is coupled to the first pad 110; 200 has a device well 211 of a first conductivity type, wherein the device well 211 is coupled to the second pad 130; a first doping region 212 located in the device well 211 and having a second conductivity type; and a device well 211 And have a second doped region 214 of a second conductivity type; a first gate 213 located above the first and second doped regions (212 and 214) and the device well 211, wherein the first gate 213 and the second pad 130 Coupling; and at least one diode region 22. Each of the diode regions includes a diode well 221-1 located in the substrate 100; a third doped region 222-1 having a first conductivity type in the diode well 221-1; and a The second doping region 223-1 of the second conductivity type is in the diode well 221-1, wherein the at least one diode region 22 is connected in series with the first doping region 212, and the first doping is performed. The region 212 is coupled to the first pad 110. In the present embodiment, the first well 200 is coupled to the first pad 110 via a higher concentration doping region 240 having a second conductivity type in the first well 200. The substrate 100 is coupled to the second pad 130 via a higher concentration doping region 250 having a first conductivity type in the substrate 100.

Referring to FIG. 7 , by enclosing the device well 211 in the first well 200 coupled to the first pad 110 , the holding voltage of the ESD protection circuit 2 can be adjusted to be higher than normal operation without the assistance of the conventional guard ring structure. The voltage applied to the first pad 110 in the state. If the guard ring structure is used, it will be disposed in the region of the P substrate 100 between the at least one diode region 22 and the first doping region 212. The holding voltage of the ESD protection circuit 2 can be adjusted by adjusting the number of diodes in the at least one diode region 22, such as shown in FIGS. 7 and 8.

Referring to FIG. 7, in the present embodiment, paths for dissipating both the forward electrostatic discharge current and the negative voltage electrostatic discharge current are respectively provided. In the case of forward electrostatic discharge, the discharge process of the electrostatic discharge current is sequentially from the first pad 110, through the at least one diode region 22, the first doping region 212, and the device well 211. And the second doping region 214 to the second pad 130. Conversely, in the case of negative voltage electrostatic discharge, the discharge process of the electrostatic discharge current is sequentially from the second pad 130, through the substrate 100 and the first well 200, to the first pad 110.

With continued reference to FIG. 8, a cross-sectional view of the ESD protection circuit 2 in another embodiment of the present disclosure is shown. In this embodiment, the ESD protection circuit 2 further includes a fifth doping region 216 having a second conductivity type in the device well 211; and a fifth doping region 216 and the first doping region 212 and a second gate 217 above the device well 211, wherein the at least one diode region 22 is connected in series with the fifth doping region 216, and the fifth doping region 216 is coupled to the second pad 130, and the second gate The pole 217 receives a control voltage. In this embodiment, the control voltage is equal to VDD.

Referring to FIG. 8 , in the embodiment, the first well 200 is coupled to the first pad 110 by being coupled to the fourth doping region 223-x of any of the diode regions, instead of being as shown in FIG. 7 . Directly coupled to the first pad 110.

FIG. 9 illustrates another embodiment of the present disclosure that surrounds the at least one diode region 32 with a second well 300. The second well 300 having the second conductivity type is embedded in the substrate 100 and coupled to the first pad 110. In this embodiment, the potential difference between the interface of the device well 321-x and the second well 300 can form a barrier to prevent leakage current from the device well 321-x from entering the substrate 100.

In the above embodiment, the first conductivity type may be a P type, and the second conductivity type may be an N type.

Referring to Figure 12, there is shown a cross-sectional view of an electrostatic discharge protection circuit 5 in one embodiment of the present disclosure. The ESD protection circuit 5 is electrically coupled between the first pad 110 and the second pad 130. Applied to the first in a normal operating state The voltage of the pad 110 is higher than the voltage applied to the second pad 130. The ESD protection circuit 5 includes a substrate 100 having a first conductivity type; a first well 500 located in the substrate 100 and having a second conductivity type, wherein the first well 500 is coupled to the first pad 110; a first device well 511 having a first conductivity type, wherein the first device well 511 is coupled to the second pad 130; and a second device well 512 is disposed in the first device well 511 and has a second conductivity type. The second device well 512 is coupled to the first pad 110; the first doping region 514 is disposed in the second device well 512 and has a first conductivity type, wherein the first doping region 514 is coupled to the first pad 110. a second doped region 517 located in the first device well 511 and having a second conductivity type; and at least one diode region 52. Each of the diode regions includes a diode well 521-1 located in the substrate 100; a third doped region 522-1 having a first conductivity type in the diode well 521-1; and a The second doping region 523-1 of the second conductivity type is in the diode well 521-1, wherein the at least one diode region 52 is connected in series with the second doping region 517, and the second doping is performed. The region 517 is coupled to the second pad 130. In the present embodiment, the first well 500 is coupled to the first pad 110 via a higher concentration doping region 540 having a second conductivity type in the first well 500. The substrate 100 is coupled to the second pad 130 via a higher concentration doping region 550 having a first conductivity type in the substrate 100. In the present embodiment, the second device well 512 is coupled to the first pad 110 via a higher concentration doping region 513 having a second conductivity type in the second device well 512; and the first device well 511 is via the first device A higher concentration doping region 518 having a first conductivity type is coupled to the second pad 130 in a device well 511

Referring to FIG. 12, by enclosing the device well 511 in the first well 500 coupled to the first pad 110, the holding voltage of the ESD protection circuit 5 can be With the aid of a conventional guard ring structure, the voltage applied to the first pad 110 is adjusted above the normal operating state. If the guard ring structure is used, it will be disposed in the P substrate 100 region between the at least second doped region 517 and a diode region 52. The holding voltage of the ESD protection circuit 5 can be adjusted by adjusting the number of diodes in the at least one diode region 52, such as shown in FIGS. 12 and 13.

Referring to FIG. 12, in the present embodiment, paths for dissipating both the forward electrostatic discharge current and the negative voltage electrostatic discharge current are respectively provided. In the case of forward electrostatic discharge, the discharge process of the electrostatic discharge current is sequentially from the first pad 130, through the first doping region 514, the second device well 512, the first device well 511, and the second doping region 517. And the at least one diode region 52 to the second pad 130. Conversely, in the case of negative voltage electrostatic discharge, the discharge process of the electrostatic discharge current is sequentially from the second pad 130, through the substrate 100 and the first well 500, to the first pad 110.

With continued reference to FIG. 12, a cross-sectional view of the ESD protection circuit 5 in another embodiment of the present disclosure is shown. In this embodiment, the ESD protection circuit 5 further includes a fifth doping region 515 located above the first and second device wells (511 and 512) and having a second conductivity type; and a fifth doping region A gate 516 between the 515 and the second doping region 517 and above the first device well 511, wherein the gate receives a control voltage V _Ctrl . When the control voltage V _{Ctrl is} higher, the electrostatic discharge protection circuit 5 is made easier to turn on for current discharge.

FIG. 14 illustrates another embodiment of the present disclosure that surrounds the at least one diode region 62 with a second well 600. The second well 600 having the second conductivity type is embedded in the substrate 100 and coupled to the first pad 110. In this embodiment The potential difference between the interface of the device well 621-x and the second well 600 can form a barrier to prevent leakage current from the device well 621-x from entering the substrate 100.

FIG. 15 illustrates another embodiment of the present disclosure. The second well 600 is coupled to the first pad 110 by being coupled to the second doping region 517 instead of directly to the first device as shown in FIG. 14 . The pad 110 is coupled.

In the above embodiment, the first conductivity type may be a P type, and the second conductivity type may be an N type.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the present invention should be construed as being limited by the scope of the appended claims

1‧‧‧Electrostatic discharge protection circuit

100‧‧‧Substrate

11‧‧‧ turning device

110‧‧‧First pad

12‧‧‧Diode string

120‧‧‧Internal circuits

13‧‧‧Reverse diode

130‧‧‧second pad

2‧‧‧Electrostatic discharge protection circuit

200‧‧‧First Well

21‧‧‧ turning device

211‧‧‧ device well

212‧‧‧The first NMOS bungee

213‧‧‧The gate of the first NMOS

214‧‧‧Source of the first NMOS

215‧‧‧The base of the first NMOS

216‧‧‧Second NMOS bungee

217‧‧‧Second NMOS gate

22‧‧‧Diode string

221-1, 221-2, 221-3‧‧‧ diode wells

222-1, 222-2, 222-3‧‧‧ anode

223-1, 223-2, 223-3‧‧‧ cathode

240‧‧‧Second Conductive Doped Area

250‧‧‧First Conductive Doped Area

300‧‧‧Second well

32‧‧‧Diode string

321-1, 321-2, 321-3‧‧‧ diode wells

322-1, 322-2, 322-3‧‧‧ anode

323-1, 323-2, 323-3‧‧‧ cathode

340‧‧‧Second conductive doped region

4‧‧‧Electrostatic discharge protection circuit

41‧‧‧ turning device

42‧‧‧Diode string

43‧‧‧Reverse diode

5‧‧‧Electrostatic discharge protection circuit

500‧‧‧First Well

51‧‧‧Transfer device

511‧‧‧First device well

512‧‧‧Second device well

513‧‧‧Second Conductive Doped Area

514‧‧‧Anode area

515‧‧‧ NMOS bungee

516‧‧‧ NMOS gate

517‧‧‧ cathode area

518‧‧‧First Conductive Doped Area

52‧‧‧Diode string

521-1, 521-2, 521-3‧‧‧ diode wells

522-1, 522-2, 522-3‧‧‧ anode

523-1, 523-2, 523-3‧‧‧ cathode

540‧‧‧Second conductive doped region

550‧‧‧First Conductive Doped Area

600‧‧‧Second well

62‧‧‧Diode string

621-1, 621-2, 621-3‧‧‧ diode wells

622-1, 622-2, 622-3‧‧‧ anode

623-1, 623-2, 623-3‧‧‧ cathode

640‧‧‧Second conductive doped region

Figure 1 shows a current-voltage graph of a turning device having a turning characteristic; Figure 2 shows a current-voltage curve of a single turning device and a current-voltage curve of a turning device with a diode.

3 is an equivalent circuit diagram of an electrostatic discharge protection circuit in an embodiment; FIG. 4 illustrates a semiconductor structure of an electrostatic discharge protection circuit in an embodiment; and FIG. 5 illustrates an electrostatic discharge in another embodiment. Protecting the semiconductor structure of the circuit; 6 is a semiconductor structure of an ESD protection circuit in another embodiment; FIG. 7 is a cross-sectional view showing an ESD protection circuit in an embodiment; FIG. 8 is an ESD protection circuit in another embodiment; FIG. 9 is a cross-sectional view showing an ESD protection circuit in another embodiment; FIG. 10 is a schematic diagram showing an equivalent circuit of an ESD protection circuit in another embodiment; FIG. 12 is a cross-sectional view showing an ESD protection circuit in an embodiment; FIG. 13 is a cross-sectional view showing an ESD protection circuit in another embodiment; A cross-sectional view of an ESD protection circuit in an embodiment; and FIG. 15 is a cross-sectional view of the ESD protection circuit in still another embodiment.

100‧‧‧Substrate

110‧‧‧First pad

12‧‧‧Diode string

130‧‧‧second pad

2‧‧‧Electrostatic discharge protection circuit

200‧‧‧First Well

21‧‧‧ turning device

211‧‧‧ device well

212‧‧‧The first NMOS bungee

213‧‧‧The gate of the first NMOS

214‧‧‧Source of the first NMOS

215‧‧‧The base of the first NMOS

240‧‧‧Second Conductive Doped Area

250‧‧‧First Conductive Doped Area

Claims (22)

An ESD protection circuit is coupled between a first pad and a second pad. In a normal operating state, a voltage applied to the first pad is higher than a voltage applied to the second pad, wherein the electrostatic discharge The protection circuit includes: a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type, wherein the first well is coupled to the first pad; and the first well is surrounded by the first well a snapback device; and a diode string in the substrate, in series with the folding device, and separated from the first well, wherein the first well is coupled to the first pad or One of the diode strings is coupled to the cathode. The electrostatic discharge protection circuit of claim 1, wherein the diode string comprises at least one diode, and the number of diodes in the diode string is set to hold the electrostatic discharge protection circuit The holding voltage is higher than the voltage applied to the first pad in the normal state. The ESD protection circuit of claim 1, wherein the turning device comprises a first NMOS, wherein the first NMOS comprises a device well located in the first well and having a first conductivity type, located in the device well a first drain, a first source, and a base end, and a first gate above the well of the device, and the first gate, the first source, and the first NMOS The base end is coupled to the second pad. The ESD protection circuit of claim 3, wherein the turning device further comprises: a second NMOS overlapped with the first NMOS, wherein the first The NMOS and the second NMOS share the device well, and a second drain of the second NMOS is coupled to the first pad through the diode string, and a second gate of the second NMOS receives a control voltage. And one of the sources of the second NMOS is substantially shared with the second port of the first NMOS. The electrostatic discharge protection circuit of claim 3, further comprising: a second well located in the substrate and having a second conductivity type, wherein the second well is coupled to the first pad, the pole The body string is surrounded by the second well, and each of the diode strings comprises: a diode well having a first conductivity type; an anode located in the diode body; and a a cathode of the diode well, wherein an anode is coupled to the first pad and a cathode is coupled to the first drain of the first NMOS. The electrostatic discharge protection circuit of claim 3, wherein a discharge process of an electrostatic discharge current is sequentially from the first pad, through the diode string, the first drain of the first NMOS The device well and the first source to the second pad. The electrostatic discharge protection circuit of claim 1, wherein the coupling between the first well and the first pad is directly coupled to the first pad, and the substrate and the second pad are coupled When connected, an electrostatic discharge current discharge process is sequentially from the second pad, through the substrate and the first well, to the first pad. An electrostatic discharge protection circuit according to claim 1, wherein The turning device comprises a Low-Voltage Triggered Silicon-Controlled Rectifier (LVTSCR), the low voltage triggering controlled rectifier comprises an anode region and a cathode region, and the diode string comprises an anode at one end a cathode of one end, the anode region of the low voltage triggering rectifier rectifier is coupled to the first pad, the cathode region of the low voltage triggering rectifier rectifier is coupled to the anode of the diode string, and the diode string The cathode of the terminal is coupled to the second pad. The electrostatic discharge protection circuit of claim 8, further comprising: a second well located in the substrate and having a second conductivity type, wherein the second well is coupled to the first pad, the pole The body string is surrounded by the second well, and each of the diode strings comprises: a diode well having a first conductivity type; an anode located in the diode body; and a The cathode of the diode well. The electrostatic discharge protection circuit of claim 8, wherein a discharge process of the electrostatic discharge current is sequentially from the first pad, and the low voltage triggers the anode region of the rectifier rectifier, and the low voltage triggers the control The cathode region of the rectifier and the string of diodes to the second pad. The electrostatic discharge protection circuit of claim 8, wherein the substrate is coupled to the second pad, and an electrostatic discharge current discharge process is sequentially from the first substrate and the first well to the First pad. An ESD protection circuit is coupled between a first pad and a second pad. In a normal operating state, a voltage applied to the first pad is higher than a voltage applied to the second pad, wherein the electrostatic discharge The protection circuit contains: a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type, wherein the first well is coupled to the first pad; and the first well is in the first well and has a first conductivity type Device well, wherein the device well is coupled to the second pad; a first doped region in the device well having a second conductivity type; and a second doping in the device well having a second conductivity type a region, wherein the second doped region is coupled to the second pad; a first gate between the first and second doped regions and above the device well, wherein the first gate and the first gate a second pad coupled; and at least one diode region, wherein each of the diode regions comprises: a diode well located in the substrate; and a third electrode in the diode body having a first conductivity type a doped region; and a fourth doped region in the diode well having a second conductivity type, wherein the at least one diode region is in series with the first doped region, and the first doping is performed The first pad is coupled to the first pad, wherein the first well is coupled to the first pad directly to the first pad Or contact with any of the fourth doped region of a diode is coupled. The electrostatic discharge protection circuit of claim 12, wherein the number of the diode regions of the at least one diode region is set such that the holding voltage of the electrostatic discharge protection circuit is lower than the normal state. The voltage applied to the first pad is high. The electrostatic discharge protection circuit of claim 12, further comprising: a fifth doped region having a second conductivity type in the device well; and a second gate located in the fifth doped region and the first doping region and above the device well, wherein the at least one The polar body region is connected in series with the fifth doped region, and the fifth doped region is coupled to the first pad, and the second gate receives a control voltage. The electrostatic discharge protection circuit of claim 12, further comprising: a second well located in the substrate and having a second conductivity type, wherein the second well is coupled to the first pad, the at least one The diode region is surrounded by the second well and the diode well has a first conductivity type. The electrostatic discharge protection circuit of claim 12, wherein a discharge process of an electrostatic discharge current is sequentially from the first pad, through the at least one diode region, the first doped region, The device well and the second doped region are to the second pad. The electrostatic discharge protection circuit of claim 12, wherein the coupling between the first well and the first pad is directly coupled to the first pad, and the substrate and the second pad are coupled When connected, an electrostatic discharge current discharge process is sequentially from the second pad, through the substrate and the first well, to the first pad. An ESD protection circuit is coupled between a first pad and a second pad. In a normal operating state, a voltage applied to the first pad is higher than a voltage applied to the second pad, wherein the electrostatic discharge The protection circuit includes: a substrate having a first conductivity type; a first well located in the substrate and having a second conductivity type, wherein the a first well coupled to the first pad; a first device well in the first well having a first conductivity type, wherein the first device well is coupled to the second pad; and a first device well is located in the first device well And having a second device type of the second conductivity type, wherein the second device well is coupled to the first pad; a first doping region located in the second device well and having a first conductivity type, wherein the first The doped region is coupled to the first pad; a second doped region in the first device well and having a second conductivity type; at least one diode region, wherein each of the diode regions includes: a diode well in the substrate; a third doped region in the diode well having a first conductivity type; and a fourth doping region in the diode well having a second conductivity type, wherein The at least one diode region is connected in series with the second doped region, and the second doped region is coupled to the second pad; and a second well located in the substrate and having a second conductivity type, wherein The second well is directly coupled to the first pad or coupled to the first pad by the second doped region. The electrostatic discharge protection circuit of claim 18, wherein the number of the diode regions of the at least one diode region is set such that a holding voltage of the electrostatic discharge protection circuit is applied under the normal state. The voltage at the first pad is high. Such as the electrostatic discharge protection circuit described in claim 18, further The at least one diode region is surrounded by the second well, and the diode well has a first conductivity type. The electrostatic discharge protection circuit of claim 18, wherein a discharge process of an electrostatic discharge current is sequentially from the first pad, through the first doping region, the second device well, and the first The device well, the second doped region, and the at least one diode region are to the second pad. The electrostatic discharge protection circuit of claim 18, wherein a discharge process of an electrostatic discharge current is sequentially from the second pad, through the substrate and the first well, to the first pad.