SE515897C2 - Device and method for a divided buffer - Google Patents

Abstract

The present invention relates to a buffer device of the first-in-first-out type. The buffer device comprises a data inlet, a data outlet and a storage buffer. The buffer device also comprises an integrated circuit, which comprises an input buffer and an output buffer. An arrangement in the buffer device is used to combine the data inlet with the data out via either one of the buffers on the integrated circuit or via at least two of the buffers connected in series.

Description

The data is first read in to the second buffer part and then moved to and read out from the first part.

The requirement for buffer size is met by the second buffer part which is not part of the integrated circuit and thus does not occupy silicon space. Since the first part is built on the same circuit as the data processing part, data can be retrieved from this buffer part without delay. The other problem that remains is input and reading to the buffer part which is separated from the integrated circuit. Since the second buffer part is separated both from the unit from which data is received and the unit to which data is sent, a delay arises compared. with whether these devices have been on the same circuit as the buffer. The requirement is important as the buffer is only for speed specifically contains a few elements.

DISCLOSURE OF THE INVENTION The present invention addresses the problem of creating sufficient memory capacity in a FIFO-type buffer used in an integrated circuit, without taking up unnecessary circuit space and without sacrificing speed.

This problem is solved according to the invention by dividing the buffer device into three buffer parts: An input buffer which is part of the integrated circuit.

- An output buffer that is part of the integrated circuit.

- A memory buffer that is separated from the integrated circuit.

The object of the flexible invention is to create a buffer device which, depending on the data coating in the buffer, can be adapted so that requirements for both speed and memory space are met. In more detail, the buffer device according to the invention comprises a data input and a data output as well as an arrangement for interconnecting the input with the output via either one of the buffer parts or via several of the buffer parts. connected in series. The different FIFO constellations are used in different operating conditions.

Which operating mode is selected depends on the number of elements currently available. is located in the buffer device and in which buffer parts these are distributed. The data input is combined with the data output via different. buffer parts by means of a method according to the invention which comprises the following steps: - merging the data input with the data output via one of the buffers on the integrated circuit; merging the data input with the data output via at least two of the buffers connected in series.

An advantage of the invention is that a large number of data elements can. occupied by the buffer without utilizing circuit space for more than a few elements on the integrated circuit.

Another advantage of the invention is that loading and unloading to / from the buffer can take place at high speed.

Another advantage is that time for moving data can be minimized by access to the separated memory can take place in bursts. Alternatively, by making the bus width to the external memory large.

Yet another advantage is that several buffer devices can efficiently share the same external memory space. .au-- lO 15 20 25. -. . ..- Yet another advantage of the invention is that conflict situations at enrollment and. data readout can be minimized.

The invention will now be described in more detail by means of preferred embodiments and with reference to the accompanying drawings.

DESCRIPTION OF FIGURES Figure 1 shows a block diagram of a buffer device according to the invention.

Figures 2a-c show with block diagram three different operating conditions for the buffer device according to the invention.

Figure 3 shows with a flow diagram a method according to the invention for switching between the different operating conditions of the buffer device.

Figure 4 shows a block diagram of a system of buffer devices according to the invention.

PREFERRED EMBODIMENTS Figure 1 shows a buffer device 1 according to the invention.

The buffer device is of the FIFO type (First ~ In-First-Out), ie the data element that is first entered into the buffer device is first read out from is also the element that the buffer device. The buffer device comprises a data input In to which data elements can be entered.

The buffer device also comprises a data output Out from which data is read out after passing through the buffer.

In addition, the buffer device comprises an integrated circuit part buffer OUTFIFO which according to IC1 which comprises a -.---. The exemplary embodiment can accommodate 8 data elements and an inbuffer INFIFO which can also accommodate 8 data elements. Both the output buffer and the input buffer are: of the FIFO type and form part of the integrated circuit, ie they are part of the silicon of which the integrated circuit is built. Data elements can be entered into and read out from both the output buffer OUTFIFO and the input buffer INFIFO. Registration from the integrated circuit to one of the buffers INFIFO, OUTFIFO can take place without delay because the buffer is part of the integrated circuit. In the same way, readout is made to the integrated circuit from one of the buffers without delay. Registration to the output buffer takes place by activating the output buffer's input OW. Reading from the buffer takes place in the same way by activating the output buffer's OR reading. The buffer device 1 comprises, in addition to the two buffers on the integrated circuit IC1, a further buffer, a so-called memory buffer MEMFIFOl. The memory buffer which is a memory unit separated circuit comprises according to from the integrated embodiment storage possibility for 1024 data elements.

Entering and reading to / from the memory buffer is done using the buffer's input MW and read input MR, respectively.

Entry to and reading from the various buffers OUTFIFO, INFIFO and MEMFIFO1 is handled by a control logic CL1. The control logic CL1 also keeps track of the number of data elements that are in the different buffers INFIFO, OUTFIFO and. MEMFIFOl. A buffer according to the exemplary embodiment comprises four address registers, namely a start address register, a stop address register, a write address register and a read address register. The start and stop address registers keep track of where in the memory the buffer starts and ends. In the start mode, the write address register and read address register are set equal to the start address register. Each write counts up the write address register and each read the value in counts up the read address register. When the writing address register becomes the same as the value in the stop address register, the value in the start address register is entered una .. 10 15 20 25 30 35 545 897 in the writing address register, ie entry takes place from the beginning again. The same happens when the read address register reaches the stop address. There is also a calculator that counts up for writing and down for readings. If this is zero, it is not possible to read anything from the buffer (it is empty) and if the counter is equal to the stop register minus the start register, it is not possible to be full).

The buffer device 1 comprises an arrangement consisting of writing to the buffer (it is different multiplex units. With INFIFO, MEMFIFO1 are connected in different ways in relation to each other, with the help of OUTFIFO and types of multiplex units the buffers so that data elements can pass through different FIFO constellations These constellations will be explained in more detail in connection with figure 2. The data input In is connected to a first demultiplexing unit DMUX1 which comprises two outputs, one output is connected to the input of the input buffer INFIFO.

The second output is connected to one of three inputs on a second demultiplexing unit DMUX2 multiplexing unit MUX1. One also includes one entrance and two exits. The input is connected to the INFIFO output of the input buffer. One of the two outputs is connected to one of the inputs on the multiplexer MUX1 and the other of the two outputs is connected to the MEMFIFO1 input of the memory buffer.

The output of the memory buffer is connected to the remaining of the three inputs on the multiplexer MUX1. The output of the multiplexer is connected to the OUTFIFO input of the output buffer. Which of the outputs with which the input of a demultiplexing unit DMUX1 or DMUX2 is to be combined is determined by the address supplied to the address input DM1 or DM2 of each multiplexing unit. In the same way, the address of an address input M1 determines which of the inputs of the multiplexer MUX1 is to be the output. The address inputs on the DMUX2 are merged with the respective multiplexer DMUX1, and the MUX1 is connected to the control logic CL1. The control logic can thus control which of the outputs in the demultiplexer units DMUX1 and DEMUX2 is 515% 897. -. . .. incoming data shall be directed to, and which input the outgoing data shall come from in the multiplexer MUX1.

Figures 2a-c show the buffer device in figure 1 when it has assumed different operating modes with the aid of the multiplex units. Figure 2a shows a first operating mode. The control logic has in Figure 2a actuated the first demultiplexing unit DMUX1 so that the data input In via the demultiplexing unit is combined with an input 'of the multiplexing unit MUX1. The control logic has also affected the multiplexer MUX1 so that the input is connected to the output buffer connected to the data output Out. In this first operating mode, input II. The output buffer Ol is thus the data input In connected to the data output Out via the output buffer OUTFIFO.

Figure 2b shows a second operating mode. The control logic CL1 has here actuated the first demultiplexing unit DMUX1 so that the data input In is connected to the INFIFO input I2 of the input buffer. The input buffer O2 of the buffer is connected to the input of the DMUX2 of the other demultiplexer. The second demultiplexer DMUX2 has been affected by the control logic CL1 so that a connection is established between the input of the second demultiplexer and one of the MUXI inputs of the multiplexer. The control logic has also actuated the multiplexer MUX1 so that this input is connected to the OUTFIFO input II of the output buffer. In this second operating mode, the data output Out is thus connected via the data input In to the input buffer INFIFO and via the output buffer OUTFIFO.

Figure 2c shows a third operating mode. The control logic CL1 has here actuated the first demultiplexing unit DMUX1 so that the data input In is connected to the INFIFO input I2 of the input buffer. The input buffer O2 of the buffer is connected to the input of the DMUX2 of the other demultiplexer. The second demultiplexer has been affected by the control logic so that a connection is established between the input of the demultiplexer and the MEMFIFOI input of the memory buffer. The output of the memory buffer is, .. «. F 15 connected to one of the MUX1 inputs of the multiplexer and the multiplexer has been actuated by the control logic CL1 so that this input is connected to the O1FIFO input II of the output buffer. In this third operating mode, the data input In is thus connected to the input buffer the data output Out via INFIFO, the memory buffer MEMFIFO1 and the output buffer OUTFIFO.

The first operating mode, where the data input In is connected to the data output Out via the output buffer OUTFIFO, is used when the buffer device is' now or 'only contains' a few data elements "A data element on. the data input In, is moved to the output buffer Il. A negative edge on the write input OW from the control logic enters the data element in the output buffer OUTFIFO and places the element last in a queue. A negative edge on the read input OR reads when desired the data element that is next in line, ie is first in the queue, in the output buffer. Since the buffer device in this operating mode is made up of only one buffer part, which is part of the integrated circuit IC, the transport between data input In and data output Out can take place quickly. The first operating mode can be used as long as the output buffer is not full, less than eight elements, ie contains according to the exemplary embodiment.

In the second operating mode, the data input In is connected to the data output Out via the input buffer INFIFO and the output buffer OUTFIFO. A data element on the data input In is moved to the input buffer where the element is written into the input buffer and placed last in the queue. If the OUTFIFO buffer is not full, ie contains less than eight data elements, the first element in the queue is read from the INFIET buffer) and. the element is moved to the OUTFIFO buffer. then to the output buffer OUTFIFO, where the element is now placed Enrollment is done last in the queue in the output buffer. The buffer device is built in this operating mode. of two buffer parts son: both belong to the integrated circuit IC. The transport between data input In and data output Out therefore takes place without delay. Still 515,897, sufficient speed for the element transactions is achieved through the buffer device. In addition, the device now has room for additional elements compared to the first operating mode.

In the third operating mode, the data input In is connected to the data output Out, via the input buffer INFIFO, the memory buffer the output buffer OUTFIFO. One is moved to the inbuffer now contains four data elements transition takes place to the third inbuffer INFIFO was sent to the memory buffer MEMFIFO1 in MEMFIFO1 and data elements on the data input In the inbuffer INFIFO. About the operating mode. The four data elements in the form of a burst, ie all four elements are written sequentially into a memory area in the memory buffer MEMFIFO1.

A sequential entry of four data elements means that all four elements are written in sequence one after the other, which effectively utilizes memories with enables burst access mode. Showers also group readings and writings so that there are fewer exchanges between them, which makes the utilization of memories in the pipeline more efficient.

The registration is done without interruption, ie without interruption due to reading from the buffer. The four data elements are placed last in the queue in the memory buffer MEMFIFO. If the OUTFIFO buffer has space for four or more data elements, the four data elements that are first in the queue in the memory buffer are read out in burst form. Despite the fact that memory space is now also utilized outside the integrated circuit, sufficient speed is achieved by means of simultaneous transmission of several elements in the form of a burst.

Figure 3 shows a method according to the invention. The figure shows with different blocks the three different operating modes and when the transition takes place between them. The direction from one block to the next is shown in the figure by arrows. Movement from one block symbolizing an operating mode to the next block symbolizing an operating mode is initiated either by a data element being written into the buffer device or by a buffer device. For example, data elements are read out of ø ~ .-. If you are in the third operating mode as shown in Figure 3 with a block 105, then a transition is made to the next block 106 and then on to the next operating mode, either when a data element has been entered into the buffer device or when a data element has been read out from the buffer device. The first operating mode is shown in the figure with a block l0l. The first operating mode means that the data input In is connected to the data output Out via the output buffer OUTFIFO. In the exemplary embodiment, it is assumed that the output buffer comprises seven elements, while both the input buffer INFIFO and the neighbor buffer MEMFIFO1 comprise zero elements. element takes place in block 102 or reading of a figure to a block l02.

When enrolling transfer in, it is checked whether the output buffer now after enrollment or reading comprises eight elements. If the check results in the answer "No", it is moved back to block l0l and the buffer device remains in the first operating mode. If the answer instead results in the answer "Yes", which is the case according to the exemplary embodiment after an entry, ie if the output buffer after entry contains eight elements, the figure is moved to a block 103 and transitioned to the second operating mode. In the second operating mode, the data input In is connected to the data output Out via the input buffer INFIFO and the output buffer OUTFIFO. According to the exemplary embodiment, the output buffer now comprises, after the transaction, eight elements, while the input buffer and the memory buffer do not comprise any elements. The next element transaction, which is a readout from the buffer device, results in the output buffer now comprising seven elements. After the transaction, movement takes place first in block 104 where it comprises four figures to one is checked if the buffer element. Since this is not the case, the figure is moved to one. block 107. In block l07, it is checked whether the buffer comprises zero elements.

Since the input buffer according to the exemplary embodiment comprises the zero figure to block 101 and elements are moved in ...-. The buffer device is put back into the first operating position.

Now assume instead that the buffer device is in operating mode 2 and that the output buffer OUTFIFO comprises eight elements, the input buffer INFIFO comprises 1-3 elements. If the next element transaction is a readout, the device remains in operating mode 2. The read element is the one that was first in the output buffer and the first element in the input buffer is moved to the last position in the output buffer, ie after reading there are 8 elements in the output buffer and O-2 elements in the buffer. If an element is written into the device when the output buffer has 8 elements and the input buffer has less than 3 elements, the new element is placed last in the input buffer and the device remains in operating mode 2. If an element is written into the device when the output buffer has 8 elements and the input buffer has' 3 elements, movement takes place in the block 104 and comprises four elements, movement takes place in a block 105. In that figure, since the input buffer is now, ie the device, is set in the third operating position. the data input In connected to the data output INFIFO, MEMFIFO1 and the output buffer OUTFIFO. The first four elements in the third operating mode are Out via the input buffer memory buffer queue in the input buffer INFIFO is moved in a burst to the memory buffer MEMFIFO1 which now thus comprises four elements. If the next transaction is an entry to the buffer device, an entry is made in the input buffer INFIFO. Moving to block 106 but the memory buffer is not empty, the device remains in the third operating mode. the figure takes place because After three more readings to the buffer device, the first four elements in the queue move the memory buffer in the input buffer INFIFO, in a burst to MMFIFO1. The memory buffer MEMFIFO1 now comprises at least eight elements, the input buffer INFIFO comprises zero elements and the output buffer OUTFIFO still comprises four elements. In the figure, movement takes place from block 105 to block 106. In block 106 elements. is checked if the memory buffer comprises zero Since the answer to the question is "No", 10 15 20 25 30 35 '515 897¿ _'_ = § _'_ = _ = .____.-' '° _' in 12 shifts in the figure back to block 105 and the device remains in the third operating position. If there are four or more free slots in the OUTFIFO buffer when the buffer device is in the third operating mode, the MEMFIFO1 memory buffer and OUTFIFO. data elements output from the output buffer are read in. The movement of the data elements from the memory buffer to the output buffer takes place in the form of a burst. Four elements are moved according to the exemplary embodiment in the cut.

Figure 4 shows in a second exemplary embodiment a buffer system according to the invention. The figure shows the same integrated circuit part IC1 as previously shown in figure 1. The parts included in the integrated circuit part IC1 have not been marked with reference numerals in figure 4.

The reference numerals are therefore found only in Figure 1. The parts have been included and the various Figures 4 have only been marked with the symbols of the respective parts. The integrated circuit part IC1, comprises the data input In, the input buffer INFIFO circuit part, the output buffer OUTFIFO, the so-called first data output Out, as well as one and two DMUX2. multiplexer MUX1 demultiplexer DMUX1, The first circuit part IC1 forms part of a larger integrated circuit IC. According to the exemplary embodiment, the larger integrated circuit IC comprises four further circuit parts.

IC2, a third circuit part IC3, fifth circuit part IC5.

The four circuit parts are called a second circuit part, a fourth circuit part IC4 and a The total of five circuit parts are thus located on the same integrated circuit IC, ie on the same silicon surface. According to the exemplary embodiment, the five circuit parts are identical, but only the first circuit part is shown in detail in Figure 4, while the other parts are only shown symbolically. In the first embodiment, the second demultiplexing unit DMUX2 was connected to an input of a memory buffer MEMFIFO1. In this second embodiment, the five circuit parts IC1, IC2, IC3, IC4 and IC5 share the same memory buffer MEMFIFO. The second multiplexer DMUX2 on the first circuit part IC1 is in the --..- ,. 10 15 20 25 30 35 '515 897 gF _'_ == ¿j' _ :: '-., _.__ =' 13 second embodiment connected to a first input of a multiplex unit MUX on the integrated circuit IC.

The MUX output of the multiplexer is connected to an input on the MEMFIFO memory buffer. The output of the MEMFIFO memory buffer is connected to an input on a DEMUX demultiplexer. A first output from the demultiplexing unit DEMUX is connected to one of the inputs of the multiplexing unit MUX1 on the first circuit part IC1. A second input of the multiplexer MUX is second second connected to a multiplexer of that circuit part IC2. Figure 4 does not show the second multiplexing unit on the second circuit part IC2. Only one connection circuit part to the multiplexer MUX. The remaining circuit parts IC3, IC4 and IC5 are shown from the other are also connected to the multiplexer MUX in the same way, but only the connection itself is shown in figure 4. A second DEMUX is connected to a circuit part IC2. output of the demultiplexing unit multiplexing unit at the second The remaining outputs of the demultiplexing unit DEMUX are similarly connected to the other circuit parts IC3, IC4 and IC5 on the integrated circuit IC. The memory buffer is divided into as many parts MEM1, MEM2, MEM3, MEM4 and MEM5 as there are circuit parts' IC1, IC2, IC3, IC4 and IC5 on the integrated circuit part. A buffer device consists of a circuit IC and uses its part of the memory buffer MEMFIFO. circuit part each IC1 together with the associated memory buffer part MEM1. Figure '4 also shows. a control logic CL soul has basically control logic CL1 the same properties and function as that described earlier in the first embodiment. The control logic CL handles the writing of a data element to a buffer device, the movement of the data element through the buffer device and the reading of the data element from the buffer device. The difference from the first embodiment is that in this second embodiment the control logic CL handles all buffer devices, ie according to the embodiment all five buffer devices IC1 + MEM1, IC2 + MEM2, handle 15: 15. : ut 13.2:: LL. "Ii I. .É 14 IC3 + MEM3, IC4 + MEM4 And IC5 + MEM5. Some of the connection points between the control logic CL1 and the parts controlled by the control logic have been marked in Figure 4 with contact symbols.

According to the exemplary embodiment, both enrollment to and reading from one of the five buffer devices is independent of the other four buffer devices. The entry to as data a buffer device occurs sporadically arrives and without the influence of the other buffers in readout from which the buffer system. The same applies to the buffer devices. A buffer device transitions, already previously described, from a second operating mode to a third operating mode when the amount of data elements in the input buffer has exceeded a predetermined value. When switching to the third operating mode, according to the first embodiment, the memory buffer MEMFIFO1 was connected between the input buffer INFIFO and the output buffer OUTFIFO. In this embodiment, the control logic CL connects only the part of the memory buffer MEMFIFO which belongs to the circuit part.

The connection is made via the multiplex unit MUX and the demultiplex unit DEMUX. Connection of the first circuit part IC1 to the first part MEM1 in the memory buffer MEMFIFO is made at the transition to the third operating mode, ie when the input buffer after reading contains four elements. The transfer between the INFIFO buffer and. the memory buffer MEMFIFO is made in burst form. When the transfer is complete, the multiplexer MUX remains in its position until another data element is to be written to another buffer in another of the buffer devices, an input buffer which already comprises a predetermined number of data elements. The same procedure applies when reading from the memory buffer MEMFIFO via DEMUX to one of the circuit parts. between a part MEM1 of the demultiplexing unit The transfer of the data element memory buffer and a circuit part IC1 thus takes place in burst form.

Since four data elements are sequentially transferred from the memory buffer to the memory buffer and from the memory buffer to the output buffer, memory space in the buffers are quickly released compared to if only one element had been transferred at a time. This means that the risk of conflict situations at the on / off for conflict situations entry and reading of data elements memory buffer is minimized. The risk can also be reduced by increasing the size of the input buffer and / or the output buffer.

The invention is not limited to the embodiments described above. The size of the different buffers can, for example, vary. The size of the input buffer and the output buffer do not have to be the same either. The different parts must be the buffer parts in order for the operating permit for one For example, an output buffer does not have to be full for elements that are in the different transitions to take place from another can also vary. transition shall take place to the next operating mode. The implementation of a buffer does not have to be structured in detail as described earlier, the significant thing is that the input buffer and the output buffer are on the circuit and are fast, external and large while the memory buffer is storage capacity. Registration for a memory buffer can take place without this being done in burst form, as was the case in both embodiments. Another possibility is that registration for the memory buffer takes place in burst form, while only individual elements are read out from the memory buffer in each reading cycle, or vice versa. The amount of elements transmitted in a burst may vary and the amount of elements written to the memory buffer in a burst may be different from the amount of elements read out of the memory buffer in another burst.

It is also conceivable that the memory buffer shown in the second exemplary embodiment can be used simultaneously by different buffer devices as well as other units in the system. ..... u ao * ° '' ''. . . The invention is thus not limited to the embodiments described and shown in the drawing, can be modified within the scope of the appended claims.

OVaII without

Claims (9)

10 15 20 25 30 35 ~ -. . . .. 515- 897 '/ 7 PAIENTKRAV Buffer device (1) of (In), a data output MEMFIFO), the type first-in-first-out comprising a data input (Out) (MEMFIFO1; the buffer device comprises an input buffer and a memory buffer characterized in that (IC1) output buffer DMUX2) for that (Out), integrated circuit part (INFIFO) and one (MUX1, DMUX1, which comprises one (OUTFIFO) and an arrangement (In) which to DMUX2) merge the data input buffer (OUTFIFO) (Out), with the data output connected DMUX1 the output of the data output which arrangement (MUX1) can put the device in one of the following operating modes: a first mode, the data input (In) being connected to an input of the output buffer (OUTFIFO), a second mode, the data input (In) being connected to an input to the input buffer (INFIFO) and where an output of the input buffer (INFIFO) is connected to the input of the output buffer (OUTFIFO), a third mode, the data input (In) being connected to the input of the input buffer (INFIFO), and where the output of the input buffer (INFIFO ) is an closed to an input to the memory buffer (MEMFIFO1; MEMFIFO) and where an output from the memory buffer is connected to the input of the output buffer (OUTFIFO). Buffer device according to claim 1, which device comprises means for moving a plurality of data elements from the input buffer (INFIFO) to the memory buffer (MEMFIFO1; MEMFIFO) in the form of a burst. Buffer device according to claim 1 or 2, which device comprises means for moving in the form of a burst a plurality of data elements from the memory buffer (MEMFIFO1; MEMFIFO) to the output buffer (OUTFIFO). 10 15 20 25 30 35/8 A method for passing data elements through a buffer device (1) of the first-in-first-out type, between a data input (In) and a data output (Out), which buffer device comprises a memory buffer (MEMFIFO1; MEMFIFO) and an integrated circuit part (IC1) comprising an input buffer (INFIFO) and an output buffer (OUTFIFO), which method comprises the following steps: - influencing the device to switch to a second operating mode if the device is in a first operating mode and if the number of elements in the output buffer (OUTFIFO) exceeds a predetermined number; - influencing the device to switch to a third operating mode if the device is in the second operating mode and if the number of elements in the buffer (INFIFO) exceeds a predetermined number; - influencing the device to switch to the second operating mode if the device is in the third operating mode and if the number of elements in the memory buffer (MEMFIFO1; MEMFIFO) is less than a predetermined number; influencing the device to switch to the first operating mode if the device is in the second operating mode and if the number of elements in the input buffer (INFIFO) is less than a predetermined number. The method of claim 4, comprising the following additional steps: forming a burst, of a plurality of data elements from the INFIFO input buffer to the memory buffer (MEMFIFO1; MEMFIFO). movement in A method according to claim 4 or 5, comprising the following further steps: plurality to burst, of a (MEMFIFO1; MEMFIFO) movement in the form of a data element from. the memory buffer utbufferten (OUTFIFO). 10 15 _> -. ~. . . . _ _ _ 545 897 / Cï Buffer system comprising at least two buffer devices according to claim 1, (MEM1, characterized in that different external memory buffers MEM2, MEM3, MEM5) in MEM4, each buffer device consists of the same physical (MEMFIFO), (CL, for allocating write and read rights for each (MEMFIFO) memory unit DMUX, MUX) and that the system comprises means buffer device, to and from the memory unit A system according to claim 7, which system comprises means for moving in the form of a burst a plurality of data elements from an input buffer in a buffer device to the memory buffer (MEMFIFO). A system according to claim 7 or 8, which system in the form of a burst move one (MEMFI FO) comprises means for transferring in a plurality of data elements from the memory buffer to an output buffer in a buffer device.