KR102778966B1 - Resistance variable memory device and method for fabricating the same - Google Patents

Abstract

The present invention relates to a variable resistance memory device and a manufacturing method thereof, and provides a variable resistance memory device including first conductive lines extending in a first direction, second conductive lines extending in a second direction intersecting the first direction, and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, wherein each of the memory cells includes a lower electrode, a variable resistance pattern, a middle electrode, a switching pattern, and an upper electrode sequentially stacked between corresponding first conductive lines and second conductive lines, wherein the lower electrode includes a lower line portion that is in contact with an upper surface of the corresponding first conductive line and extends in the first direction, a plurality of protrusions that protrude from an upper surface of the lower line portion and are spaced apart from each other along the first direction, and pillar patterns that are respectively arranged on the plurality of protrusions and have a pillar shape, and the variable resistance pattern is arranged on a corresponding protrusion and covers an upper surface and side surfaces of the pillar pattern on the corresponding protrusion.

Description

Resistance variable memory device and method for fabricating the same {Resistance variable memory device and method for fabricating the same}

The present invention relates to a variable resistance memory device and a method for manufacturing the same, and more particularly, to a variable resistance memory device having a cross-point structure and a method for manufacturing the same.

Recently, with the spread of portable digital devices and the increasing need to store digital data, interest in nonvolatile memory devices that do not lose stored data even when power is turned off is increasing.

As semiconductor devices, flash memory devices are widely used because they can be manufactured at low cost based on silicon processes, such as DRAM memory devices. However, flash memory devices have the disadvantages of having relatively low integration, slow operation speed, and requiring relatively high voltage for data storage compared to DRAM memory devices, which are volatile memory devices.

To overcome the shortcomings of such flash memory devices, various next-generation semiconductor devices such as phase changeable RAM (PRAM), magnetic RAM (MRAM), and resistance changeable RAM (RRAM) have been proposed. Such next-generation nonvolatile memory devices can operate at relatively low voltages and have fast access times, which significantly offsets the shortcomings of flash memory devices. In particular, magnetic memory devices are attracting attention as next-generation memories because they can have high-speed operation and/or non-volatility characteristics.

As the electronics industry advances, the demand for high integration and/or low power consumption of magnetic memory devices is increasing. Accordingly, many studies are being conducted to meet these demands.

The background technology of this application is disclosed in Patent Publication No. 10-2020-0022567.

The technical problem to be solved by the present invention is to provide a variable resistance memory device with improved electrical characteristics and reliability and a method for manufacturing the same.

The problems to be solved by the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

According to embodiments of the present invention for achieving the above object, a variable resistance memory device includes first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; and memory cells respectively provided at intersections between the first conductive lines and the second conductive lines, each of the memory cells including a lower electrode, a variable resistance pattern, a middle electrode, a switching pattern, and an upper electrode sequentially stacked between corresponding first conductive lines and second conductive lines, wherein the lower electrode includes a lower line portion in contact with an upper surface of the corresponding first conductive line and extending in the first direction, a plurality of protrusions protruding from an upper surface of the lower line portion and spaced apart from each other along the first direction, and pillar patterns respectively disposed on the plurality of protrusions and having a pillar shape, wherein the variable resistance pattern is disposed on a corresponding protrusion and covers an upper surface and side surfaces of the pillar pattern on the corresponding protrusion.

According to one embodiment, the memory cells arranged along the first direction share one lower electrode, and the pillar patterns arranged respectively on the protrusions and their upper surfaces can be two-dimensionally arranged in an island shape along the first direction and the second direction corresponding to each memory cell.

In one embodiment, the variable resistance pattern can be in contact with the upper surface of the corresponding protrusion and the upper surface and side surfaces of the pillar pattern on the corresponding protrusion.

According to embodiments of the present invention, since the variable resistance pattern is arranged on the upper surface of the protrusion of the lower electrode and is implemented to be in contact with the upper surface and side surfaces of the pillar pattern, the contact area between the lower electrode and the variable resistance pattern can be increased. As a result, the flow of current can be improved due to the reduction in contact resistance between the lower electrode and the variable resistance pattern in contact therewith, so that the electrical characteristics (e.g., minimization of power consumption) and reliability can be improved.

As a result, it may be possible to provide a variable resistance memory device with improved electrical characteristics and reliability.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.
FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention.
Figures 3a and 3b are cross-sectional views taken along lines I-I' and II-II' of Figure 2, respectively.
FIGS. 4A to 8A are drawings for explaining a method for manufacturing a variable resistance memory element according to one embodiment of the present invention, and are cross-sectional views corresponding to line II' of FIG. 2.
FIGS. 4b to 8b are drawings for explaining a method for manufacturing a variable resistance memory element according to one embodiment of the present invention, and are cross-sectional views corresponding to line II-II' of FIG. 2.

The advantages and features of the present invention, and the methods for achieving them, will become clearer with reference to the embodiments described in detail below together with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and the present embodiments are provided only to make the disclosure of the present invention complete and to fully inform those skilled in the art of the scope of the invention, and the present invention is defined only by the scope of the claims. Like reference numerals refer to like elements throughout the specification.

In this specification, when it is said that an element is “on” another element, this includes not only cases where the element is in contact with the other element, but also cases where another element exists between the two elements. In addition, when it is said in this specification that a part “includes” a certain element, this does not mean that other elements are excluded, but rather that other elements can be included, unless otherwise specifically stated.

The terms “about,” “substantially,” and the like, as used throughout this specification, are used in a meaning that is at or near the numerical value when manufacturing and material tolerances inherent in the meanings referred to are presented, and are used to prevent unscrupulous infringers from unfairly exploiting the disclosure, which contains precise or absolute values to aid understanding of this specification.

Hereinafter, embodiments of the present invention will be described in detail with reference to the attached drawings.

FIG. 1 is a perspective view schematically illustrating a variable resistance memory element according to embodiments of the present invention.

Referring to FIG. 1, first conductive lines (CL1) extending in a first direction (D1) and second conductive lines (CL2) extending in a second direction (D2) intersecting the first direction (D1) may be provided. The second conductive lines (CL2) may be spaced apart from the first conductive lines (CL1) along a third direction (D3) perpendicular to the first direction (D1) and the second direction (D2). A memory cell stack (MCA) may be provided between the first conductive lines (CL1) and the second conductive lines (CL2). The memory cell stack (MCA) may include memory cells (MC) provided at each of the intersections of the first conductive lines (CL1) and the second conductive lines (CL2). The memory cells (MC) may be arranged two-dimensionally to form rows and columns. Although one memory cell stack (MCA) is illustrated in the present embodiment, embodiments of the present invention are not limited thereto. Memory cell stacks (MCAs) can be provided in multiples and stacked vertically.

Each of the memory cells (MC) may include a variable resistance pattern (VR) and a switching pattern (SW). The variable resistance pattern (VR) and the switching pattern (SW) may be connected in series with each other between a pair of conductive lines (CL1, CL2) connected thereto.

For example, a variable resistance pattern (VR) and a switching pattern (SW) included in each of the memory cells (MC) may be connected in series with each other between a corresponding first conductive line (CL1) and a corresponding second conductive line (CL2). Here, the first conductive line (CL1) may be a bit line, and the second conductive line (CL2) may be a word line, or vice versa. In addition, although FIG. 1 illustrates that the switching pattern (SW) is provided on the variable resistance pattern (VR), embodiments of the present invention are not limited thereto. Unlike FIG. 1, the variable resistance pattern (VR) may also be provided on the switching pattern (SW).

Voltage is applied to the variable resistance pattern (VR) of the memory cell (MC) through the first challenge line (CL1) and the second challenge line (CL2), so that current can flow through the variable resistance pattern (VR), and the resistance of the variable resistance pattern (VR) of the selected memory cell (MC) can change depending on the applied voltage.

According to the change in resistance of the variable resistance pattern (VR), the memory cell (MC) can store digital information such as "0" or "1", and the digital information can be erased from the memory cell (MC). For example, data can be written in the memory cell (MC) in a high resistance state "0" and a low resistance state "1". Here, writing from the high resistance state "0" to the low resistance state "1" can be called a "set operation", and writing from the low resistance state "1" to the high resistance state "0" can be called a "reset operation". However, the memory cell (MC) according to the embodiments of the present invention is not limited to the digital information of the high resistance state "0" and the low resistance state "1" exemplified above, and can store various resistance states.

For example, the variable resistance pattern (VR) may include a phase change material layer that can reversibly transition between a first state and a second state. However, the variable resistance pattern (VR) is not limited thereto, and may include any variable resistor whose resistance value changes depending on an applied voltage.

As another example, the variable resistance pattern (VR) may include a transition metal oxide layer, in which case at least one electrical passage may be created or destroyed within the variable resistance pattern (VR) by a program operation. When the electrical passage is created, the variable resistance pattern (VR) may have a low resistance value, and when the electrical passage is destroyed, the variable resistance pattern (VR) may have a high resistance value. By utilizing the difference in resistance values of the variable resistance pattern (VR), the variable resistance memory element may store data.

The switching pattern (SW) may be a current control element capable of controlling the flow of current. In the present invention, the switching pattern (SW) may be a selection element having an ovonic threshold switching (OTS) characteristic. That is, the switching pattern (SW) may include a material having an ovonic threshold switching characteristic in which resistance may change depending on the magnitude of a voltage applied to both ends of the switching pattern (SW). Accordingly, when a voltage smaller than the threshold voltage is applied to the switching pattern (SW), the switching pattern (SW) is in a high resistance state, and when a voltage larger than the threshold voltage is applied to the switching pattern (SW), it is in a low resistance state and current starts to flow. In addition, when the current flowing through the switching pattern (SW) becomes smaller than the holding current, the switching pattern (SW) may change to a high resistance state.

Any memory cell (MC) can be addressed by selecting a first challenge line (CL1) and a second challenge line (CL2), and by applying a predetermined signal between the first challenge line (CL1) and the second challenge line (CL2), the memory cell (MC) is programmed, and by measuring a current value through the first challenge line (CL1), information according to the resistance value of a variable resistor constituting the corresponding memory cell (MC) can be read.

Referring to FIGS. 2, 3a, and 3b below, a variable resistance memory device according to one embodiment of the present invention will be described.

FIG. 2 is a plan view showing a variable resistance memory element according to one embodiment of the present invention. FIGS. 3a and 3b are cross-sectional views taken along lines I-I' and II-II' of FIG. 2, respectively. FIGS. 4a and 4b are drawings showing a variable resistance memory element according to another embodiment of the present invention, and are cross-sectional views taken along lines I-I' and II-II' of FIG. 2, respectively.

Referring to FIGS. 2, 3A, and 3B, first conductive lines (CL1) and second conductive lines (CL2) may be sequentially provided on a substrate (100). The first conductive lines (CL1) may extend in a first direction (D1) substantially parallel to a top surface of the substrate (100) and may be spaced apart from each other in a second direction (D2) substantially parallel to the top surface of the substrate (100) and intersecting the first direction (D1). The second conductive lines (CL2) may extend in the second direction (D2) and be spaced apart from each other in the first direction (D1). The first conductive lines (CL1) and the second conductive lines (CL2) may be spaced apart from each other in a third direction (D3) perpendicular to the top surface of the substrate (100).

The substrate (100) may include a semiconductor substrate, such as a Si substrate, a Ge substrate, a Si-Ge substrate, a Silicon-on-Insulator (SOI) substrate, a Germanium-On-Insulator (GOI) substrate, etc. The substrate (100) may also include a III-V group compound, such as InP, GaP, GaAs, GaSb, etc. Meanwhile, although not shown, a p-type or n-type impurity may be injected into the upper portion of the substrate (100) to form a well.

Each of the first and second challenge lines (CL1, CL2) may include a metal (e.g., copper, tungsten, or aluminum) and/or a metal nitride (e.g., tantalum nitride, titanium nitride, or tungsten nitride).

An interlayer insulating film (102) may be interposed between the substrate (100) and the first conductive lines (115). The interlayer insulating film (102) may be formed of an oxide film, a nitride film, or a combination thereof. The interlayer insulating film (102) may serve to electrically isolate a plurality of first conductive lines (110) from the substrate (102). In addition, a peripheral circuit (not shown) including a transistor, a contact, a wiring, etc. may be formed on the substrate (100). In addition, a lower insulating film (not shown) that at least partially covers the peripheral circuit may be formed on the substrate (100).

First insulating patterns (104) may be arranged between the first challenge lines (CL1). The first insulating patterns (104) may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof.

Memory cells (MC) may be arranged between first conductive lines (CL1) and second conductive lines (CL2), and may be respectively positioned at intersections of the first conductive lines (CL1) and second conductive lines (CL2). The memory cells (MC) may be two-dimensionally arranged along the first direction (D1) and the second direction (D2). The memory cells (MC) may form one memory cell stack (MCA, see FIG. 1).

Each of the memory cells (MC) may include a lower electrode (112), a variable resistance pattern (122), a middle electrode (132), a switching pattern (142), and an upper electrode (152) that are sequentially stacked, and their cell structures may be connected in series between a pair of conductive lines (CL1, CL2) connected thereto. In the present embodiment, the first and second conductive lines (CL1, CL2), the variable resistance pattern (122), and the switching pattern (142) may correspond to the first and second conductive lines (CL1, CL2), the variable resistance pattern (VR), and the switching pattern (SW) of FIG. 1.

The lower electrodes (112) are arranged on the first conductive lines (CL1) and can generate Joule heat by the current applied to the cell structure through the first conductive lines (CL1).

According to embodiments of the present invention, each of the lower electrodes (112) may have a line shape extending in a first direction (D1) and in contact with the upper surface of the first conductive line (CL1) thereunder, and the upper surface of the lower electrode (112) may form an uneven surface, and pillar patterns (115) may be provided on the uneven surface.

Specifically, each of the lower electrodes (112) may include a lower line portion (113) that is in contact with the upper surface of the first conductive line (CL1) and extends in the first direction (D1), a plurality of protrusions (114) that protrude from the upper surface of the lower line portion (113) and are spaced apart from each other along the first direction (D1), and pillar patterns (115) that are respectively arranged on the plurality of protrusions (114) and have a pillar shape. The pillar patterns (115) may generally have a hexahedral pillar shape, but the present invention is not limited thereto.

Since the lower electrode (112) has a line shape extending in the first direction (D1), the memory cells (MC) arranged along the first direction (D1) can share one lower electrode (112). In addition, the protrusions (114) and the pillar patterns (115) arranged on the upper surface thereof can be two-dimensionally arranged in an island shape along the first direction (D1) and the second direction (D2) corresponding to each memory cell (MC).

A variable resistance pattern (122) may be arranged on each of the protrusions (114) to surround the upper surface and side surfaces of the pillar pattern (115). That is, the variable resistance pattern (122) may be arranged on the protrusion (114) and cover the upper surface and side surfaces of the pillar pattern (115). Accordingly, the variable resistance pattern (122) may be in contact with the upper surface of the protrusion (114) and the upper surface and side surfaces of the pillar pattern (115).

In one embodiment, the lower electrode (112) may be a heater electrode that applies heat to the variable resistance patterns (122) in contact therewith to change the phase of the variable resistance patterns (122). For example, the lower electrode (112) may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO.

According to embodiments of the present invention, since the variable resistance pattern (122) is disposed on the upper surface of the protrusion (114) of the lower electrode (112) and is implemented to be in contact with the upper surface and side surfaces of the pillar pattern (115), the contact area between the lower electrode (112) and the variable resistance pattern (122) can be increased. As a result, due to the reduction in contact resistance between the lower electrode (112) and the variable resistance pattern (122) in contact therewith, the flow of current is improved, so that electrical characteristics (e.g., minimization of power consumption) and reliability can be improved.

The variable resistance pattern (122) may include a material that stores information according to changes in resistance.

According to one embodiment, the variable resistance pattern (122) may include a material capable of a reversible phase change between crystalline and amorphous depending on temperature. For example, the variable resistance pattern (122) may be formed of a compound in which at least one of chalcogenide elements Te and Se is combined with at least one selected from Ge, Sb, Bi, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, P, O, and C. Specifically, the variable resistance pattern (122) may include at least one of GeSbTe, GeTeAs, SbTeSe, GeTe, SbTe, SeTeSn, GeTeSe, SbSeBi, GeBiTe, GeTeTi, InSe, GaTeSe, and InSbTe.

According to another embodiment, the variable resistance pattern (122) may include a material whose electrical resistance changes due to oxygen vacancy or oxygen movement.

In detail, the variable resistance pattern (122) may include at least one of perovskite compounds or conductive metal oxides. For example, the variable resistance pattern (122) may include at least one of niobium oxide, titanium oxide, nickel oxide, zirconium oxide, vanadium oxide, PCMO ((Pr,Ca)MnO3), strontium-titanium oxide, barium-strontium-titanium oxide, strontium-zirconium oxide, barium-zirconium oxide, or barium-strontium-zirconium oxide. When the variable resistance pattern (122) includes transition metal oxides, the dielectric constant of the variable resistance pattern (122) may be greater than the dielectric constant of the silicon oxide film. As another example, the variable resistance pattern (122) may have a dual structure of a conductive metal oxide and a tunnel insulating film, or a triple structure of a first conductive metal oxide, a tunnel insulating film, and a second conductive metal oxide. The tunnel insulating film may include aluminum oxide, hafnium oxide, or silicon oxide.

The middle electrode (132) is in contact with the upper surface of the variable resistance pattern (122) and can electrically connect the switching pattern (142) and the variable resistance pattern (122). The middle electrode (132) can include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, and TaSiN.

The switching pattern (142) is a selection element having ovonic threshold switching (OTS) characteristics and can act as a switch.

In one embodiment, the switching pattern (142) may include a chalcogenide material. The chalcogenide material may include a compound in which at least one of the chalcogen elements Te and Se is combined with at least one of Ge, Sb, Bi, Al, Pb, Sn, Ag, As, S, Si, In, Ti, Ga, and P. For example, the chalcogenide material may include at least one of AsTe, AsSe, GeTe, SnTe, GeSe, SnTe, SnSe, ZnTe, AsTeSe, AsTeGe, AsSeGe, AsTeGeSe, AsSeGeSi, AsTeGeSi, AsTeGeS, AsTeGeSiIn, AsTeGeSiP, AsTeGeSiSbS, AsTeGeSiSbP, AsTeGeSeSb, AsTeGeSeSi, SeTeGeSi, GeSbTeSe, GeBiTeSe, GeAsSbSe, GeAsBiTe, and GeAsBiSe. According to some embodiments, the switching pattern (142) may further include an impurity (for example, at least one of C, N, B, and O).

An upper electrode (152) may be placed on the switching pattern (142). The upper electrode (152) may include a metal nitride, such as titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), zirconium nitride (ZrNx), etc.

A second conductive line (CL2) may be provided on the upper electrode (152). The second conductive line (CL2) may be commonly connected to a plurality of upper electrodes (170) arranged along the second direction (D2). The second conductive line (CL2) may include a metal or a metal nitride, such as copper, aluminum, tungsten, cobalt, titanium, tantalum, titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), or the like.

A capping insulating pattern (162) may be provided on sidewalls of a cell structure including a lower electrode (112), a variable resistance pattern (122), a middle electrode (132), a switching pattern (142), and an upper electrode (152) that are sequentially stacked. The capping insulating pattern (162) covers the sidewalls of the cell structure and may extend onto a lower line portion (113) of the lower electrode (112) to be connected to a capping insulating pattern (162) that covers sidewalls of an adjacent cell structure. The capping insulating pattern (162) may expose an upper surface of the upper electrode (120). The capping insulating pattern (162) may include silicon nitride. The capping insulating pattern (162) may perform a function of protecting a surface of the cell structure from being oxidized or damaged.

Second insulating patterns (164) may be arranged between memory cells (MC) on which capping insulating patterns (162) are formed (i.e., between cell structures). The second insulating patterns (164) may be formed of a silicon oxide film, a silicon nitride film, or a combination thereof. The second insulating patterns (164) may be formed of a single film or a multilayer film.

As described, a variable resistance memory device can be provided in which variable resistance memory cells are provided at the cross points of a first challenge line (CL1) and a second challenge line (CL2).

FIGS. 4A to 8A are drawings for explaining a method for manufacturing a variable resistance memory element according to an embodiment of the present invention, and are cross-sectional views corresponding to line I-I' of FIG. 2. FIGS. 4B to 8B are drawings for explaining a method for manufacturing a variable resistance memory element according to an embodiment of the present invention, and are cross-sectional views corresponding to line II-II' of FIG. 2. The same reference numerals may be provided for components that are substantially the same as those described with reference to FIGS. 2, 3A, and 3B, and redundant descriptions may be omitted.

Referring to FIGS. 4A and 4B, an interlayer insulating film (102) may be formed on a substrate (100), and first conductive lines (CL1) and lower electrode lines (110) extending in a first direction (D1) and spaced apart in a second direction (D2) may be formed on the interlayer insulating film (102). The first conductive lines (CL1) and the lower electrode lines (110) may be formed by sequentially depositing a first conductive film and a first lower electrode film on the substrate (100) on which the interlayer insulating film (102) is formed, and patterning the same. The first conductive film may include a metal or a metal nitride, such as, for example, copper, aluminum, tungsten, titanium, tantalum, titanium nitride (TiNx), tungsten nitride (WNx), tantalum nitride (TaNx), or the like. The first lower electrode film may include at least one of W, Ti, Al, Cu, C, CN, TiN, TiAlN, TiSiN, TiCN, WN, CoSiN, WSiN, TaN, TaCN, TaSiN, or TiO. Each of the first conductive film and the first lower electrode film may be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process.

First insulating patterns (104) may be formed between the stacked first conductive lines (CL1) and the lower electrode lines (110). The first insulating patterns (104) may be formed of silicon oxide, silicon nitride, or a combination thereof.

Referring to FIGS. 5A and 5B, pillar patterns (115) may be formed on the lower electrode lines (110). The pillar patterns (115) may be formed two-dimensionally in an island shape along the first direction (D1) and the second direction (D2). The pillar patterns (115) may be formed by forming a second lower electrode film on the substrate (100) on which the first conductive lines (CL1), the lower electrode lines (110), and the first insulating patterns (104) are formed, and patterning the second lower electrode film. The second lower electrode film may be formed of substantially the same material and by the same method as the first lower electrode film.

Referring to FIGS. 6A and 6B, a variable resistance film (120) may be formed on a substrate (100) on which pillar patterns (115) are formed. The variable resistance film (120) may be formed to cover the upper surfaces and side surfaces of the pillar patterns (115) and fill spaces between adjacent pillar patterns (115). Thereafter, a planarization process may be performed so that the upper surface of the variable resistance film (120) becomes flat. The variable resistance film (120) may be made of the same material as the variable resistance pattern (122) described with reference to FIGS. 2, 3A, and 3B, and therefore, a detailed description thereof will be omitted.

Referring to FIGS. 7A and 7B, an intermediate electrode film (130), a switching material film (140), and an upper electrode film (150) may be sequentially formed on a substrate (100) on which a variable resistance film (120) is formed. Each of the intermediate electrode film (130), the switching material film (140), and the upper electrode film (150) may be formed through a physical vapor deposition (PVD) process, a sputtering process, or a chemical vapor deposition (CVD) process. The intermediate electrode film (130), the switching material film (140), and the upper electrode film (150) may be the same as the constituent materials of the intermediate electrode (132), the switching pattern (142), and the upper electrode (152) described with reference to FIGS. 2, 3A, and 3B, respectively, and therefore, a detailed description thereof will be omitted.

Referring to FIGS. 8A and 8B, a variable resistance film (120), an intermediate electrode film (130), a switching material film (140), and an upper electrode film (150) may be patterned to form a variable resistance pattern (122), an intermediate electrode (132), a switching pattern (142), and an upper electrode (152). The patterning may include forming island-shaped mask patterns (not shown) arranged along a first direction (D1) and a second direction (D2) on the upper electrode film (150), and performing an etching process using the island-shaped mask patterns as an etching mask.

During the above patterning, a portion of the upper surface of the lower electrode lines (110) may be recessed. As a result, a lower line portion (113) that is in contact with the upper surface of the first conductive line (CL1) and extends in the first direction (D1) and a plurality of protrusions (114) that protrude from the upper surface of the lower line portion (113) and are spaced apart from each other along the first direction (D1) may be formed. The lower line portion (113) in the form of a line extending in the first direction (D1), the protrusion (114) on the lower line portion (113), and the pillar pattern (115) on the protrusion (114) may be defined as the lower electrode (112). In addition, a portion of the upper surface of the first insulating patterns (104) may also be recessed during the above patterning.

Referring again to FIGS. 3A and 3B, capping insulating patterns (162) may be formed to cover sidewalls of cell structures including a lower electrode (112), a variable resistance pattern (122), a middle electrode (132), a switching pattern (142), and an upper electrode (152), and having an upper surface of the same height as an upper surface of the upper electrode (152), and second insulating patterns (164) may be formed to fill spaces between the cell structures on which the capping insulating patterns (162) are formed. The second insulating patterns (164) may have an upper surface of the same height as an upper surface of the upper electrode (152).

Next, a second conductive line (CL2) can be formed that is commonly connected to the upper electrodes (152) arranged along the second direction (D2).

Although the embodiments of the present invention have been described with reference to the attached drawings, those skilled in the art will understand that the present invention can be implemented in other specific forms without changing the technical idea or essential features thereof. Therefore, it should be understood that the embodiments and application examples described above are exemplary in all respects and are not limiting.

Claims (3)

First challenge lines extending in the first direction;
Second challenge lines extending in a second direction intersecting the first direction; and
Including memory cells provided at each intersection between the first challenge lines and the second challenge lines,
Each of the above memory cells includes a lower electrode, a variable resistance pattern, a middle electrode, a switching pattern, and an upper electrode sequentially stacked between corresponding first and second conductive lines,
The lower electrode includes a lower line portion extending in the first direction and in contact with the upper surface of the corresponding first conductive line, a plurality of protrusions protruding from the upper surface of the lower line portion and spaced apart from each other along the first direction, and pillar patterns each arranged on the plurality of protrusions and having a pillar shape.
A variable resistance memory element in which the variable resistance pattern is arranged on a corresponding protrusion and covers the upper surface and side surfaces of the pillar pattern on the corresponding protrusion. In the first paragraph,
The memory cells arranged along the first direction share one lower electrode,
A variable resistance memory element in which the protrusions and the pillar patterns respectively arranged on the upper surface thereof are two-dimensionally arranged in an island shape along the first direction and the second direction corresponding to the respective memory cells. In the second paragraph,
A variable resistance memory element in which the above variable resistance pattern is in contact with the upper surface of the corresponding protrusion and the upper surface and side surfaces of the pillar pattern on the corresponding protrusion.