KR102718858B1 - Transmitter and receiver for low power input/output and memory system including the same - Google Patents

Abstract

The transmitter includes a multiplexer, control logic, and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals in a binary manner that are input in parallel and have two different voltage levels and multi-phase clock signals. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals having a temporarily boosted voltage level based on the plurality of time-interleaved data signals. The voltage mode driver generates a duobinary output data signal having three different voltage levels based on the at least one pull-down control signal and the plurality of pull-up control signals.

Description

TRANSMITTER AND RECEIVER FOR LOW POWER INPUT/OUTPUT AND MEMORY SYSTEM INCLUDING THE SAME

The present invention relates to a semiconductor integrated circuit, and more particularly, to a transmitter and receiver for low power input/output, and a memory system including the transmitter and the receiver.

Recently, there has been an increasing demand for memory bandwidth for high performance computing (HPC), such as artificial intelligence (AI) and graphic processing units (GPUs). The expansion of bandwidth can depend on innovation in process technology, and the advancement of process technology has created higher densities in integrated circuits (ICs). 3D integration is receiving increasing attention as it offers the possibility of continuously increasing the density of ICs, and high bandwidth memory (HBM) using through silicon vias (TSVs) is being studied.

When utilizing multiple through-silicon vias as channels, signal transitions occurring in one channel may be transmitted or received as noise to an adjacent channel due to parasitic capacitance generated according to the material characteristics of the through-silicon via. Problems such as data delay or jitter added due to the transmitted noise, resulting in deterioration of reception performance in the receiver, etc., may occur.

One object of the present invention is to provide a transmitter that generates a duobinary data signal using a time-interleaved method for low-power input/output.

Another object of the present invention is to provide a receiver that effectively receives a data signal in duobinary mode.

Another object of the present invention is to provide a memory system including the transmitter and the receiver.

To achieve the above object, a transmitter according to embodiments of the present invention includes a multiplexer, control logic, and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of binary input data signals and multi-phase clock signals that are input in parallel and have two different voltage levels. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals having a temporarily boosted voltage level based on the plurality of time-interleaved data signals. The voltage mode driver generates a duobinary output data signal having three different voltage levels based on the at least one pull-down control signal and the plurality of pull-up control signals.

In order to achieve the above other objects, a receiver according to embodiments of the present invention includes a first flip-flop and a second flip-flop. The first flip-flop receives a duobinary input data signal having three different voltage levels, and generates a binary first output data signal having two different voltage levels based on the input data signal, a first clock signal, a first reference voltage, and a first selection signal. The second flip-flop receives the input data signal, and generates a binary second output data signal based on the input data signal, a second clock signal different from the first clock signal, the first reference voltage, and a second selection signal. The second output data signal is provided as the first selection signal, and the first output data signal is provided as the second selection signal. The first flip-flop forms a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal.

In order to achieve the above further object, a memory system according to embodiments of the present invention includes a transmitter, a channel, and a receiver. The transmitter outputs write data to be stored in a memory device or read data read from the memory device. The channel transmits the write data or the read data. The receiver receives the write data or the read data. The transmitter includes a multiplexer, control logic, and a voltage mode driver. The multiplexer generates a plurality of time-interleaved data signals based on a plurality of input data signals in a binary manner that are input in parallel and have two different voltage levels and multi-phase clock signals. The control logic generates at least one pull-down control signal and a plurality of pull-up control signals having a temporarily boosted voltage level based on the plurality of time-interleaved data signals. The voltage mode driver generates a duobinary mode output data signal having three different voltage levels based on the at least one pull-down control signal and the plurality of pull-up control signals. The receiver includes a first flip-flop and a second flip-flop. The first flip-flop receives the output data signal and generates the first data signal in binary format based on the output data signal, the first clock signal, the first reference voltage, and the first selection signal. The second flip-flop receives the output data signal and generates the second data signal in binary format based on the output data signal, a second clock signal different from the first clock signal, the first reference voltage, and the second selection signal. The second data signal is provided as the first selection signal, and the first data signal is provided as the second selection signal. The first flip-flop forms a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal. The plurality of input data signals, the output data signal, and the first and second data signals correspond to the write data or the read data.

The transmitter and receiver according to the embodiments of the present invention as described above may have a structure for low-power input/output. Specifically, the transmitter is implemented to generate a duobinary-type output data signal using a time interleaved method, and may have a structure for no static power consumption, guaranteeing operation at high speed, and increasing power efficiency. In addition, the receiver is implemented to reduce complexity by reducing the number of reference voltages for sensing the duobinary-type input data signal, and may have a structure for improving input offset and a structure for reducing output delay variation.

A memory system including a transmitter and a receiver according to embodiments of the present invention as described above can have improved signal characteristics.

FIG. 1 is a block diagram illustrating a transmitter and a receiver according to embodiments of the present invention.
FIG. 2 is a block diagram showing a transmitter according to embodiments of the present invention.
Fig. 3 is a circuit diagram showing an example of the transmitter of Fig. 2.
FIGS. 4a, 4b, 4c, 4d, and 4e are diagrams showing examples of signals input and output from the transmitter of FIG. 3.
FIG. 5 is a circuit diagram showing an example of a first boosting circuit included in the transmitter of FIG. 3.
FIG. 6 is a diagram showing examples of signals input and output from the first boosting circuit of FIG. 5.
Figures 7a, 7b, 7c and 7d are drawings showing the performance of the transmitter of Figure 3.
FIG. 8 is a block diagram illustrating a receiver according to embodiments of the present invention.
FIG. 9 is a circuit diagram showing an example of a first flip-flop included in the receiver of FIG. 8.
FIGS. 10A and 10B are diagrams showing examples of signals input and output from the first flip-flop of FIG. 9.
Figures 11a and 11b are drawings showing the performance of the receiver of Figures 8 and 9.
FIG. 12 is a block diagram illustrating a memory system according to embodiments of the present invention.
Figure 13 is a block diagram showing an example of the memory system of Figure 12.
FIGS. 14a and 14b are cross-sectional views showing a semiconductor package including the memory system of FIGS. 12 and 13.

Hereinafter, with reference to the attached drawings, a preferred embodiment of the present invention will be described in more detail. The same reference numerals are used for the same components in the drawings, and duplicate descriptions of the same components are omitted.

FIG. 1 is a block diagram illustrating a transmitter and a receiver according to embodiments of the present invention.

Referring to FIG. 1, a transmitter (TX) (10) and a receiver (RX) (20) are connected to each other through a channel (30). For example, as described below with reference to FIGS. 14a and 14b, the channel (30) may include at least one through silicon via (TSV).

The transmitter (10) generates a duobinary-type output data signal (TX_OUT) based on a binary-type input data signal (TX_IN). The output data signal (TX_OUT) is transmitted to the receiver (20) through a channel (30). The receiver (20) generates a binary-type output data signal (RX_OUT) based on the duobinary-type input data signal (RX_IN).

The above duobinary method is a method implemented so that the output data signal (TX_OUT) has three different voltage levels, and at this time, one value (or data) included in the output data signal (TX_OUT) of the duobinary method can represent the sum of two adjacent values (or bits) included in the input data signal (TX_IN) (for example, the sum of the previous value and the current value).

For example, the three voltage levels of the output data signal (TX_OUT) may include a first voltage level (VL1), a second voltage level (VL2) higher than the first voltage level (VL1), and a third voltage level (VL3) higher than the second voltage level (VL2). The first voltage level (VL1), the second voltage level (VL2), and the third voltage level (VL3) may be referred to as a low level, a middle (middle or mid) level, and a high level, respectively. For example, the first voltage level (VL1) may be about 0 V, the second voltage level (VL2) may be about 0.3 V, and the third voltage level (VL3) may be about 0.6 V.

The above binary method is a method implemented so that the output data signal (RX_OUT) has two different voltage levels, and at this time, one value (or data) included in the output data signal (RX_OUT) of the binary method can represent one value (or bit) included in the input data signal (TX_IN).

For example, the two voltage levels of the output data signal (RX_OUT) may include a first voltage level (VL1) and a fourth voltage level (VL4) higher than the first voltage level (VL1). The first voltage level (VL1) and the fourth voltage level (VL4) may be referred to as a low level and a high level, respectively. For example, the fourth voltage level (VL4) is higher than the third voltage level (VL3) and may be about 1.2 V. In other words, the swing width of the output data signal (RX_OUT) may be larger than the swing width of the output data signal (TX_OUT).

Meanwhile, the input data signal (TX_IN) in the binary format may also have two different voltage levels. For example, although not illustrated in detail, the low level of the input data signal (TX_IN) may be identical to the first voltage level (VL1), and the high level may be identical to the third voltage level (VL3).

The transmitter (10) and the receiver (20) according to the embodiments of the present invention may have a structure for low power input/output. Specifically, the transmitter (10) is implemented to generate the output data signal (TX_OUT) of the duobinary method using a time-interleaved method, and may have a structure for no static power consumption, guaranteeing operation at high speed, and increasing power efficiency. The receiver (20) is implemented to reduce complexity by reducing the number of reference voltages for sensing the input data signal (RX_IN) of the duobinary method, and may have a structure for improving input offset and a structure for reducing output delay variation. The structure and operation of the transmitter (10) will be described later with reference to FIGS. 2 to 7, and the structure and operation of the receiver (20) will be described later with reference to FIGS. 8 to 11.

FIG. 2 is a block diagram showing a transmitter according to embodiments of the present invention.

Referring to FIG. 2, the transmitter (100) includes a multiplexer (110), control logic (120), and a voltage mode driver (130).

A multiplexer (110) generates a plurality of time interleaved data signals (TID) based on a plurality of input data signals (TX_IN) and multi-phase clock signals (MPCK). The plurality of input data signals (TX_IN) are input in parallel and are binary signals having two different voltage levels, as described above with reference to FIG. 1. The multi-phase clock signals (MPCK) may be clock signals whose phases partially overlap. The multiplexer (110) may serialize the plurality of input data signals (TX_IN).

For example, the number of the plurality of input data signals (TX_IN) and the number of the multi-phase clock signals (MPCK) are the same, and one clock signal can correspond to one input data signal. In addition, two or more input data signals are time-interleaved to generate one time-interleaved data signal, and therefore the number of the plurality of time-interleaved data signals (TID) can be less than the number of the plurality of input data signals (TX_IN).

The control logic (120) generates at least one pull-down control signal (PDS) and a plurality of pull-up control signals (PUS) based on a plurality of time interleaved data signals (TID). Each of the plurality of pull-up control signals (PUS) has a temporarily boosted voltage level, thereby reinforcing a transition of an output data signal (TX_OUT), ensuring operation at high speed, and increasing power efficiency.

The voltage mode driver (130) generates an output data signal (TX_OUT) based on at least one pull-down control signal (PDS) and a plurality of pull-up control signals (PUS). The output data signal (TX_OUT) is a duobinary signal having three different voltage levels as described above with reference to FIG. 1. For example, the voltage mode driver (130) may be a dual source driver as described below with reference to FIG. 3.

A transmitter (100) according to embodiments of the present invention is implemented including a voltage mode driver (130) having almost no static power consumption instead of a current mode driver (or current mode logic (CML) driver) having high static power consumption, and may be implemented including a control logic (120) for generating a 3-level signal (i.e., a duobinary signal) based on the voltage mode driver (130).

Fig. 3 is a circuit diagram showing an example of the transmitter of Fig. 2. Figs. 4a, 4b, 4c, 4d, and 4e are drawings showing examples of signals input and output from the transmitter of Fig. 3.

Referring to FIGS. 3, 4a, 4b, 4c, 4d and 4e, the transmitter (100a) includes a multiplexer (110a), control logic (120a) and a voltage mode driver (130a), and may further include an output terminal (or output node) (140).

In the example of FIG. 3, the plurality of input data signals (TX_IN) of FIG. 2 may include a first input data signal (D0), a second input data signal (D1), a third input data signal (D2), and a fourth input data signal (D3) that are input in parallel. The multi-phase clock signals (MPCK) of FIG. 2 may include a first clock signal (CK1), a second clock signal (CK2), a third clock signal (CK3), and a fourth clock signal (CK4) whose phases partially overlap. The plurality of time interleaved data signals (TID) of FIG. 2 may include a first time interleaved data signal (X) and a second time interleaved data signal (Y). At least one pull-down control signal (PDS) of FIG. 2 may include a first pull-down control signal (PD). The plurality of pull-up control signals (PUS) of FIG. 2 may include a first pull-up control signal (PUMID) and a second pull-up control signal (PUHIGH). The output data signal (TX_OUT) of Fig. 2 can correspond to the output data signal (TOUT).

The multiplexer (110a) may include a first transistor (MN11), a second transistor (MN12), a third transistor (MN13), and a fourth transistor (MN14).

A first transistor (MN11) may be connected between a first input node (N11) receiving a first input data signal (D0) and a first output node (N15) providing a first time interleaved data signal (X), and may have a gate electrode to which a first clock signal (CK1) is applied. A second transistor (MN12) may be connected between a second input node (N12) receiving a second input data signal (D1) and a second output node (N16) providing a second time interleaved data signal (Y), and may have a gate electrode to which a second clock signal (CK2) is applied. A third transistor (MN13) may be connected between a third input node (N13) receiving a third input data signal (D2) and the first output node (N15), and may have a gate electrode to which a third clock signal (CK3) is applied. A fourth transistor (MN14) is connected between a fourth input node (N14) that receives a fourth input data signal (D3) and a second output node (N16), and may have a gate electrode to which a fourth clock signal (CK4) is applied.

As illustrated in FIG. 4e, when the time interval at which the output data signal (TOUT) represents one value is 1 unit interval (UI) (1UI), the time intervals at which the first, second, third, and fourth input data signals (D0, D1, D2, D3) represent one value and the periods of the first, second, third, and fourth clock signals (CK1, CK2, CK3, CK4) as illustrated in FIGS. 4a and 4b may correspond to 4 unit intervals (4UI). For example, the first data rate of the first, second, third, and fourth input data signals (D0, D1, D2, D3) may be about 1 Gb/s, and the periods of the first, second, third, and fourth clock signals (CK1, CK2, CK3, CK4) may be about 0.5 GHz. The first, second, third and fourth input data signals (D0, D1, D2, D3) have values of “a”, “b”, “c” and “d”, respectively, for example, “a” and “b” may be “0” each and “c” and “d” may be “1” each.

As described above, the multiplexer (110a) serializes the first, second, third and fourth input data signals (D0, D1, D2, D3) and can output first and second time-interleaved data signals (X, Y) in which the first, second, third and fourth input data signals (D0, D1, D2, D3) are time-interleaved. For example, the first time-interleaved data signal (X) may be a signal in which the first and third input data signals (D0, D2) are time-interleaved, and the second time-interleaved data signal (Y) may be a signal in which the second and fourth input data signals (D1, D3) are time-interleaved. For example, the second data rate of the first and second time-interleaved data signals (X, Y) may be higher than the first data rate. For example, the second data rate may be about twice as high as the first data rate and may be about 2 Gb/s.

Specifically, as illustrated in FIGS. 4a, 4b, and 4c, at time t1, the first input data signal (D0) is output as the first time-interleaved data signal (X) based on the first clock signal (CK1), and thus, the first time-interleaved data signal (X) has a value of “0” corresponding to the first input data signal (D0), and the second time-interleaved data signal (Y) can have a value of “0” which is an initial value. At time t2, the second input data signal (D1) is output as the second time-interleaved data signal (Y) based on the second clock signal (CK2), and thus, the second time-interleaved data signal (Y) has a value of “0” corresponding to the second input data signal (D1), and the first time-interleaved data signal (X) can maintain the value of “0” which is the value at time t1. Similarly, at time t3, the third input data signal (D2) is output as the first time interleaved data signal (X) based on the third clock signal (CK3), and thus, the first time interleaved data signal (X) has a value of “1” corresponding to the third input data signal (D2), and the second time interleaved data signal (Y) can be maintained at a value of “0”. At time t4, the fourth input data signal (D3) is output as the second time interleaved data signal (Y) based on the fourth clock signal (CK4), and thus, the second time interleaved data signal (Y) has a value of “1” corresponding to the fourth input data signal (D3), and the first time interleaved data signal (X) can be maintained at a value of “1”.

The control logic (120a) may include a first NAND gate (121), a NOR gate (122), an inverter (123), a second NAND gate (124), a first boosting circuit (125), and a second boosting circuit (126).

The first NAND gate (121) can perform a NAND operation on the first and second time interleaved data signals (X, Y). The NOR gate (122) can perform a NOR operation on the first and second time interleaved data signals (X, Y) to generate a first pull-down control signal (PD). The inverter (123) can invert the output of the NOR gate (122). The second NAND gate (124) can perform a NAND operation on the output of the first NAND gate (121) and the output of the inverter (123). The first boosting circuit (125) can generate a first pull-up control signal (PUMID) having a temporarily boosted voltage level based on the output of the first NAND gate (121). The second boosting circuit (126) can generate a second pull-up control signal (PUHIGH) having a temporarily boosted voltage level based on the output of the second NAND gate (124).

The value of the first pull-down control signal (PD) and the values of the first and second pull-up control signals (PUMID, PUHIGH) can be determined according to the values of the first and second time interleaved data signals (X, Y). For example, a third data rate of the first pull-down control signal (PD) and the first and second pull-up control signals (PUMID, PUHIGH) can be higher than the second data rate. For example, the third data rate can be about twice as high as the second data rate and can be about 4 Gb/s.

Specifically, as illustrated in FIGS. 4c and 4d, when the first and second time-interleaved data signals (X, Y) have a value of “0” at times t1 and t2, respectively, the first pull-down control signal (PD) can have a value of “1” and the first and second pull-up control signals (PUMID, PUHIGH) can have a value of “0”, respectively. When the first time-interleaved data signal (X) has a value of “1” and the second time-interleaved data signal (Y) has a value of “0” at time t3, the first pull-up control signal (PUMID) can have a value of “1” and the first pull-down control signal (PD) and the second pull-up control signal (PUHIGH) can have a value of “0”, respectively. When the first and second time interleaved data signals (X, Y) each have a value of "1" at time t4, the second pull-up control signal (PUHIGH) can have a value of "1", and the first pull-down control signal (PD) and the first pull-up control signal (PUMID) can each have a value of "0". An asterisk (*) displayed in front of the value of "1" of the first pull-up control signal (PUMID) at time t3 and the second pull-up control signal (PUHIGH) at time t4 indicates that the first and second pull-up control signals (PUMID, PUHIGH) each have a boosted high level.

The voltage mode driver (130a) may include a first transistor (MN15), a second transistor (MN16), and a third transistor (MN17).

A first transistor (MN15) may be connected between an output node (140) providing an output data signal (TOUT) and a ground voltage having a first voltage level (VL1), and may have a gate electrode receiving a first pull-down control signal (PD). A second transistor (MN16) may be connected between a first power supply voltage (VDDL1) having a third voltage level (VL3) and the output node (140), and may have a gate electrode receiving a second pull-up control signal (PUHIGH). A third transistor (MN17) may be connected between a second power supply voltage (VDDL2) having a second voltage level (VL2) and the output node (140), and may have a gate electrode receiving a first pull-up control signal (PUMID). For example, the second voltage level (VL2) may be approximately half of the third voltage level (VL3) (i.e., 2*VL2=VL3 or 2*VDDL2=VDDL1). For example, the first transistor (MN15) may be a pull-down transistor, and the second and third transistors (MN16, MN17) may be pull-up transistors.

The output data signal (TOUT) can have a level corresponding to the sum of two adjacent ones of the first, second, third and fourth input data signals (D0, D1, D2, D3). For example, one of the first, second and third transistors (MN15, MN16, MN17) is turned on based on the value of the first pull-down control signal (PD) and the values of the first and second pull-up control signals (PUMID, PUHIGH), and the voltage level of the output data signal (TOUT) can be determined by the turned-on transistor. For example, the output data signal (TOUT) can have the third data rate.

Specifically, as illustrated in FIGS. 4a, 4d and 4e, when the first pull-down control signal (PD) has a value of "1" at time t2, the first transistor (MN15) is turned on, and the output data signal (TOUT) can have a first voltage level (VL1) based on the power supply voltage. The first voltage level (VL1) can correspond to a value of "a+b", i.e., "0", which is the sum of the first and second input data signals (D0, D1). Similarly, when the first pull-up control signal (PUMID) has a value of "1" at time t3, the third transistor (MN17) is turned on, and the output data signal (TOUT) can have a second voltage level (VL2) based on the second power supply voltage (VDDL2). The second voltage level (VL2) may correspond to a value of "b+c", that is, "1", which is the sum of the second and third input data signals (D1, D2). When the second pull-up control signal (PUHIGH) has a value of "1" at time t4, the second transistor (MN16) is turned on, and the output data signal (TOUT) may have a third voltage level (VL3) based on the first power voltage (VDDL1). The third voltage level (VL3) may correspond to a value of "c+d", that is, "2", which is the sum of the third and fourth input data signals (D2, D3). Meanwhile, although not illustrated, at time t1, the first transistor (MN15) is turned on similarly to at time t2, and the output data signal (TOUT) may have the first voltage level (VL1).

In one embodiment, the transistors (MN11, MN12, MN13, MN14, MN15, MN16, MN17) may all be N-type Metal Oxide Semiconductor (NMOS) transistors.

Fig. 5 is a circuit diagram showing an example of a first boosting circuit included in the transmitter of Fig. 3. Fig. 6 is a diagram showing examples of signals input and output from the first boosting circuit of Fig. 5.

Referring to FIGS. 5 and 6, the first boosting circuit (125) may include a pulse generator (128), a first transistor (MP21), a capacitor (C21), a second transistor (MP22), and a third transistor (MN23).

A pulse generator (128) is connected to an input node (N21) that receives an output of a first NAND gate (121), and can generate a pulse signal (PUL) based on the output of the first NAND gate (121). A first transistor (MP21) is connected between a first power supply voltage (VDDL1) and a node (N22), and can have a gate electrode to which a pulse signal (PUL) is applied. A capacitor (C21) can be connected between a gate electrode of the first transistor (MP21) and the node (N22). A second transistor (MP22) is connected between the node (N22) and an output node (N23) that provides a first pull-up control signal (PUMID), and can have a gate electrode connected to the input node (N21). A third transistor (MN23) is connected between the output node (N23) and the ground voltage, and can have a gate electrode connected to the input node (N21).

In one embodiment, the transistors (MP21, MP22) may be PMOS (P-type Metal Oxide Semiconductor) transistors, and the transistor (MN23) may be an NMOS transistor.

The control logic (120a) included in the transmitter (100a) according to embodiments of the present invention may include a pulse generator (128) that creates a delay for a predetermined period of time in order to ensure operation at high speed and increase power efficiency. The level of the pulse signal (PUL) and the first pull-up control signal (PUMID) provided through the output node (N23) may be determined based on the output of the first NAND gate (121) received at the input node (N21).

Specifically, in FIG. 6, IN1 represents the output of the first NAND gate (121), that is, the voltage of the input node (N21), and OUT1 represents the first pull-up control signal (PUMID) provided through the output node (N23), the voltage of the output node (N23). When the voltage (IN1) of the input node (N21) has a high level (i.e., the third voltage level (VL3) or "1"), the pulse signal (PUL) and the voltage (OUT1) of the output node (N23) can have a low level (i.e., the first voltage level (VL1) or "0"). At this time, the first transistor (MP21) (i.e., the header PMOS transistor) is turned on to have a sufficient precharge time, and the capacitor (C21) can be precharged based on the first power supply voltage (VDDL1). When the voltage (IN1) of the input node (N21) transitions from a high level to a low level, the pulse signal (PUL) can transition from a low level to a high level, maintain the high level for a predetermined period of time, and then transition from the high level to a low level again. During the predetermined period of time that the pulse signal (PUL) has a high level, the first transistor (MP21) is turned off and the output node (N23) is boosted based on the charges charged in the capacitor (C21) for the predetermined period of time to have a boosted high level (i.e., a level of VL3+α), and thereafter, when the pulse signal (PUL) has a low level, the first transistor (MP21) is turned on, so that the output node (N23) can return to the original high level (i.e., a level of VL3). Therefore, the first pull-up control signal (PUMID) can have a temporarily boosted voltage level like the voltage of the output node (N23) illustrated in FIG. 6.

Meanwhile, although not illustrated, the structure and operation of the second boosting circuit (126) may be substantially identical to the structure and operation of the first boosting circuit (125) described above with reference to FIGS. 5 and 6.

The outputs of the control logic (120a) temporarily boosted to the level of VL3+α (i.e., the first and second pull-up control signals (PUMID, PUHIGH)) can reinforce the transition from the first voltage level (VL1) to the second voltage level (VL2) and the transition from the second voltage level (VL2) to the third voltage level (VL3) of the voltage-mode driver (130a) of the final stage (i.e., the pull-up transistors of the output driver can be temporarily strongly driven). In addition, since the operating region is guaranteed to be a linear region through the boosted high level even when the transition from the second voltage level (VL2) to the third voltage level (VL3) occurs, the voltage-mode driver (130a) can perform reliable operation even under PVT (Process-Voltage-Temperature) variation.

Figures 7a, 7b, 7c and 7d are drawings showing the performance of the transmitter of Figure 3. Figures 7a, 7b, 7c and 7d show simulation results for the transmitter of Figure 3.

Referring to FIG. 7a, the results of Monte Carlo (1000 runs) simulation performed under ideal conditions (VDD, TT corner, room temperature) of a transmitter (100a) according to embodiments of the present invention are shown, and it can be confirmed that the transmitter is operating while securing sufficient margin.

Referring to FIG. 7b, it shows the change in the boosted high level (i.e., peak voltage) and the time (duty) for which boosting is maintained according to the PVT variation for the outputs of the control logic (120a) of the transmitter (100a) according to the embodiments of the present invention. It can be confirmed that even if the boosted high level varies by about ±10%, the change in the eye-performance and power is within about ±2%, and even if the time varies by up to about 40%, the overall performance change is within about 4%.

Referring to Fig. 7c, it shows the results of analyzing the eye performance in 20 corners (Process corner: TT, SS, FF, FS, SF / Supply voltage: HVDD, LVDD / Temperature: Cold, Hot) based on the PVT variation analysis of Fig. 7b. As a result of analyzing the performance in the two corners with the most severe changes, "SS/LVDD/Hot" and "FF/HVDD/Cold", it can be confirmed that the former has a performance change of about 21% to 26%, and the latter has a performance change of about 12% to 21%.

Referring to FIG. 7d, the power consumption of the transmitter (100a) according to embodiments of the present invention is shown. In FIG. 7d, the left side shows a conventional case using a current mode driver (i.e., a CML driver), and the right side shows an embodiment of the present invention using a voltage mode driver (130a) or a dual source driver. Compared to the left side, the embodiment of the present invention can obtain a power consumption reduction of about 59%, and can obtain a power consumption reduction of about 41% (power consumption reduction of the serialization process is 26%) compared to the voltage mode driver I/O structure that swings to VDD/2 (about 0.6 V).

FIG. 8 is a block diagram illustrating a receiver according to embodiments of the present invention.

Referring to FIG. 8, the receiver (200) includes a first flip-flop (FF1) (210) and a second flip-flop (FF2) (220).

A first flip-flop (210) receives an input data signal (RX_IN) and generates a first output data signal (RX_OUT1) based on the input data signal (RX_IN), a first clock signal (CKE), a first reference voltage (VH), and a first selection signal (SEL1). A second flip-flop (220) receives an input data signal (RX_IN) and generates a second output data signal (RX_OUT2) based on the input data signal (RX_IN), a second clock signal (CKO) different from the first clock signal (CKE), a first reference voltage (VH), and a second selection signal (SEL2).

The input data signal (RX_IN) is a duobinary signal having three different voltage levels as described above with reference to FIG. 1. Each of the first and second output data signals (RX_OUT1, RX_OUT2) is a binary signal having two different voltage levels as described above with reference to FIG. 1. One of the first and second output data signals (RX_OUT1, RX_OUT2) (e.g., the first output data signal (RX_OUT1)) may correspond to the output data signal (RX_OUT) of FIG. 1.

Each of the first and second flip-flops (210, 220) may include a first input terminal for receiving an input data signal (RX_IN), a clock terminal for receiving clock signals (CKE, CKO), an output terminal for outputting output data signals (RX_OUT1, RX_OUT2), a reference voltage terminal (VREF) for receiving a first reference voltage (VH), and a selection terminal (SEL) for receiving selection signals (SEL1, SEL2). At this time, the second output data signal (RX_OUT2) of the second flip-flop (220) may be provided to the first flip-flop (210) as a first selection signal (SEL1), and the first output data signal (RX_OUT1) of the first flip-flop (210) may be provided to the second flip-flop (220) as a second selection signal (SEL2).

The first flip-flop (210) forms a second reference voltage (e.g., VL) different from the first reference voltage (VH) based on the first reference voltage (VH) and the first selection signal (SEL1). Similarly, the second flip-flop (220) forms a second reference voltage (VL) based on the first reference voltage (VH) and the second selection signal (SEL2). In other words, the same operation/effect as using two reference voltages (VH, VL) can be obtained by using only one first reference voltage (VH).

The first flip-flop (210) and the second flip-flop (220) may be referred to as an even flip-flop and an odd flip-flop, respectively, and the first clock signal (CKE) and the second clock signal (CKO) may also be referred to as an even clock signal and an odd clock signal, respectively. For example, the first and second clock signals (CKE, CKO) may have opposite phases. By using clock signals of opposite phases, it is possible to operate at about half the frequency.

A receiver (200) according to embodiments of the present invention can be implemented to receive and sense the input data signal (RX_IN) in the duobinary mode having the three voltage levels using only one first reference voltage (VH).

Fig. 9 is a circuit diagram showing an example of a first flip-flop included in the receiver of Fig. 8. Figs. 10a and 10b are drawings showing examples of signals input and output from the first flip-flop of Fig. 9.

Referring to FIGS. 9, 10a and 10b, the first flip-flop (210a) may include a first circuit portion (230), a second circuit portion (240) and an output portion (250).

In the example of FIG. 9, the input data signal (RX_IN) of FIG. 8 may correspond to the input data signal (DIN), and the first output data signal (RX_OUT1) of FIG. 8 may correspond to the output data signal (RDE).

The first circuit unit (230) may include a first structure for generating a first data signal (DA) and a second data signal (DREF) based on a power supply voltage (VDDH), an input data signal (DIN), a first clock signal (CKE), a first reference voltage (VH), and a first selection signal (SEL), and forming a second reference voltage (VL), and a second structure for boosting the first and second data signals (DA, DREF).

As illustrated in FIG. 10A, the input data signal (DIN) has substantially the same waveform as the output data signal (TOUT) of FIG. 4E, and may have first, second, and third voltage levels (VL1, VL2, VL3). The first reference voltage (VH) may have a voltage level (VLH) between the second and third voltage levels (VL2, VL3), and the second reference voltage (VL) may have a voltage level (VLL) between the first and second voltage levels (VL1, VL2). For example, the voltage level (VLH) of the first reference voltage (VH) may be about 0.45 V, and the voltage level (VLL) of the second reference voltage (VL) may be about 0.15 V.

The first circuit unit (230) may include a first transistor (MP31), a second transistor (MP32), a third transistor (MP33), a fourth transistor (MP34), a fifth transistor (MP35), a sixth transistor (MP36), a seventh transistor (MP37), an eighth transistor (MN38), and a ninth transistor (MN39).

The first, second and third transistors (MP31, MP32, MP33) may be connected in parallel between the node (N31) and a first data node (N32) providing a first data signal (DA). The first transistor (MP31) may have a gate electrode receiving a power supply voltage (VDDH), the second transistor (MP32) may have a gate electrode receiving an input data signal (DIN), and the third transistor (MP33) may have a gate electrode connected to a second data node (N33) providing a second data signal (DREF). The fourth, fifth and sixth transistors (MP34, MP35, MP36) may be connected in parallel between the node (N31) and the second data node (N33). The fourth transistor (MP34) may have a gate electrode connected to the first data node (N32), the fifth transistor (MP35) may have a gate electrode receiving a first reference voltage (VH), and the sixth transistor (MP36) may have a gate electrode receiving a first selection signal (SEL1). The seventh transistor (MP37) may be connected between the power supply voltage (VDDH) and the node (N31) and may have a gate electrode receiving a first clock signal (CKE). The eighth transistor (MN38) may be connected between the first data node (N32) and a ground voltage and may have a gate electrode receiving the first clock signal (CKE). The ninth transistor (MN39) may be connected between the second data node (N33) and the ground voltage and may have a gate electrode receiving the first clock signal (CKE).

In one embodiment, the sixth transistor (MP36) may correspond to the first structure for forming the second reference voltage (VL). Specifically, when the first selection signal (SEL1), which is the second output data signal (RX_OUT2) of the second flip-flop (220) (i.e., the previous data output of the second flip-flop (220)), is at a high level (i.e., “1”), the sixth transistor (MP36) is turned off, and the first circuit unit (230) may compare the input data signal (DIN) with the first reference voltage (VH) to generate the first and second data signals (DA, DREF). When the first selection signal (SEL1) is at a high level (i.e., “1”), the sixth transistor (MP36) is turned on to allow additional current to flow to the second data node (N33), and almost the same current as when the second reference voltage (VL) is applied to the fifth transistor (MP35) can be provided to the second data node (N33). In other words, based on the first reference voltage (VH), the first selection signal (SEL1), and the fifth and sixth transistors (MP35, MP36), a driving current corresponding to the second reference voltage (VL) is provided to the second data node (N33), and the first circuit unit (230) can compare the input data signal (DIN) with the second reference voltage (VL) to generate the first and second data signals (DA, DREF).

In one embodiment, the third and fourth transistors (MP33, MP34) may correspond to the second structure for boosting the first and second data signals (DA, DREF). Specifically, the current flowing to the first and second data nodes (N32, N33) can be temporarily boosted at an evaluation timing through the third and fourth transistors (MP33, MP34). When an input of a first voltage level (i.e., about 0 V) through which a relatively large current flows is applied, the influence of the boosted current is relatively small, whereas when an input of a third voltage level (i.e., about 0.6 V) through which a relatively small current flows is applied, the influence of the boosted current is relatively large, so that a change in output delay according to an input case can be ultimately reduced.

The second circuit unit (240) can generate a third data signal (SB) and a fourth data signal (RB) based on a power supply voltage (VDDH), first and second data signals (DA, DREF), and a first clock signal (CKE). In addition, the second circuit unit (240) can include a third structure for improving an input offset.

The second circuit unit (240) may include a first inverter (242), a second inverter (244), a first transistor (MP41), a second transistor (MN42), a third transistor (MN43), a fourth transistor (MP44), a fifth transistor (MN45), a sixth transistor (MN46), and a seventh transistor (MP47).

The first inverter (242) can receive the first data signal (DA). The second inverter (244) can receive the second data signal (DREF). The first transistor (MP41) has a gate electrode connected to a third data node (N42) providing a third data signal (SB) and can be connected between the node (N41) and a fourth data node (N43) providing a fourth data signal (RB). The second and third transistors (MN42, MN43) can be connected in parallel between the fourth data node (N43) and the ground voltage. The second transistor (MN42) can have a gate electrode connected to an output of the first inverter (242), and the third transistor (MN43) can have a gate electrode connected to the third data node (N42). The fourth transistor (MP44) may be connected between the node (N41) and the third data node (N42) and may have a gate electrode connected to the fourth data node (N43). The fifth and sixth transistors (MN45, MN46) may be connected in parallel between the third data node (N42) and the ground voltage. The fifth transistor (MN45) may have a gate electrode connected to the fourth data node (N43), and the sixth transistor (MN46) may have a gate electrode connected to the output of the second inverter (244). The seventh transistor (MP47) may be connected between the power supply voltage (VDDH) and the node (N41) and may have a gate electrode that receives a first clock signal (CKE).

In one embodiment, the first and second inverters (242, 244) may correspond to the third structure for improving the input offset. By adding the first and second inverters (242, 244), the input offset problem occurring in the conventional structure can be improved.

The output unit (250) can generate an output data signal (RDE) and an inverted signal (RDBE) of the output data signal (RDE) based on the third and fourth data signals (SB, RB).

The output unit (250) may include a first inverter (252), a second inverter (254), and an SR NAND latch (256). The first inverter (252) may receive a third data signal (SB). The second inverter (254) may receive a second data signal (RB). The SR NAND latch (256) may generate an output data signal (RDE) and an inverted signal (RDBE) of the output data signal (RDE) based on the outputs of the first and second inverters (252, 254).

The power supply voltage (VDDH) is a different voltage from the first and second power supply voltages (VDDL1, VDDL2) of FIG. 3, and may have a fourth voltage level (VL4). Accordingly, as illustrated in FIG. 10b, the two voltage levels of the output data signal (RDE) generated based on the power supply voltage (VDDH) may include the first voltage level (VL1) and the fourth voltage level (VL4). In addition, the output data signal (RDE) may be generated such that the values "a", "b", "c", and "d" of the input data signals (D0, D1, D2, D3) of the transmitter (100a) illustrated in FIG. 4a are sequentially arranged.

In one embodiment, the transistors (MP31, MP32, MP33, MP34, MP35, MP36, MP37, MP41, MP44, MP47) can be PMOS transistors, and the transistors (MN38, MN39, MN42, MN43, MN45, MN46) can be NMOS transistors.

Meanwhile, although the embodiments of the present invention have been described based on the case where only one first reference voltage (VH) is used, the present invention is not limited thereto and can be applied even when only one second reference voltage (VL) is used.

Meanwhile, although not illustrated, the structure and operation of the second flip-flop (220) may be substantially identical to the structure and operation of the first flip-flop (210a) described above with reference to FIGS. 9 and 10.

Figures 11a and 11b are drawings showing the performance of the receivers of Figures 8 and 9. Figures 11a and 11b show simulation results for the receivers of Figures 8 and 9.

Referring to FIG. 11A, currents generated in a receiver (200) according to embodiments of the present invention are shown. In FIG. 11A, the left side shows a driving current (Iconv) generated by a second reference voltage (VL) in a conventional case using two first and second reference voltages (VH, VL), and the right side shows a driving current (Ipro) generated by a first reference voltage (VH) and a first selection signal (SEL1) in an embodiment of the present invention using only two first reference voltages (VH). In the conventional case, the mean of the driving current (Iconv) is about 2.53f, the standard deviation is about 99.2a, and the mean over sigma is about 0.039. In the embodiment of the present invention, the mean of the driving current (Ipro) is about 3.54f, the standard deviation is about 99a, and the mean over sigma is about 0.039. It can be confirmed that the driving current (Iconv) and the driving current (Ipro) are output similarly.

Referring to FIG. 11b, the performance of a receiver (200) according to embodiments of the present invention is illustrated. In FIG. 11b, the left side represents a conventional case and the right side represents an embodiment of the present invention. In addition, in FIG. 11b, case 1 represents a case where the input is about 0 V and the reference voltage is about 0.15 V, case 2 represents a case where the input is about 0.3 V and the reference voltage is about 0.15 V, case 3 represents a case where the input is about 0.3 V and the reference voltage is about 0.45 V, and case 4 represents a case where the input is about 0.6 V and the reference voltage is about 0.45 V. When checking the delay from case 2, which has the least change, to case 4, where a high level is input, we can see that the delay in case 2 is reduced by about 1%, but in case 4, it is reduced by about 27%, and the delay variation by input case is improved by about 50%, from about ±20% to ±10% based on the median value.

FIG. 12 is a block diagram illustrating a memory system according to embodiments of the present invention.

Referring to FIG. 12, the memory system (300) includes a memory controller (310) and a memory device (320). The memory system (300) may further include a plurality of signal lines (330) that electrically connect the memory controller (310) and the memory device (320).

The memory device (320) is controlled by the memory controller (310). For example, the memory controller (310) may write data to the memory device (320) or read data from the memory device (320) based on a request from a host (not shown). For example, the memory device (320) may be a high bandwidth memory (HBM) device.

The plurality of signal lines (330) may include a control line, a command line, an address line, a data line, and a power line. The memory controller (310) may transmit a command (CMD), an address (ADDR), and a control signal (CTRL) to the memory device (320) through the command line, the address line, and the control line, may exchange a data signal (MLDAT) with the memory device (320) through the data line, and may provide a power voltage (PWR) to the memory device (320) through the power line. For example, the control signal (CONT) may include a chip enable signal (CE), a write enable signal (WE), a read enable signal (RE), a command latch enable signal (CLE), an address latch enable signal (ALE), etc. For example, the data signal (MLDAT) is a multi-level signal and may be a duobinary data signal generated by a transmitter according to embodiments of the present invention and received by a receiver according to embodiments of the present invention.

Although not illustrated, the plurality of signal lines (330) may further include a DQS line for transmitting a data strobe signal (i.e., a DQS signal). The DQS signal may be a signal for providing a reference point for determining a logic value of a data signal (MLDAT) exchanged between the memory controller (310) and the memory device (320). However, as illustrated in FIG. 12, the DQS signal may be omitted.

In one embodiment, some or all of the plurality of signal lines (330) may be referred to as a channel. In this specification, the data line through which the data signal (MLDAT) is transmitted is referred to as a channel. However, the present invention is not limited thereto, and the channel may further include the command line through which the command (CMD) is transmitted and/or the address line through which the address (ADDR) is transmitted. For example, the channel may include at least one Through Silicon Via (TSV).

Figure 13 is a block diagram showing an example of the memory system of Figure 12.

Referring to FIG. 13, the memory system (302) includes a memory controller (312), a memory device (322), and a channel (332).

The memory controller (312) includes a first transmitter (314) and a first receiver (316). The memory device (322) includes a second transmitter (324) and a second receiver (326). The first transmitter (314) and the first receiver (316) and the second transmitter (324) and the second receiver (326) are connected via a channel (332). According to an embodiment, each of the memory controller (312) and the memory device (322) may include a plurality of transmitters and a plurality of receivers, and may include a plurality of channels for connecting them.

Transmitters (314, 324) output write data to be stored in the memory device (322) or read data read from the memory device (322), a channel (332) transmits the write data or the read data, and receivers (316, 326) receive the write data or the read data. For example, during a data write operation, the transmitter (314) generates a data signal corresponding to the write data and outputs it through the channel (332), and the receiver (326) can receive the data signal and perform the data write operation based thereon. During a data read operation, the transmitter (324) generates a data signal corresponding to the read data and outputs it through the channel (332), and the receiver (316) can receive the data signal and perform the data read operation based thereon.

Transmitters (314, 324) are transmitters according to embodiments of the present invention and can generate data signals in a duobinary format according to embodiments of the present invention. Receivers (316, 326) are receivers according to embodiments of the present invention and can receive data signals in a duobinary format according to embodiments of the present invention.

FIGS. 14a and 14b are cross-sectional views showing a semiconductor package including the memory system of FIGS. 12 and 13.

Referring to FIG. 14a, a semiconductor package (400) includes a package substrate (401), a first semiconductor device (SD1) (410), a second semiconductor device (SD2) (420), and an interposer (430). The semiconductor package (400) may further include a sealing member (440).

The semiconductor package (400) may be a memory package having a stacked chip structure in which a plurality of dies (or chips) are stacked. For example, the semiconductor package (400) may be implemented in a 2.5D structure and may include semiconductor devices and memory devices of the 2.5D chip structure. In this case, the first semiconductor device (410) may include a logic semiconductor device, and the second semiconductor device (420) may include a memory device. For example, the logic semiconductor device may be a host such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), a SoC (System-on-Chip), or an ASIC (Application Specific Integrated Circuit) as a memory controller. For example, the memory device may include a high bandwidth memory (HBM) device.

The package substrate (401) may be a substrate having upper and lower surfaces facing each other. For example, the package substrate (401) may be a printed circuit board (PCB). The printed circuit board may be a multilayer circuit board having vias and various circuits therein.

The interposer (430) may be placed on the package substrate (401). The interposer (430) may be mounted on the package substrate (401) via solder bumps (435). For example, the solder bumps (135) may be C4 bumps. For example, the planar area of the interposer (430) may be smaller than the planar area of the package substrate (401). In other words, the interposer (430) may be placed within the package substrate (401) on a planar surface.

The interposer (430) may include a plurality of connecting wires (431) formed therein and a plurality of through-electrodes (433). For example, the interposer (430) may be a silicon interposer including a silicon substrate, which is a semiconductor substrate, and the plurality of through-electrodes (433) may be through-silicon vias (TSVs) that penetrate the silicon substrate.

The first semiconductor device (410) and the second semiconductor device (420) may be electrically connected to each other and to the package substrate (401) via connecting wires (431) within the interposer (430) and/or via through-electrodes (433) (e.g., through-silicon vias) and solder bumps (435) (e.g., C4 bumps). The silicon interposer may provide high-density interconnections between a plurality of first and second semiconductor chips.

The first semiconductor device (410) and the second semiconductor device (420) may be placed on the interposer (430). The first semiconductor device (410) and the second semiconductor device (420) may be mounted on the interposer (430) by a flip chip bonding method. For example, the first semiconductor device (410) and the second semiconductor device (420) may be mounted on the interposer (430) such that the active surfaces on which the chip pads are formed face the interposer (430). The chip pads of the first semiconductor device (410) and the second semiconductor device (420) may be electrically connected to the connection pads of the interposer (430) by solder bumps (437), which are conductive bumps. For example, the solder bumps (437) may be uBumps.

Although one first semiconductor device (410) and one second semiconductor device (420) are illustrated as being arranged, it will be understood that the present invention is not limited thereto. For example, the second semiconductor device (420) may include a buffer die and a plurality of memory dies (chips) sequentially stacked on the buffer die. The buffer die and the memory dies may be electrically connected to each other by through-silicon vias.

The first semiconductor device (410), the second semiconductor device (420), and the interposer (430) can be fixed with a sealing member (440).

In one embodiment, although not illustrated in detail, the semiconductor package (400) may further include a first adhesive underfilled between the interposer (430) and the package substrate (401), a second adhesive underfilled between the first semiconductor device (410) and the interposer (430), and a third adhesive underfilled between the second semiconductor device (420) and the interposer (430). For example, the first to third adhesives may include an epoxy material to reinforce a gap between the interposer (430) and the package substrate (401) and between the first and second semiconductor devices (410, 420) and the interposer (430).

External connection pads are formed on the lower surface of the package substrate (401), and external connection members (403) may be arranged on the external connection pads for electrical connection with an external device. For example, the external connection members (403) may be solder balls (e.g., BGA (Ball Grid Array)). The semiconductor package (400) may be mounted on a module substrate (e.g., board substrate) via the solder balls to form a memory module.

The first semiconductor device (410) may include an interface (IF) (411) for communicating with the outside of the semiconductor package (400). For example, the interface (411) may include any serial interface. The first semiconductor device (410) may include an interface (413) for communicating with the second semiconductor device (420), and the second semiconductor device (420) may include an interface (421) for communicating with the first semiconductor device (410). For example, the interfaces (413, 421) may each include an HBM PHY section for implementing a memory interface.

In the example of FIG. 14a, the semiconductor substrate (e.g., a silicon substrate), the plurality of connecting wires (431) and the plurality of through-electrodes (433) (e.g., through-silicon vias) included in the interposer (430) may correspond to the channels described above with reference to FIGS. 12 and 13. In addition, the interfaces (411, 413, 421) may include a transmitter and a receiver according to embodiments of the present invention.

Referring to FIG. 14b, a semiconductor package (500) includes a package substrate (501), a first semiconductor device (510), and a second semiconductor device (520). The semiconductor package (500) may further include a sealing member (540).

The semiconductor package (500) of FIG. 14b may be similar to the semiconductor package (400) of FIG. 14a, except that the interposer (430) of FIG. 14a is omitted, the first and second semiconductor devices (510, 520) are stacked in a vertical direction, and the through electrodes and connecting wires are included in the first and second semiconductor devices (510, 520) rather than the interposer (430).

The semiconductor package (500) may be a memory package having a stacked chip structure in which a plurality of dies (or chips) are stacked. For example, the semiconductor package (500) may be implemented in a 3D structure and may include semiconductor devices and memory devices of the 3D chip structure. In this case, the first semiconductor device (510) may include a logic semiconductor device, and the second semiconductor device (520) may include a memory device.

The package substrate (501), external connecting members (503), and sealing member (540) may be substantially identical to the package substrate (401), external connecting members (403), and sealing member (440) of FIG. 14a, respectively.

The first semiconductor device (510) may be placed on a package substrate (501). The first semiconductor device (510) may be mounted on the package substrate (501) by a flip chip bonding method. For example, the first semiconductor device (510) may be mounted on the package substrate (501) such that an active surface on which chip pads are formed faces the package substrate (501). The chip pads of the first semiconductor device (510) may be electrically connected to the connection pads of the package substrate (501) by solder bumps (537) (e.g., uBumps) which are conductive bumps.

The first semiconductor device (510) may include a semiconductor substrate (512) and a wiring layer (514). The semiconductor substrate (512) may include a circuit structure (not shown) such as a transistor, and may include a plurality of through-hole electrodes (533) (e.g., through-hole silicon vias) formed therein. Although not illustrated in detail, the wiring layer (514) may include a plurality of connecting wires (531) and a plurality of vias.

The second semiconductor device (520) may be placed on the first semiconductor device (510). The second semiconductor device (520) may be mounted on the first semiconductor device (510) by a flip chip bonding method. For example, the second semiconductor device (520) may be mounted on the first semiconductor device (510) such that the active surface on which the chip pads are formed faces the first semiconductor device (510). The chip pads of the second semiconductor device (520) may be electrically connected to the through electrodes (533) (e.g., through silicon vias) of the first semiconductor device (510) by solder bumps (535) (e.g., C4 bumps) which are conductive bumps.

The second semiconductor device (520) may include a semiconductor substrate (522) and a wiring layer (524). The semiconductor substrate (522) may include a circuit structure (not shown) such as a transistor. Although not shown in detail, the wiring layer (524) may include a plurality of connecting wires (532) and a plurality of vias.

Although one first semiconductor device (510) and one second semiconductor device (520) are illustrated as being arranged, it will be understood that this is not limiting. For example, at least one other second semiconductor device may be stacked on the second semiconductor device (520). In this case, similar to the first semiconductor device (510), the semiconductor substrate (522) of the second semiconductor device (520) may include through-hole electrodes.

In the example of FIG. 14b, the through-hole electrodes (533), solder bumps (535) and connecting wires (531, 532) within the wiring layers (514, 524) may correspond to the channels described above with reference to FIGS. 12 and 13.

Embodiments of the present invention can be usefully applied to a memory system including a transmitter and a receiver, and various communication devices and systems, and any electronic device and system including the same. For example, embodiments of the present invention can be more usefully applied to electronic systems such as a PC (Personal Computer), a laptop, a cellular phone, a smart phone, an MP3 player, a PDA (Personal Digital Assistant), a PMP (Portable Multimedia Player), a digital TV, a digital camera, a portable game console, a navigation device, a wearable device, an IoT (Internet of Things) device, an IoE (Internet of Everything) device, an e-book, a VR (Virtual Reality) device, an AR (Augmented Reality) device, a drone, and the like.

Although the present invention has been described above with reference to preferred embodiments thereof, it will be understood by those skilled in the art that various modifications and changes may be made to the present invention without departing from the spirit and scope of the present invention as set forth in the claims below.

Claims (10)

A multiplexer that generates a plurality of time-interleaved data signals based on a plurality of binary input data signals input in parallel and having two different voltage levels and multi-phase clock signals;
A control logic for generating a plurality of pull-up control signals having a boosted voltage level for a predetermined time period during which at least one pull-down control signal and a pulse signal have a first level based on the plurality of time-interleaved data signals; and
A transmitter including a voltage mode driver that generates a duobinary type output data signal having three different voltage levels based on at least one pull-down control signal and the plurality of pull-up control signals. In paragraph 1,
The above plurality of input data signals include a first input data signal, a second input data signal, a third input data signal, and a fourth input data signal,
The above multi-phase clock signals include a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal whose phases partially overlap,
The above plurality of time interleaved data signals include a first time interleaved data signal and a second time interleaved data signal,
wherein said at least one pull-down control signal comprises a first pull-down control signal,
The above plurality of pull-up control signals include a first pull-up control signal and a second pull-up control signal,
A transmitter characterized in that the three voltage levels include a first voltage level, a second voltage level higher than the first voltage level, and a third voltage level higher than the second voltage level. In the second paragraph, the multiplexer,
A first transistor connected between a first input node receiving the first input data signal and a first output node providing the first time interleaved data signal, the first transistor having a gate electrode to which the first clock signal is applied;
A second transistor connected between a second input node receiving the second input data signal and a second output node providing the second time interleaved data signal, the second transistor having a gate electrode to which the second clock signal is applied;
A third transistor connected between a third input node receiving the third input data signal and the first output node, the third transistor having a gate electrode to which the third clock signal is applied; and
A transmitter characterized by comprising a fourth transistor connected between a fourth input node receiving the fourth input data signal and the second output node, the fourth transistor having a gate electrode to which the fourth clock signal is applied. In the second paragraph, the control logic,
A first NAND gate performing a NAND operation on the first and second time interleaved data signals;
A NOR gate that performs a NOR operation on the first and second time interleaved data signals to generate the first pull-down control signal;
An inverter that inverts the output of the above NOR gate;
A second NAND gate performing a NAND operation on the output of the first NAND gate and the output of the inverter;
A first boosting circuit for generating the first pull-up control signal based on the output of the first NAND gate; and
A transmitter characterized by including a second boosting circuit for generating the second pull-up control signal based on the output of the second NAND gate. In the fourth paragraph, the first boosting circuit,
A pulse generator connected to an input node receiving an output of the first NAND gate and generating the pulse signal based on the output of the first NAND gate;
A first transistor connected between a first power supply voltage and a first node and having a gate electrode to which the pulse signal is applied;
A capacitor connected between the gate electrode of the first transistor and the first node;
A second transistor connected between the first node and an output node providing the first pull-up control signal and having a gate electrode connected to the input node; and
A transmitter characterized by comprising a third transistor connected between the output node and the ground voltage and having a gate electrode connected to the input node. In the second paragraph, the voltage mode driver,
A first transistor connected between an output node providing the output data signal and a ground voltage having the first voltage level, and having a gate electrode receiving the first pull-down control signal;
A second transistor connected between the first power supply voltage having the third voltage level and the output node and having a gate electrode receiving the second pull-up control signal; and
A transmitter characterized by comprising a third transistor connected between a second power supply voltage having the second voltage level and the output node and having a gate electrode receiving the first pull-up control signal. A first flip-flop which receives a duobinary input data signal having three different voltage levels and generates a binary first output data signal having two different voltage levels based on the input data signal, a first clock signal, a first reference voltage, and a first selection signal; and
A second flip-flop is included which receives the input data signal and generates the second output data signal in binary format based on the input data signal, a second clock signal different from the first clock signal, the first reference voltage, and a second selection signal.
The second output data signal is provided as the first selection signal, and the first output data signal is provided as the second selection signal.
A receiver in which the first flip-flop forms a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal. In the seventh paragraph, the first flip-flop,
A first circuit unit including a first structure for generating a first data signal and a second data signal based on a power supply voltage, the input data signal, the first clock signal, the first reference voltage, and the first selection signal, and a second structure for forming the second reference voltage and boosting the first and second data signals;
A second circuit unit generating a third data signal and a fourth data signal based on the power supply voltage, the first and second data signals, and the first clock signal; and
A receiver characterized by including an output unit that generates the first output data signal based on the third and fourth data signals. In the 8th paragraph, the first circuit part,
First, second and third transistors connected in parallel between a first node and a first data node providing the first data signal, and each having a gate electrode connected to a second data node providing the power supply voltage, the input data signal and the second data signal;
Fourth, fifth and sixth transistors connected in parallel between the first node and the second data node, each having a gate electrode connected to the first data node, the first reference voltage and the first selection signal;
A seventh transistor connected between the power supply voltage and the first node and having a gate electrode receiving the first clock signal;
An eighth transistor connected between the first data node and the ground voltage and having a gate electrode receiving the first clock signal; and
A receiver characterized by comprising a ninth transistor connected between the second data node and the ground voltage and having a gate electrode receiving the first clock signal. A transmitter for outputting write data to be stored in a memory device or read data read from the memory device;
a channel for transmitting the above-mentioned write data or the above-mentioned read data; and
Including a receiver that receives the above write data or the above read data,
The above transmitter,
A multiplexer that generates a plurality of time-interleaved data signals based on a plurality of binary input data signals input in parallel and having two different voltage levels and multi-phase clock signals;
A control logic for generating a plurality of pull-up control signals having a boosted voltage level for a predetermined time period during which at least one pull-down control signal and a pulse signal have a first level based on the plurality of time-interleaved data signals; and
A voltage mode driver is included that generates a duobinary type output data signal having three different voltage levels based on at least one pull-down control signal and the plurality of pull-up control signals.
The above receiver,
A first flip-flop that receives the output data signal and generates the first data signal in binary format based on the output data signal, the first clock signal, the first reference voltage, and the first selection signal; and
A second flip-flop is included which receives the output data signal and generates the second data signal in binary format based on the output data signal, a second clock signal different from the first clock signal, the first reference voltage, and a second selection signal.
The second data signal is provided as the first selection signal, and the first data signal is provided as the second selection signal.
The first flip-flop forms a second reference voltage different from the first reference voltage based on the first reference voltage and the first selection signal,
A memory system wherein the plurality of input data signals, the output data signal, and the first and second data signals correspond to the write data or the read data.

Images