KR102178470B1 - Display device having a flexible film cable - Google Patents

Abstract

The present invention relates to a display device, comprising: a display panel including a pixel array in which data lines and gate lines cross and pixels are arranged in a matrix form; A source drive IC supplying data voltages to the data lines; A gate drive IC for supplying a gate pulse to the gate lines; And a first flexible film cable bonded to a substrate of the display panel and formed with wires for transferring gate timing control signals and gate driving powers to the gate drive IC supplied from the printed circuit board (PCB).

Description

Display device having a flexible film cable {DISPLAY DEVICE HAVING A FLEXIBLE FILM CABLE}

The present invention relates to a display device having a flexible film cable.

Flat panel displays include Liquid Crystal Display Device (LCD), Plasma Display Panel (PDP), Organic Light Emitting Display Device (OLED), and Electrophoretic Display Device: EPD). The liquid crystal display displays an image by controlling an electric field applied to liquid crystal molecules according to a data voltage. Active matrix type liquid crystal display devices have been applied to almost all display devices, from small mobile devices to large TVs, and are widely used because of lower cost and higher performance thanks to the development of process technology and driving technology.

Since the organic light-emitting display device is a self-luminous device, power consumption is lower than that of a liquid crystal display device requiring a backlight, and can be manufactured to be thinner. In addition, the organic light emitting display device has a wide viewing angle and a fast response speed. The organic light emitting display device is attracting attention as a next-generation display device that can replace a liquid crystal display device.

The pixels of the organic light emitting display device include organic light emitting diodes (hereinafter referred to as "OLED") which are self-luminous devices. OLED is a hole injection layer (HIL), a hole transport layer (HTL), an emission layer (EML), an electron transport layer (ETL), and an electron injection layer (EIL). ) And organic compound layers. OLEDs generate light as electrons and holes combine in the organic material layer by flowing electric current through a fluorescent or phosphorescent organic material thin film.

Organic light emitting display devices include a source drive IC (integrated circuit) that generates a data voltage, a gate drive IC that generates a gate pulse (or scan pulse) synchronous to the data voltage, and a timing controller that controls the operation timing of these drive ICs. Display panel driving circuits are required. The timing controller transmits the digital video data of the input image to the source drive ICs. The timing controller includes a source timing control signal for controlling the operation timing of the source drive ICs and gate timing control signals for controlling the operation timing of the gate drive ICs. The gate timing control signals are transmitted to the gate drive ICs through a flexible circuit board such as a flexible flat cable (Flexible Flat Circuit, hereinafter referred to as "FFC") or a flexible print circuit (hereinafter referred to as "FPC"). I can. The FPC is connected to the PCB by manually inserting it into a connector installed on a printed circuit board (hereinafter referred to as "PCB"), and on the display panel through an anisotropic conductive film ("ACF"). It can be bonded. In addition, the FPC may be bonded to the PCB and the display panel by ACF. Both ends of the FFC are connected through connectors. Accordingly, the FFC is connected to a connector mounted on the source PCB and a connector connected to the gate PCB when connecting the source PCB to the gate PCB.

A flexible circuit board such as FFC or FPC has a structure in which a film having a thickness of 300 to 350 μm and a large elastic modulus is bonded to multiple layers. For this reason, when the flexible circuit board is bent and the PCB is disposed behind the display panel, a crack may occur in the flexible circuit board, or a crack may occur in the bonding surface of the FFC or the FPC and the display panel. Accordingly, when a flexible circuit board is bonded to a display panel and the flexible circuit board is bent, many defects have occurred.

The high-potential pixel power voltage EVDD and the low-potential pixel power voltage EVSS are supplied to the pixels of the OLED display. However, if the EVDD wiring supplying the high-potential pixel power supply voltage (EVDD) and the EVSS wiring supplying the low-potential pixel power supply voltage (EVSS) are short-circuited (or short-circuited), a burnt out may occur at that part. have.

The present invention provides a display device capable of preventing cracks from occurring in a flexible circuit board and preventing ignition of the display panel when a flexible circuit board bonded to the display panel is bent.

The display device of the present invention includes: a display panel including a pixel array in which data lines and gate lines cross and pixels are arranged in a matrix form; A source drive IC supplying data voltages to the data lines; A gate drive IC for supplying a gate pulse to the gate lines; And a first flexible film cable bonded to a substrate of the display panel and formed with wires for transferring gate timing control signals and gate driving powers to the gate drive IC supplied from the printed circuit board (PCB).

The first flexible film cable has a thickness between 20 μm and 100 μm.

The present invention transmits a gate timing control signal and a gate driving power to a gate drive IC through a flexible film cable having an easy to bend structure. As a result, according to the present invention, the PCB can be folded behind the display panel without defect, and furthermore, the distance between the high-potential pixel power supply voltage wirings and the low-potential pixel power supply voltage wirings is increased, resulting in a short circuit between wirings having a potential difference. It can prevent fire.

1 is a plan view schematically illustrating an organic light emitting display device according to a first exemplary embodiment of the present invention.
2 is an equivalent circuit diagram showing a pixel in the organic light emitting display device of the present invention.
3 is a cross-sectional view showing the structure of a FOG film and a COF film according to an embodiment of the present invention compared with a conventional FPC film.
FIG. 4 is a cross-sectional view illustrating a state in which the FOG film and the COF film shown in FIG. 3 are bent and the source PCB is folded behind the display panel.
5 and 6 are plan views showing various mounting methods of a gate driving circuit.
7 is a plan view showing in detail a display device of the present invention.
FIG. 8 is an enlarged plan view of a left source PCB and a portion of a display panel below it in FIG. 7.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals throughout the specification mean substantially the same constituent elements. In the following description, when it is determined that detailed descriptions of known functions or configurations related to the present invention may unnecessarily obscure the subject matter of the present invention, detailed descriptions thereof will be omitted.

In the following embodiments, it should be noted that the display device of the present invention is mainly described with an organic light emitting display device, but is not limited thereto.

1 and 2, the organic light emitting display device of the present invention includes a display panel 10, a source PCB 30, a control PCB 36, a flexible circuit film 12, 16, 38, a flexible film cable ( 20) and the like.

The display panel 10 may be made of a glass substrate, a plastic substrate, or a metal substrate. The display panel 10 includes a pixel array 11 for reproducing an input image. The pixel array 11 includes data lines 24 to which a data voltage is supplied, gate lines 26 to which a gate pulse is supplied, and pixels 28 arranged in a matrix form. Each of the pixels 28 includes a switch TFT (Thin Film Transistor, ST), a driving TFT (DT), and an OLED. The switch TFT ST supplies a data voltage to the gate of the driving TFT DTP in response to the gate pulse SCAN. The driving TFT (DT) is connected between the high-potential pixel power voltage line to which the high-potential pixel power voltage (EVDD) is supplied and the OLED and controls the current flowing through the OLED according to the data voltage applied to its gate. Each of the pixels 28 may have a built-in compensation circuit for compensating the threshold voltage and mobility of the driving TFT DT. The compensation circuit can be applied to any known compensation circuit.

The source PCB 30 is formed with wirings 71 to 74 for transmitting power and signals required for driving the source drive IC 14 and the gate drive IC 18 as shown in FIG. 8. As shown in FIG. 7, when the display panel 10 becomes larger, the source PCB 30 may be divided into two and bonded to the display panel 10.

Circuits such as a timing controller 32 and a power IC 34 are mounted on the control PCB 36. The timing controller 32 receives digital video data and a timing signal of an input image from the outside and transmits the digital video data to the source drive ICs 14. The control PCB 36 may be connected to the source PCB 30 through the flexible circuit film 38 and connectors 39a and 39b. The flexible circuit film 38 may be implemented as a conventional FFC film or FPC film.

The timing controller 32 transmits digital video data (DATA in FIG. 8) of an input image input from an external host system to the source drive ICs 14. The timing controller 32 uses a timing signal received from an external host system to control the source timing control signal for controlling the operation timing of the source drive ICs 14 and the operation timing of the gate drive IC 18. To generate a gate timing control signal. The gate timing signal (Fig. 8, GCS) includes a gate start pulse (GSP), a gate output enable signal (Gate Output Enable, GOE), and a gate shift clock signal (Gate Shift Clock, GSC). The gate start pulse is input to a shift register of the gate drive IC 18 to control the start timing of the shift register. The gate output enable signal GOE controls the output timing of the gate drive IC 18. The gate shift clock signal GSC controls the shift timing of the shift register of the gate drive IC 18.

The host system may be implemented as any one of a TV (Television) system, a set-top box, a navigation system, a DVD player, a Blu-ray player, a personal computer (PC), a home theater system, and a phone system.

The power IC 34 includes power (EVDD, EVSS) applied to the pixels 28 of the display panel 10, a power supply (VCC) of the source and gate drive ICs 14 and 19, and a gamma compensation voltage (VGMA). Generates gate driving power sources (VGH, VGL) and the like. The gate driving power source includes a gate high voltage VGH and a gate low voltage VGL. The gate high voltage VGH and the gate low voltage VGL are supplied to the gate drive IC 18. The gate high voltage VGH is generated with a voltage higher than the threshold voltage of the switch TFT ST. The gate low voltage VGL is generated with a voltage lower than the threshold voltage of the switch TFT ST. The gate pulse output from the gate drive IC 18 swings between the gate high voltage VGH and the gate low voltage VGL. The gate pulse may be divided into an initialization pulse for initializing the gate of the driving TFT DT, a scan pulse synchronized with a data voltage, and a light emission control pulse for controlling the timing of emission of the OLED. The initialization pulse, scan pulse, light emission control pulse, and the like are independently applied through different gate lines and are sequentially shifted along the scan direction.

The gate timing signal (GSC) and the gate driving power supply (VGH, VGL) connect the source PCB 30, the flexible film cable 20, the line on glass (LOG) wirings 40, and the gate flexible circuit film 16. Through the gate drive IC 18. When the data lines 24 or the gate lines 26 of the pixel array 11 are formed, the LOG wirings 40 are formed directly on the substrate of the display panel 10 using the same metal as the wiring lines. The LOG wirings 40 electrically connect the flexible film cable 20 and the gate flexible circuit film 16 to provide a gate timing signal GSC and a gate driving power supply (VGH, VGL) from the flexible film cable 20. It is transferred to the gate flexible circuit film 16.

The source drive ICs 14 are mounted on the source flexible circuit film 12. The input terminals of the source flexible circuit film 12 are bonded to the source PCB 30 with ACF. The output terminals of the source flexible circuit film 12 are ACF bonded to the substrate of the display panel 10 and the source PCB 30 to be connected to the data lines 24. The digital video data DATA and the source timing control signal are transmitted to the source drive ICs 14 through wirings formed on the source PCB 30 and the source flexible circuit film 12. The source timing signal includes a source start pulse of the source drive IC 14, a source shift clock, an ADC clock, a source output enable signal, and the like.

The source drive ICs 14 receive digital video data DATA of an input image received from the timing controller 32. The source drive ICs 14 convert digital video data (DATA) to gamma compensation voltage (VGMA) using an analog-to-digital converter (Analog to Digital Convertor, hereinafter referred to as "ADC") to convert the data voltage (Fig. 8, Vd) occurs. The data voltage (Vd in FIG. 8) is supplied to the pixels 28 through the data line 24. The data voltage Vd output from the source drive ICs 14 is supplied to the data lines 24 of the pixel array 11 through wirings and data link patterns formed on the source flexible circuit film 12.

The gate drive IC 18 is mounted on the gate flexible circuit film 16. The gate flexible circuit film 14 is bonded to the substrate of the display panel 10 to be connected to the LOG wirings 40 and the gate lines 26. Although one IC is illustrated in FIG. 1 as the gate drive IC 18, the number of the gate drive IC 18 increases as the display panel 10 increases. In addition, the gate drive IC 18 has a larger display panel 10 and may be bonded to the left and right sides of the display panel 10. The gate drive IC 18 sequentially supplies a gate pulse to the gate lines 26.

The flexible film cable 20 is implemented with a film on glass (FOG) film shown in FIG. 3. The source flexible circuit film 12 and the gate flexible circuit film 14 are implemented as a chip on film (COF) film shown in FIG. 3. The source flexible circuit film 12 and the gate flexible circuit film 14 have substantially the same cross-sectional structure as the flexible film cable 20 except for the source/gate drive ICs 14 and 18.

The FOG film includes a polyimide film 52, metal wires 54 formed on the polyimide film 52, metal wires 54, and polyimide film 52 as shown in FIG. 3. And a covering solder resist 56. The metal wires 54 may be formed of copper wires. In the FOG film, the total thickness t1 of the polyimide film 52, the metal wirings 54, and the solder resist 56 is as thin as 20 μm to 100 μm. The COF film is substantially the same as the FOG film in terms of the laminated film structure and thickness (t1). The COF film is different from the FOG film in that the source drive IC 12 or the gate drive IC 14 is mounted. In other words, no IC is mounted on the FOG film, only wiring is formed. The FOG film and the COF film are bonded onto the substrate of the source PCB 30 and the display panel 10 with the ACF 21 without a connector as shown in FIG. 4. The ACF bonding process is automated through surface mount technology equipment. Accordingly, a process of bonding the FOG film and the COF film to the substrate of the source PCB 30 or the display panel 10 by the ACF 21 can be completely automated without manual labor.

As for the source PCB 30, as shown in FIG. 4, the FOG film and the COF film have a smaller number of stacked film layers and thinner than that of the conventional FFC or FPC, as shown in FIG. Accordingly, the FOG film and the COF film are easily bent without cracks, so that the source PCB 30 can be disposed behind the display panel 10 as shown in FIG. 4.

The FPC film may be manufactured in a single-sided coverlay structure and a double-sided coverlay structure as shown in FIG. 4. The single-sided coverlay structure includes a coverlay 68 formed on an upper surface of the base layer 64 and a reinforcement 62 bonded to the lower surface of the base layer 64. The coverlay 68 is made of polyimide film. The base layer 64 includes a polyimide film and a copper foil pattern formed on the polyimide film. The reinforcing layer 62 is made of a polyimide film or a PET (poly-ethylene terephthalate) film and serves as a reinforcing plate when the FPC is bent or compressed. The double-sided coverlay structure includes an upper coverlay 68a formed on the upper surface of the base layer 64, a lower coverlay 68b formed on the lower surface of the base layer 64, and a reinforcing layer adhered to the lower surface of the lower coverlay 68b. 62). The thickness (t2, t3) of the FPC film is about 300 to 350 μm, which is much thicker than the FOG film and the COF film. In addition, the FPC film has a larger number of laminated films than the FOG film and the COF film. Therefore, the FFC film or the FPC film has a higher elasticity than that of the FOG film and the COF film, so that when it is bent, the tension is large and cracks are likely to occur.

The gate drive IC 17 may be directly formed on the substrate of the display panel 10 by a GIP (Gate In Panel) process as shown in FIG. 5. The GIP process technique forms the circuit of the gate drive IC 17 on the substrate at the same time as the pixel array 11. The gate timing signal (GSC) and gate driving power supplies (VGH, VGL) required for driving the gate drive IC 17 are provided through the source PCB 30, the flexible film cable 20, and the LOG wires 40. It is sent to (17).

The gate drive IC 19 may be directly bonded to the substrate of the display panel 10 through a chip on glass (COG) process as shown in FIG. 6. The COG type gate drive IC 19 is adhered to the substrate of the display panel 10 with ACF. The gate timing signal (GSC) and gate driving power supplies (VGH, VGL) required for driving the gate drive IC 19 are gated through the source PCB 30, the flexible film cable 20, and the LOG wires 40. It is transmitted to the IC 19.

The present invention provides a short circuit between EVDD wirings and EVSS wirings using flexible film cables 20 and 21 as shown in FIGS. 7 and 8 in order to improve the ignition problem due to short circuit of wirings having a potential difference in an organic light emitting display device. Prevent.

7 and 8, a first wiring group 71, a second wiring group 72, a third wiring group 73, and a fourth wiring group 74 are formed on the source PCBs 30a and 30b. do.

The first wiring group 71 is formed between the connector 39a and the first flexible film cable 20 to transmit the gate timing signal GSC and the gate driving power supplies VGH and VGL to the gate drive IC 19. do. The first flexible film cable 20 and the gate drive IC 19 are connected by a LOG wiring 40.

The second wiring group 72 transfers the power sources S-VCC and G-VCC of the source drive IC 14 and the gate drive IC 19 to the source drive IC 14 and the gate drive IC 19. The power supply (G-VCC) of the gate drive IC is transmitted to the gate drive IC 19 via the first flexible film cable 20 and the LOG wiring 40. The power source (S-VCC) of the source drive IC is applied to the source drive IC 14 through the flexible circuit film 12.

The third wiring group 73 applies the high-potential pixel power voltage EVDD and the low-potential pixel power voltage EVSS to the flexible film cables 20 and 21 and the flexible circuit film on which the source drive IC 14 is mounted. 12). The high potential pixel power voltage EVDD is applied to the pixels of the display panel 10 through wirings of dummy channels of the flexible circuit film 12. The flexible circuit film 12 has no wiring to which the low potential power supply voltage EVSS is applied. The low-potential pixel power voltage EVSS is applied to the pixels of the display panel 10 only through the first and second flexible film cables 20 and 21. The flexible circuit film 12 and the flexible film cables 20 and 21 are separated by a predetermined distance and are bonded to the substrate of the display panel 10. Accordingly, even if the substrates of the flexible circuit film 12 and the display panel 10 are mis-aligned, or the substrates of the flexible film cables 20 and 21 and the display panel 10 are misaligned, EVDD wiring and EVSS Since the wiring is not short-circuited, a fire problem can be prevented.

The fourth wiring group 74 transmits digital video data DATA of an input image, a source shift clock CLK, a gamma compensation voltage VGMA, and the like to the source drive IC 14.

The first flexible film cable 20 is formed on the left and right edges (bezel) of the display panel 10 close to the gate drive IC 19. The first flexible film cable 20 is made of a FOG film as shown in FIG. 3 and is easily bent. The first flexible film cable 20 includes a wiring connected to the first wiring group 71 to receive a gate timing signal GSC and gate driving power supplies VGH and VGL through the first wiring group 71 do. In addition, the first flexible film cable 20 includes a wire connected to the EVSS wires of the third wire group 73 to receive a low-potential pixel power voltage EVSS. Further, the first flexible film cable 20 includes a wiring connected to the G-VCC wiring of the second wiring group 72.

The flexible circuit film 12 on which the source drive IC 14 is mounted is disposed between the first flexible film cable 20 and the second flexible film cable 21. The second flexible film cable 21 is made of a FOG film as shown in FIG. 3 and is easily bent. The second flexible film cable 21 includes a wire connected to the EVSS wires of the third wire group 73 to receive the low-potential pixel power voltage EVSS. The second flexible film cable 21 has no EVDD wiring.

The flexible circuit film 12 is made of a COF film as shown in FIG. 3 and is easily bent. The flexible circuit film 12 is disposed between the first flexible film cable 20 and the second flexible film cable 21, or between adjacent second flexible film cables 21. The flexible circuit film 12 includes a wiring connected to the S-VCC wiring of the second wiring group 72, a dummy channel wiring connected to the EVDD wiring of the third wiring group 73, and the fourth wiring group 74. Includes wires connected to wires.

It will be appreciated by those skilled in the art through the above description that various changes and modifications can be made without departing from the technical idea of the present invention. Therefore, the technical scope of the present invention should not be limited to the content described in the detailed description of the specification, but should be determined by the claims.

10: display panel 12, 16: flexible circuit film (COF)
14: source drive IC 15: dummy wiring formed on the flexible circuit film
16: gate drive IC 20, 21: flexible film cable (FOG)
30: source PCB 32: timing controller
34: power IC 36: control PCB
40: LOG wiring

Claims (13)

A display panel including a pixel array in which data lines and gate lines cross and pixels are arranged in a matrix form;
A source drive IC supplying data voltages to the data lines;
A gate drive IC for supplying a gate pulse to the gate lines;
A first flexible film cable bonded to a substrate of the display panel and formed with wires for transmitting gate timing control signals and gate driving power supplied from a printed circuit board (PCB) to the gate drive IC; And
A second flexible film cable to which a low-potential pixel power supply voltage is supplied; Including,
A flexible circuit film is disposed between the first flexible film cable and the second flexible film cable, or the flexible circuit film is disposed between adjacent second flexible film cables,
At least one of the first flexible film cable and the second flexible film cable has a thickness between 20 μm and 100 μm. The method of claim 1,
The first flexible film cable,
A display device comprising wires to which a low-potential pixel power voltage (EVSS) is supplied. The method of claim 1,
The first flexible film cable,
A display device comprising a polyimide film, metal wires formed on the polyimide film, and a solder resist covering the metal wires and the polyimide film. The method of claim 1,
The source drive IC is mounted on the flexible circuit film,
The display device according to claim 1, wherein the flexible circuit film has a thickness between 20 μm and 100 μm. The method of claim 1,
The display device, wherein the cross-sectional structure of the flexible circuit film excluding the source drive IC is substantially the same as that of the first flexible film cable. The method of claim 1,
The flexible circuit film,
A display device comprising wires to which a high potential pixel power voltage (EVDD) is supplied.
delete delete delete The method of claim 6,
The display device, wherein the cross-sectional structure of the flexible circuit film excluding the source drive IC is substantially the same as that of the first flexible film cable and the flexible circuit film. The method of claim 10,
Including a LOG wiring connecting the first flexible film cable and the gate drive IC,
The LOG wiring is formed directly on a substrate of the display panel. The method of claim 11,
The first flexible film cable, the second flexible film cable, and the flexible circuit film are bonded to the printed circuit board (PCB) and the substrate of the display panel through an anisotropic conductive film (ACF),
The printed circuit board (PCB) is a display device, wherein the first flexible film cable, the second flexible film cable, and the flexible circuit film are bent and disposed behind the display panel. The method of claim 12,
The printed circuit board (PCB) is
A first wiring group to which a gate timing signal to be transmitted to the gate drive IC and gate driving power are supplied;
A second wiring group to which power is supplied to the source drive IC and the gate drive IC;
A third wiring group to which the high potential pixel power voltage EVDD and the low potential pixel power voltage EVSS are supplied; And
A display device comprising: a fourth wiring group to which digital video data of an input image and a clock and a gamma compensation voltage are supplied.

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