KR101684285B1 - Segmented digital analog converter reducing layout area - Google Patents

Abstract

A split digital-to-analog converter that reduces the layout area is posted. The rough DAC block of the divided DAC of the present invention includes a plurality of select voltage generating groups formed between respective low undervoltage and each node high voltage and each of the first select voltage and the second select voltage, A plurality of selection voltage generating groups for generating a selection voltage in each of a first selection stage and a second selection stage; A logic group for generating said selection signal group; The first selection voltage of the first selection stage of the selection voltage generating group specified is set to the first preliminary voltage of the first preliminary stage and the second selection voltage of the second selection stage is set to the second preliminary voltage of the second preliminary stage Said measure selection group providing a reserve voltage; And supplying a low level voltage of the first preliminary voltage and the second preliminary voltage as the first coarse voltage to the first output terminal, and supplying a high level voltage of the first preliminary voltage and the second preliminary voltage, And a polarity switching group driven to provide the second coarse voltage to the second output terminal. In the divided DAC according to the present invention, as one divided voltage is transmitted to the fixed spare stage via one path, a path provided with the first coarse voltage and the second coarse voltage with respect to one divided voltage The number of switches for transmitting the divided voltage is significantly reduced as compared with the prior art that exists separately.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a divide-

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital-to-analog converter (DAC), and more particularly to a divided DAC for reducing a layout area.

As the number of gradations required in recent DACs increases, the demand for a split DAC is increasing. Generally, a split DAC consists of a coarse DAC block and a fine DAC block. The coarse DAC block outputs two coarse voltages obtained by performing digital-analog conversion according to the bit values of the M upper data bits among the data bits (M + N bits) constituting the digital data. At this time, the coarse DAC block using the resistance column performs digital-analog conversion using 2 ^M resistors connected in series.

The fine DAC block includes an analog voltage obtained by interpolating the two coarse voltages according to the bit value of the N lower data bits among the data bits (M + N bits) constituting the digital data (the final output voltage ).

1 shows a rough DAC block applied to a conventional split DAC, where M is 3; The rough DAC block of Fig. 1 includes a resistor string 10 having eight resistors R1 to R8 formed in series between eight reference low voltages VRLW and VRHG. At this time, nine divided voltages VRC1 to VRC9 are generated by the eight resistors R1 to R8.

One of the eight resistors R1 to R8 constituting the resistance column 10 is specified according to the bit values of the three upper data bits MBT1, MBT2 and MBT3. Then, the divided voltage of the low terminal of the specified resistor is supplied to the first coarse voltage VCAS1, and the divided voltage of the high terminal is provided to the second coarse voltage VCAS2.

However, in the rough DAC block of FIG. 1, there is a path provided with the first coarse voltage and a path provided with the second coarse voltage separately for one divided voltage.

That is, the first divided voltage transfer section 20 disposed on the right side has a relatively low level of the eight divided voltages VRC1 to VRC8 according to the bit values of the three upper data bits MBT1, MBT2 and MBT3 Is generated as the first coarse voltage VCAS1.

The second divided voltage transfer unit 30 disposed on the left side of the first divided voltage transfer unit 30 has a relatively high level of the eight divided voltages VRC2 to VRC9 according to the bit values of the three upper data bits MBT1, MBT2 and MBT3 Is generated as the second coarse voltage VCAS2.

As described above, in the rough DAC block of FIG. 1, a large number of switches are required as a whole because the path provided by the first coarse voltage and the path provided by the second coarse voltage exist for one divided voltage separately. As a result, the divided DAC including the rough DAC block of FIG. 1 has a disadvantage that the required layout area is large.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems of the prior art, and to provide a divided DAC that reduces the number of switches required for a rough DAC block and reduces the layout area as a whole.

According to an aspect of the present invention, there is provided a method of converting digital data composed of M upper data bits and N lower data bits (where N is a natural number) into analog voltages And a segmented DAC for outputting the divided data. The divided DAC according to the present invention divides the reference high voltage for the reference low voltage according to the bit value of the M upper data bits to output a first coarse voltage to the first output terminal and a second coarse voltage to the second output terminal, A coarse DAC block outputting a coarse voltage; And a fine DAC block outputting the analog voltage generated by interpolating the first coarse voltage and the second coarse voltage according to a bit value of the N (where N is a natural number) lower data bit. The rough DAC block includes a plurality of select voltage generating groups formed between each of the node low voltages and the node high voltages included between the reference low voltage and the reference high voltage, A plurality of selection voltage generating groups for generating a selection voltage and a second selection voltage in each of a first selection stage and a second selection stage; A logic group for generating the selection signal group using a bit value of k upper data bits, k being a natural number smaller than M, where k is a number greater than 2 and a part of the upper data bits; (Mk) upper data bits, which are the remaining part of the upper data bits, as a node selection group that specifies any one of the plurality of selection voltage generation groups, The node selection group providing the first selection voltage of a selected node to a first preliminary voltage of a first preliminary stage and the second selection voltage of the second selected node to a second preliminary voltage of a second preliminary stage; And supplying a low level voltage of the first preliminary voltage and the second preliminary voltage as the first coarse voltage to the first output terminal, and supplying a high level voltage of the first preliminary voltage and the second preliminary voltage, And a polarity switching group driven to provide the second coarse voltage to the second output terminal.

In the divided DAC according to the present invention, as one divided voltage is transmitted to the fixed spare stage through one path, the path in which the first coarse voltage and the second coarse voltage are provided for one divided voltage The number of switches for transmitting the divided voltage is significantly reduced as compared with the prior art that exists separately.

A brief description of each drawing used in the present invention is provided.
1 is a diagram showing a rough DAC block applied to a conventional divided DAC.
2 is a diagram showing a divided DAC according to an embodiment of the present invention.
FIG. 3 is a diagram specifically showing the rough DAC block of FIG. 2. FIG.
4 is a diagram for explaining a path in which the first coarse voltage and the second coarse voltage are selected in the coarse DAC block of FIG.

For a better understanding of the present invention and its operational advantages, and the objects attained by the practice of the present invention, reference should be made to the accompanying drawings, which illustrate preferred embodiments of the invention, and the accompanying drawings. However, the present invention is not limited to the embodiments described herein but may be embodied in other forms. Rather, the embodiments disclosed herein are being provided so that this disclosure will be thorough and complete, and will fully convey the concept of the invention to those skilled in the art.

It should be noted that, in understanding each of the drawings, the same members are denoted by the same reference numerals whenever possible. In the present specification, the same reference numerals are used for components that perform the same configurations and functions, and reference numerals are added to <&gt;. At this time, these components are collectively referred to as reference numerals. If they need to be distinguished from each other, '<>' is added after the reference character.

Also, a plurality of expressions for each component may be omitted. For example, even if the switch is composed of a plurality of switches, it may be expressed as 'switches', or may be expressed as a single number such as 'switch'. This is because the switches may operate complementarily with each other, and sometimes operate independently. In this respect, such description is reasonable. Accordingly, similar expressions should be construed in the same sense throughout the specification.

In order to fully understand the operational advantages of the present invention and the objects attained by the practice of the present invention, reference should be made to the following description taken in conjunction with the accompanying drawings and accompanying drawings which illustrate exemplary embodiments of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a diagram showing a divided DAC according to an embodiment of the present invention. Referring to FIG. 2, the divided DAC of the present invention includes digital data (DDAT) composed of M upper data bits and M (where N is a natural number) And converts it to a voltage (VANG) and outputs it.

In the present embodiment, M is 3, and the upper data bits are MBT1, MBT2, and MBT3. N is 2, and the lower data bits are LBT1 and LBT2.

The divided DAC of the present invention comprises a rough DAC block (CADAC) and a fine DAC block (FNDAC).

The rough DAC block CADAC divides the reference high voltage VRHG for the reference low voltage VRLW according to the bit value of the upper data bits MBT1, MBT2 and MBT3, Outputs the coarse voltage VCAS1, and outputs the second coarse voltage VCAS2 to the second output terminal NUT2.

FIG. 3 is a diagram showing a specific example of the rough DAC block (CADAC) of FIG.

Referring to FIG. 3 together with FIG. 2, the coarse DAC block CADAC includes a plurality of select voltage generating groups 100 <1> and 100 <2>, a logic group 200, a node selection group 300, Polarity switching group (400).

In this embodiment, the coarse DAC block CADAC is shown to include two select voltage generating groups, but may include four, eight, etc. select voltage generating groups.

Each of the plurality of select voltage generating groups 100 <1> and 100 <2> includes a plurality of select voltage generating groups VML <1> and VML <2> included between the reference low voltage VRLW and the reference high voltage VRHG, 2 &gt;) and their respective node high voltages VMH &lt; 1 &gt;, VMH &lt; 2 &gt;.

Each of the plurality of selection voltage generation groups 100 <1> and 100 <2> includes a first selection voltage VSL1 selected by the selection signal group GXSL provided in the logic group 200, (NSL1 <1>, NSL1 <2>) and the second selection stage (NSL2 <2>) and the second selection voltages VSL2 < &Lt; 1 &gt;, NSL2 &lt; 2 &gt;).

In the present embodiment, the selection signal group GXSL includes the first to fifth selection signals XSL1 to XSL5.

3, the node high voltage VMH <1> of the selection voltage generation group 100 <1> and the node low voltage VML <2> of the selection voltage generation group 100 <2> are the same. The node low voltage VML <1> of the selection voltage generation group 100 <1> is the reference low voltage VRLW and the node high voltage VMH <2> of the selection voltage generation group 100 < Is the reference high voltage (VRHG).

In addition, the plurality of select voltage generating groups 100 have only a difference in node low voltage VML and node high voltage VMH, and have a similar configuration and action as a whole.

Therefore, in the present specification, for the sake of simplicity of explanation, the select voltage generation group 100 <1> shown below is representatively described.

The selection voltage generation group 100 <1> includes a resistance column 110 <1> and a voltage division transfer unit 130 <1>.

The resistor string 110 <1> is connected in series with the resistor string 110 to generate (i + 1) divided voltages VML <1> (R1 <1>, R2 <1>, R2 <1>, and R3 <1>) in the order of generating the resistors (VDV1 <1>, VDV2 <1>, VDV3 <1>, VDV4 < &Gt;, R4 < 1 >).

Here, i is a natural number of 4 or more, and can be 8, 16, and so on. In Fig. 3, the case where i = 4 is representatively shown.

At this time, the first divided voltage VDV1 <1> is equal to the divider voltage VML <1>, and the fifth divided voltage VDV5 <1> is equal to the divider high voltage VMH <1> Do.

The divided voltage transfer unit 130 <1> is connected to two consecutive divided voltages among the divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1> and VDV4 < To provide the first selection stage NSL1 <1> and the second selection stage NSL2 <1>.

At this time, the first selection node NSL1 <1> is an odd-numbered one among the plurality of divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1>, VDV4 < And receives the divided voltages VDV1 <1>, VDV3 <1> and VDV5 <1> as the first selection voltage VSL1 <1>. The second selection node NSL2 <1> is an even-numbered one among the plurality of divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1> and VDV4 < And receives the divided voltages VDV2 <1> and VDV4 <1> as the second selection voltage VSL2 <1>.

The partial pressure transfer unit 130 <1> specifically includes first to fifth node selection switches 131 <1> to 135 <1>.

The first node selection switch 131 <1> transmits the first divided voltage VDV1 <1> to the first selected node NSL1 <1> in response to the first selection signal XSL1 . The second node selection switch 132 <1> transmits the second divided voltage VDV2 <1> to the second selected node NSL2 <1> in response to the second selection signal XSL2 .

The third node selection switch 133 <1> transmits the third divided voltage VDV3 <1> to the first selection node NSL1 <1> in response to the third selection signal XSL3 . The fourth node selection switch 134 <1> transmits the fourth divided voltage VDV4 <1> to the second selection node NSL2 <1> in response to the fourth selection signal XSL4 .

In response to the fifth selection signal XSL5, the fifth node selection switch 135 <1> switches the fifth divided voltage VDV5 <1> to the first selection node NSL1 <1> send.

The logic group 200 generates the selection signal group GXSL using the bit values of k upper bit data that are a part of the upper data bits MBT1, MBT2 and MBT3.

In this embodiment, k is 2, and the logic group 200 uses the first higher data bit MBT1 and the second higher data bit MBT2 to select the first through fifth selection control signals XSL1- XSL5).

The first upper data bit MBT1 is the lowest order data bit among the upper data bits MBT1, MBT2 and MBT3 and the second upper data bit MBT2 is the data bit of the first upper data bit MBT1 ) The next lower order data bits.

The logic group 200 specifically includes a first NOR gate 210, an exclusive OR gate 230, and a second NOR gate 250.

The first NOR gate 210 inverts the bit value of the first upper data bit MBT1 and the bit value of the second upper data bit MBT2 to generate the first selection signal XSL1 Occurs.

The exclusive OR gate 230 exclusively ORs the bit value of the first upper data bit MBT1 and the bit value of the second upper data bit MBT2 to generate the third selection signal XSL3, Lt; / RTI &gt;

The second NOR gate 250 inverts the inverted bit value of the first upper data bit MBT1 and the inverted bit value of the second upper data bit MBT2 to generate the fifth selection signal XSL5 ).

The second selection signal XSL2 is an inverted bit value of the second upper data bit MBT2 and the fourth selection signal XSL4 is a bit value of the second upper data bit MBT2.

3, the node selection group 300 selects one of the plurality of selection voltage generating groups 100 <1> and 100 <2> using the bit value of the third upper data bit MBT3. It specifies either one.

That is, the first selection voltage VSL1 <1> of the first selection nodes NSL1 <1> and NSL1 <2> in the selected voltage generation groups 100 < VSL1 &lt; 2 &gt;) are provided as the first preliminary voltage VPRE1 of the first preliminary stage NPRE1. The second selection voltage VSL2 <1> of the second selection nodes NSL2 <1> and NSL2 <2> in the specified selection voltage generation groups 100 <1> and 100 <2> VSL2 &lt; 2 &gt;) are provided as the second preliminary voltage VPRE2 of the second preliminary stage NPRE2.

As a result, in this embodiment, the terminal to which each of the divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1>, VDV4 <1> and VDV5 < (NPRE1) and the second preliminary stage (NPRE2).

That is, if the divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1>, VDV4 <1> and VDV5 <1> are ultimately the first coarse voltage VCSA1 or the second coarse voltage (VCSA2), the first and second preliminary stages (PRE1 and NPRE2) are transmitted through one path.

As a result, the number of switches for selection and transmission of the divided voltages VDV1 <1>, VDV2 <1>, VDV3 <1>, VDV4 <1>, VDV5 <1>

Preferably, the node selection group 300 includes first to fourth group selection switches 310 to 340.

The first group selection switch 310 is responsive to the inverted bit value of the third upper data bit MBT3 to select the first selection node NSL1 <1> of the selection voltage generation group 100 <1> And provides the first selection voltage VSL1 <1> to the first preliminary voltage VPRE1 of the first preliminary stage NPRE1. In response to the inverted bit value of the third upper data bit MBT3, the second group selection switch 320 selects the second selection node NSL2 <1> of the selection voltage generation group 100 <1> The second selection voltage VSL2 < 1 > of the second preliminary stage NPRE2 is supplied as the second preliminary voltage VPRE2 of the second preliminary stage NPRE2.

The third group selection switch 330 is responsive to the bit value of the third upper data bit MBT3 to select the first selection node NSL1 <2> of the selection voltage generation group 100 <2> And provides the first selection voltage VSL1 <2> to the first preliminary voltage VPRE1 of the first preliminary stage NPRE1. The fourth group selection switch 340 is responsive to the bit value of the third upper data bit MBT3 to select the second selection stage NSL2 <2> of the selection voltage generation group 100 <2> The second selection voltage VSL2 <2> of the second preliminary stage NPRE2 is supplied as the second preliminary voltage VPRE2 of the second preliminary stage NPRE2.

3, the polarity switching group 400 applies a low level voltage of the first preliminary voltage VPRE1 and the second preliminary voltage VPRE2 to the first output terminal NUT1, Voltage VCAS1. The polarity switching group 400 may be configured to apply a high level voltage of the first preliminary voltage VPRE1 and the second preliminary voltage VPRE2 to the second output node NUT2 as the second rough voltage VCAS2 to provide.

Preferably, the polarity switching group 400 is controlled by the first upper data bit MBT1, and more preferably includes first through fourth polarity-connecting switches 410-440.

The first polarity-connecting switch 410 outputs the first preliminary voltage VPRE1 to the first output terminal NUT1 in response to the inverted bit value of the first upper data bit MBT1, VCAS1).

The second polarity-connecting switch 420 outputs the second preliminary voltage VPRE2 to the second output terminal NUT2 in response to the inverted bit value of the first upper data bit MBT1, VCAS2).

The third polarity-connecting switch 430 outputs the first preliminary voltage VPRE1 to the second output terminal NUT2 in response to the bit value of the first upper data bit MBT1, ).

The fourth polarity connection switch 440 outputs the second preliminary voltage VPRE2 to the first output terminal NUT1 in response to the bit value of the first upper data bit MBT1, ).

Referring again to FIG. 2, the fine DAC block FNDAC interpolates the first coarse voltage VCAS1 and the second coarse voltage VCAS2 according to the bit values of the lower data bits LBT1 and LBT2 And outputs the generated analog voltage VANG.

The fine DAC block (FNDAC) may be implemented in various manners, for example, a resistance heating method (using 2 ^N resistance columns), a capacitor method, and an embedded amplifier method. Further, since such a fine DAC block (FNDAC) can be easily implemented by those skilled in the art, a detailed description thereof will be omitted for simplicity of description in this specification.

Subsequently, in the rough DAC block (CADAC) of FIG. 3, the two divided voltages adjacent to each other by the upper data bits MBT1, MBT2 and MBT3 are divided into the first rough voltage VCAS1 and the second rough voltage VCAS2 Output.

For example, assume that the bit values of the upper data bits MBT1, MBT2, and MBT3 are (Table 1).

beat MBT1 MBT2 MBT3 Bit value One 0 One

The logic states of the first to fifth selection signals XSL1 to XSL5 are as shown in Table 2 below.

Selection signal XSL1 XSL2 XSL3 XSL4 XSL5 Logical state L H H L L

Accordingly, the switches indicated by dotted circles in FIG. 4 are turned on. As a result, the divided voltage VDV2 < 2 >, which is a low level among the two divided voltages adjacent to each other, is output to the first rough voltage VCAS1 and the divided voltage VDV3 < VCAS2.

In summary, in the rough DAC block (CADAC) of the divided DAC of the present invention, the two divided voltages neighboring by the selected voltage generating groups are transmitted to the first and second preliminary stages. At this time, the preliminary stage in which each divided voltage is transmitted is already fixed regardless of the relative size. That is, one divided voltage is transmitted to the fixed selected stage through one path.

Then, the low-level divided voltage of the two divided voltages by the polarity switching group is provided to the first coarse voltage of the first output terminal, and the high-level divided voltage is provided to the second coarse voltage of the second output terminal.

In the divided DAC according to the present invention, as one divided voltage is transmitted to the fixed spare stage via one path, a path provided with the first coarse voltage and the second coarse voltage with respect to one divided voltage The number of switches for transmitting the divided voltage is significantly reduced as compared with the prior art that exists separately.

Therefore, with the divided DAC of the present invention, the overall layout area is remarkably reduced.

As described above, in the divided DAC according to the present invention, the effect of reducing the number of switches for transmitting the divided voltage, that is, the effect of reducing the layout area is more remarkable as the number of upper data bits is larger.

(Table 3) compares the number of switches for transmitting divided voltages in the present invention shown in FIG. 3 and the number of switches for transmitting divided voltages in the related art shown in FIG.

Number of upper data bits  M = 2 M = 3 M = 4 M = 5 The number of switches for transmitting the divided voltages in the prior art (FIG. 1) 12 28 60 124 The number of switches for transmitting the divided voltages in the present invention (FIG. 3) 9 18 36 72

As can be seen from Table 3, in the divided DAC of the present invention, the effect of reducing the number of switches for transmitting the divided voltage, that is, the effect of reducing the layout area is more remarkable as the number of upper data bits is larger.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is to be understood that the invention is not limited to the disclosed embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

Claims (6)

In a segmented DAC that converts digital data composed of M (where M is a natural number of 3 or more) upper data bits and N (where N is a natural number) lower data bits into an analog voltage and outputs the analog voltage ,
A coarse DAC for dividing the reference high voltage for the reference low voltage according to the bit value of the M upper data bits to output a first coarse voltage to the first output terminal and a second coarse voltage to the second output terminal, Block; And
And a fine DAC block outputting the analog voltage generated by interpolating the first coarse voltage and the second coarse voltage according to a bit value of the N lower data bits, where N is a natural number,
The coarse DAC block
A plurality of select voltage generating groups formed between each of the node low voltages and the respective node high voltages included between the reference low voltage and the reference high voltage and each of the first select voltage and the second select voltage selected by the select signal group, A plurality of selection voltage generating groups for generating a selection voltage in each of a first selection stage and a second selection stage;
A logic group for generating the selection signal group using a bit value of k upper data bits, k being a natural number smaller than M, where k is a number greater than 2 and a part of the upper data bits;
(Mk) upper data bits, which are the remaining part of the upper data bits, as a node selection group that specifies any one of the plurality of selection voltage generation groups, The node selection group providing the first selection voltage of a selected node to a first preliminary voltage of a first preliminary stage and the second selection voltage of the second selected node to a second preliminary voltage of a second preliminary stage; And
A first preliminary voltage and a second preliminary voltage are supplied to the first output terminal at the first coarse voltage and a high level voltage of the first preliminary voltage and the second preliminary voltage is supplied to the first output terminal, And a polarity switching group driven to provide the second coarse voltage to the second output terminal.
The method of claim 1, wherein each of the plurality of selection voltage generating groups
A series of resistors connected in series to each other in series order to generate (i + 1) divided voltages having a series order from the node undervoltage to the node high voltage, wherein i is a natural number of 4 or more The resistance column; And
Voltage dividing transfer section for selecting two consecutive divided voltages among the (i + 1) divided voltages and providing the selected one to the first selection stage and the second selection stage, wherein the first selection stage comprises: Wherein the second selection stage receives the odd-numbered divided voltage among the divided voltages at the first selection voltage, and the second selection stage receives the even-numbered divided voltage among the plurality of divided voltages at the second selected voltage And a plurality of divided DACs.
3. The apparatus of claim 2, wherein the selection signal group
The first to fifth selection signals,
The partial pressure-
A first selection switch responsive to the first selection signal for transmitting the first divided voltage to the first selection terminal;
A second selection switch responsive to the second selection signal for transmitting the second divided voltage to the second selection terminal;
A third selection switch responsive to the third selection signal for transmitting the third divided voltage to the first selection stage;
A fourth selection switch responsive to the fourth selection signal for transmitting the fourth divided voltage to the second selection stage; And
And a fifth selection switch responsive to the fifth selection signal for transmitting the fifth divided voltage to the first selection stage.
4. The apparatus of claim 3,
A first NOR gate for generating a first selection signal by inverting the bit value of the first upper data bit and the bit value of the second upper data bit;
An exclusive OR gate for exclusive-ORing a bit value of the first upper data bit and a bit value of the second upper data bit to generate the third selection signal; And
And a second NOR gate for generating the fifth selection signal by inverting and inverting the inverted bit value of the first upper data bit and the inverted bit value of the second upper data bit,
The second selection signal
An inverted bit value of the second upper data bit,
The fourth selection signal
And the second upper data bit is a bit value of the second upper data bit.
5. The method of claim 4, wherein the polarity switching group
And the second data bit is controlled by the first upper data bit.
The method of claim 5, wherein the polarity switching group
A first polarity-connecting switch responsive to an inverted bit value of the first upper data bit to provide the first preliminary voltage to the first output terminal at the first coarse voltage;
A second polarity-connecting switch responsive to the inverted bit value of the first higher data bit to provide the second preliminary voltage to the second output terminal at the second coarse voltage;
A third polarity-coupling switch responsive to a bit value of the first upper data bit to provide the first preliminary voltage to the second output terminal at the second coarse voltage; And
And a fourth polarity-coupling switch for providing the second preliminary voltage to the first output terminal at the first coarse voltage in response to the bit value of the first upper data bit.

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