KR100959366B1 - CIO structure liquid crystal display substrate and manufacturing method thereof - Google Patents

Abstract

According to the COT liquid crystal display including the top gate type thin film transistor according to the present invention and a method of manufacturing the same, by minimizing the bonding margin by the COT structure can increase the aperture ratio, and using a polysilicon thin film transistor to separate the upper substrate The black matrix pattern can be omitted, and since the black matrix is formed as a protective layer, a high opening ratio structure can be easily applied through the process simplification, thereby increasing the production yield.

Description

Substrate for Liquid Crystal Display Device Having Color Filter on Thin Film Transistor (COT) Structure and Method for Fabricating the Same}             

1 is a view schematically showing a general liquid crystal display device.

2 is a cross-sectional view taken along the line II-II of FIG.

3 is a cross-sectional view of an array substrate for a liquid crystal display device including a conventional top gate type thin film transistor.

4 is an enlarged plan view showing an array substrate including a top gate type thin film transistor of the present invention and having a color filter on thin film transistor (COT) structure.

5 is a cross-sectional view taken along the line V-V of FIG. 4.

Figure 6 is a process flow diagram showing a manufacturing process step by step for the array substrate for a liquid crystal display device having a COT structure according to the present invention.

7A to 7I are cross-sectional views illustrating a manufacturing process of an array substrate for a liquid crystal display device having a top gate type thin film transistor and a COT structure according to the present invention.

<Brief description of the main parts of the drawing>                 

110 substrate 112 buffer layer

114: semiconductor layer 116: first capacitor electrode

118 gate insulating film 120 gate electrode

124: interlayer insulating film

126a, 126b, 126c: 1st, 2nd, 3rd contact hole

128: source electrode 130: drain electrode

132: second capacitor electrode 134: data wiring

136: black matrix 138: the first transparent conductive layer

140: color filter layer 142: second transparent conductive layer

144 pixel electrodes

C _ST : Storage capacitance P: Pixel area

T: thin film transistor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a liquid crystal display (COT) structure liquid crystal display device having a structure of simultaneously forming a color filter layer on a substrate on which a thin film transistor is formed, and a manufacturing method thereof.                         

In general, flat panel display devices are widely used in portable display devices because of their thin, light, and low power consumption. Among the flat panel display devices, the liquid display device is capable of high resolution and color display, and is widely used as a display device for notebook computers and general desktop computers.

A liquid crystal display device displays an image by using optical anisotropy and birefringence characteristics of liquid crystal molecules. When an electric field is applied, the arrangement of liquid crystals is changed, and the light transmission characteristics are also changed according to the arrangement direction of the liquid crystals.

In general, a liquid crystal display device is formed by arranging two substrates on which electric field generating electrodes are formed so that the surfaces on which the two electrodes are formed face each other, injecting a liquid crystal material between the two substrates, and then applying a voltage to the two electrodes. By moving the liquid crystal molecules by the electric field is a device that represents the image by the transmittance of light that varies accordingly.

The liquid crystal display device is applied to office equipment and many video devices. In particular, an active matrix type liquid crystal display device in which pixel electrodes and thin film transistors are arranged in a matrix form is most widely used. In particular, the active matrix type liquid crystal display device has high resolution and is excellent in color moving image implementation.

1 is a view schematically showing a general active matrix liquid crystal display device.

As shown in the drawing, a general color liquid crystal display device 11 includes a black matrix formed between a sub color filter 8 of red (R) / green (G) / blue (B) color and each sub color filter (8). An upper substrate 5 on which a color filter layer including 6) and a common electrode 18 deposited on the red, green, blue, and blue color filters 8 are formed; The region P is defined, the pixel electrode 17 and the switching element T are formed in the pixel region, and the lower substrate 22, the upper substrate 5 and the array wiring are formed around the pixel region P. The liquid crystal 14 is filled between the lower substrates 22.

The lower substrate 22 is also referred to as an array substrate, and the thin film transistor T, which is a switching element, is positioned in a matrix type, and the gate wiring 13 crosses the plurality of thin film transistors TFT. ) And data wirings 15 are formed.

In this case, the pixel area P is an area defined by the gate wiring 13 and the data wiring 15 intersecting. A transparent pixel electrode 17 is formed on the pixel area P as described above.

The pixel electrode 17 uses a transparent conductive metal having relatively high light transmittance such as indium-tin-oxide (ITO).

A storage capacitor C _ST connected in parallel with the pixel electrode 17 is formed on the gate line 13, and a portion of the gate line 13 is used as the first electrode of the storage capacitor C _ST . As the second electrode, an island-shaped capacitor metal layer 30 formed of the same material as the source and drain electrodes is used.

In this case, the capacitor metal layer 30 is configured to be in contact with the pixel electrode 17 to receive a signal of the pixel electrode.

As described above, when the upper color filter substrate 5 and the lower array substrate 22 are bonded to each other to produce a liquid crystal panel, the adhesion error between the color filter substrate 5 and the array substrate 22 is reduced. It is very likely that light leakage will occur.

A description with reference to FIG. 2 is as follows.

FIG. 2 is a cross-sectional view taken along line II-II of FIG. 1.

As described above, the first substrate 22, which is an array substrate, and the second substrate 5, which is a color filter substrate, are spaced apart from each other, and the liquid crystal layer 14 is disposed between the first and second substrates 22, 5. This is located.

The thin film transistor T including the gate electrode 32, the active layer 34, the source electrode 36, and the drain electrode 38 is disposed on the array substrate 22, and the thin film transistor T is disposed on the thin film transistor T. A protective film 40 is configured to protect it.

In the pixel region P, a transparent pixel electrode 17 is formed in contact with the drain electrode 38 of the thin film transistor T, and a storage capacitor C _ST connected in parallel with the pixel electrode 17 includes a gate wiring ( 13) is configured on the top.

The upper substrate 5 includes a black matrix 6 corresponding to the gate wiring 13, the data wiring 15, and the thin film transistor T, and corresponds to the pixel region P of the lower substrate 22. The color filter 8 is comprised.                         

In this case, the general array substrate is configured such that the data line 15 and the pixel electrode 17 are spaced apart by a predetermined distance A to prevent vertical cross talk, and the gate line 13 and the pixel electrode are spaced apart from each other. In addition, a predetermined interval (B) is configured to be spaced apart.

Since the spaces A and B spaced apart between the data line 15 and the gate line 13 and the pixel electrode 17 are areas where light leakage occurs, a black matrix formed on the upper color filter substrate 5 matrix) (6) will cover this part.

In addition, the black matrix 6 formed on the thin film transistor T serves to block the light so that the light radiated from the outside does not affect the active layer 34 through the passivation layer 40. .

However, a misalignment may occur during the process of bonding the upper substrate 5 and the lower substrate 22. In view of this, a margin of a constant value is determined when designing the black matrix 6. Since the design is carried out with reference to), the aperture ratio decreases by that amount.

In addition, in the case where the bonding error beyond the margin occurs, there is often a light leakage defect in which the light leakage regions A and B are not covered by the black matrix 6.

In this case, since the light leakage appears outside, there is a problem that the image quality is deteriorated.

In order to solve the above problems, an object of the present invention is to provide a liquid crystal display device having a structure that can increase the transmittance by minimizing the bonding margin. To this end, the present invention is to provide a COT liquid crystal display device of a method of forming a color filter element on a substrate on which a thin film transistor is formed.

Another object of the present invention is to provide a COT liquid crystal display device having a process simplification structure. To this end, in the present invention, the gate electrode is formed on a semiconductor layer made of polysilicon (p-Si), and the exposed both sides of the semiconductor layer are impurity treated using the gate electrode as a mask, and the impurity treatment of the semiconductor layer is performed. And a top gate type thin film transistor structure array element formed by a fabrication process of forming a source electrode and a drain electrode in contact with a region. In particular, instead of separately forming a protective layer for the top gate type thin film transistor, a process of forming a black matrix of a color filter element as a protective layer for both light blocking patterns is simplified.

3 is a cross-sectional view of an array substrate for a liquid crystal display device including a conventional top gate type thin film transistor.

As illustrated, a buffer layer 52 is formed on the substrate 50, and the semiconductor layer 54 and the first capacitor electrode 56 are positioned apart from each other on the buffer layer 52, and the semiconductor layer 54 is disposed therebetween. ) Is composed of an active region C, a source region D and a drain region E positioned at the periphery of the active region C, and the first capacitor electrode 56 is formed of the same material as the semiconductor layer. .

The material constituting the semiconductor layer 54 and the first capacitor electrode 56 is selected from a polysilicon material, and the source region D, the drain region E, and the first capacitor electrode correspond to an impurity treated region.

A gate insulating layer 58 is formed in a region covering the semiconductor layer 54 and the first capacitor electrode 56, and the gate electrode 60 is positioned at a position covering the active region C on the gate insulating layer 58. The second capacitor electrode 62 is formed at a portion corresponding to the first capacitor electrode 56 on the gate insulating layer 58.

An interlayer insulating layer 64 is formed to cover the gate electrode 60 and the second capacitor electrode 62, and the source region D of the semiconductor layer 54 is formed in the interlayer insulating layer 64 and the gate insulating layer 58. And contact holes exposing any one region of the drain region E and the first capacitor electrode 56, respectively.

For convenience of description, exposing the first contact hole 66a and the drain region E to the contact hole exposing the source region D of the semiconductor layer 54 may include the second contact hole 66b and the first capacitor. Exposing the electrode 56 is referred to as a third contact hole 66c.

The source electrode 68 and the second contact connected to the source region D through the first contact hole 66a on the interlayer insulating layer 64 including the first to third contact holes 66a, 66b, and 66c. A drain electrode 70 connected to the drain region E is formed through the hole 66b, and the auxiliary capacitor electrode 72 connected to the first capacitor electrode 56 through the third contact hole 66c is formed. Formed.

The data line 69 is formed in connection with the source electrode 68.

The drain contact hole 74 is formed at a position covering the source electrode 68, the drain electrode 70, and the auxiliary capacitor electrode 72, and exposes the drain electrode 70 and the auxiliary capacitor electrode 72. And a protective layer 78 having a capacitor contact hole 76. The drain electrode 70 and the auxiliary capacitor electrode are formed on the protective layer 78 through the drain contact hole 74 and the capacitor contact hole 76. A pixel electrode 80 connected to the 72 is formed.

The semiconductor layer 54, the gate electrode 60, the source electrode 68, and the drain electrode 70 form a thin film transistor T and become conductive as a voltage is applied through the auxiliary capacitor electrode 72. The region where the first capacitor electrode 56 and the second capacitor electrode 62 overlap each other forms a storage capacitor C _ST with the gate insulating layer 58 interposed therebetween.

In the present invention, to form a liquid crystal display array substrate including a conventional top-gate thin film transistor in a COT structure to simplify the process.

In more detail, the top gate type thin film transistor structure is applied to the COT liquid crystal display device, and the black matrix is used instead of the organic insulating layer used for the purpose of improving the aperture ratio and the protective layer, thereby minimizing the bonding margin of the COT structure. It is possible to further have a process simplification effect on the increase of the aperture ratio.

In order to achieve the above object, in a first aspect of the present invention, there is provided a semiconductor device comprising: a top gate type thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode; A storage capacitor including a first capacitor electrode and a second capacitor electrode and formed adjacent to the top gate type thin film transistor; A black matrix formed on the top gate thin film transistor; A first transparent pixel electrode in contact with the drain electrode and formed in the pixel region; A color filter formed on the first transparent pixel electrode in the pixel region; And a second transparent pixel electrode formed on the color filter in contact with the first transparent pixel electrode, wherein the active layer and the first capacitor electrode are integrally formed on the same layer of the same material, and the first transparent pixel electrode And a second transparent pixel electrode whose end is coincident with the end thereof, and is formed on the black matrix, and the first transparent pixel electrode is formed to overlap the second capacitor. A substrate for a liquid crystal display device is provided.

A buffer layer between the top gate thin film transistor and the substrate, a gate insulating layer between the active layer and the gate electrode, and between the first capacitor electrode and the second capacitor electrode; A substrate for a COT structure liquid crystal display device including an interlayer insulating film covering the gate electrode and the second capacitor electrode. First and second contact holes are formed in the gate insulating layer and the interlayer insulating layer to expose an active layer, the source electrode contacts the active layer through the first contact hole, and the drain electrode contacts the second contact hole. It is characterized in that the substrate for the COT structure liquid crystal display device in contact with the active layer through.

A protective layer covering the drain electrode and the black matrix and having a third contact hole exposing the drain electrode, wherein the protective layer is in contact with the drain electrode of the top gate type thin film transistor through the third contact hole. It is a substrate for a liquid crystal display device having a COT structure formed under the transparent pixel electrode.

The black matrix is made of one of a light blocking insulating material and a black resin, and the active layer is divided into a first region corresponding to the gate electrode and a second region on both sides of the first region. Is composed of polysilicon doped with impurities and is a substrate for a liquid crystal display device having a COT structure having an "L" shape.

The second capacitor electrode is a substrate for a COT structure liquid crystal display device configured to be parallel to the gate wiring.

Another aspect of the present invention includes the steps of forming a top gate type thin film transistor including an active layer, a gate electrode, a source electrode and a drain electrode on the substrate; Forming a storage capacitor comprising a first capacitor electrode and a second capacitor electrode and adjacent to the top gate type thin film transistor; Forming a black matrix on the top gate thin film transistor; Forming a first transparent pixel electrode in the pixel region in contact with the drain electrode; Forming a color filter on the first transparent pixel electrode in the pixel region; Forming a second transparent pixel electrode in contact with the first transparent pixel electrode on the color filter, wherein the active layer and the first capacitor electrode are integrally formed on the same layer with the same material, The first transparent pixel electrode and the second transparent pixel electrode are patterned at the same time, and the ends thereof are formed to coincide with the black matrix, and the first transparent pixel electrode is formed to overlap with the second capacitor. Color filter on thin film transistor) structure provides a substrate manufacturing method for a liquid crystal display device.

In the present invention, forming a buffer layer between the top-gate thin film transistor and the substrate, forming a gate insulating film between the active layer and the gate electrode and between the first capacitor electrode and the second capacitor electrode; And forming an interlayer insulating film formed on the gate insulating film and covering the gate electrode and the second capacitor electrode. The method may further include forming first and second contact holes exposing an active layer on the gate insulating layer and the interlayer insulating layer, wherein the source electrode contacts the active layer through the first contact hole, and the drain electrode. Is a method of manufacturing a substrate for a COT structure liquid crystal display device formed to be in contact with the active layer through the second contact hole.

In the method for manufacturing a substrate for a COT structure liquid crystal display of the present invention, a protective layer covering the drain electrode and the black matrix and having a third contact hole exposing the drain electrode is formed below the first transparent pixel electrode. And the first transparent pixel electrode contacts the drain electrode of the top gate thin film transistor through a third contact hole.

In the method of manufacturing a substrate for a COT structure liquid crystal display device of the present invention, the black matrix is formed of one selected from a light blocking insulating material and a black resin.

In the method of manufacturing a substrate for a COT structure liquid crystal display device of the present invention, the active layer is formed of polysilicon so as to have an "L" shape, and includes a first region corresponding to the gate electrode and first and second sides of the first region. It is divided into two regions, characterized in that it comprises the step of doping (doping) with impurities in the second region.

In the method of manufacturing a substrate for a liquid crystal display device of the COT structure of the present invention, the second capacitor electrode is configured to be parallel to the gate wiring.

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BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly, to a COT structure liquid crystal display device and a method of manufacturing the same, which together form a color filter on an array substrate.

In addition, the present invention is characterized in that the color filter is formed on the array substrate having a top gate type thin film transistor, wherein the black matrix is used as a protective layer for the thin film transistor, so that the black matrix is light on the non-pixel region. In addition to the light blocking role of blocking the function of the organic insulating film used for the aperture ratio improving structure, the aperture ratio improving structure can be provided.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the drawings.

4 is an enlarged plan view of an array substrate including a top gate type thin film transistor of the present invention and having a color filter on thin film transistor (COT) structure.

As shown in the drawing, the data forming the gate lines 122 extending in one direction on the substrate 100 in parallel with each other and crossing the gate lines 122 perpendicularly to each other to define a plurality of pixel regions P. As shown in FIG. The wiring 134 is constituted.

The thin film transistor T including the gate electrode 120, the active layer 114, and the source and drain electrodes 128 and 130 is formed at the point where the gate line 122 and the data line 134 cross each other. .

In the top gate type thin film transistor T according to the present invention, the source electrode 128 is a portion of the data line 134 at the intersection of the data line 134 and the gate line 122. . In particular, the active layer 114 according to the present invention has a shape in which the letter “L” is rotated 180 degrees in the horizontal direction (hereinafter, referred to as an “L” shape for convenience of description), and thus the gate line 122 direction (the horizontal direction). ) And a portion formed by bending in the direction of the data line 134 (the longitudinal direction) are orthogonal to each other. The first capacitor electrode 116 extends at an end of the “L” shaped active layer 114. The gate electrode 120 is branched from the gate wiring so as to overlap a transverse portion of the “L” shaped active layer 114, and the drain electrode 130 is the “L” shaped first capacitor. It is located above the longitudinal portion of the electrode 116. In addition, one end of the transverse portion of the activa portion 114 having an “L” shape extends to overlap the source electrode 128. The "L" shaped active layer 114 of the top gate type thin film transistor T according to the present invention is formed of polysilicon (p-Si).

The color filter 130 is formed in the pixel region P defined by the intersection of the two wires 122 and 134, and the first transparent pixel electrode 138 and the second transparent pixel electrode 142 are formed. The first and second pixel electrodes 138 and 142 have the same planar shape and form a double layer pixel electrode 144 in contact with the drain electrode 130. The double layer pixel electrode 144 is called a sandwich pixel electrode.

The transparent electrodes 138 and 142 are made of the same material, and the first transparent pixel electrode 138 is formed under the color filter 140 while being in contact with the drain electrode 130, and the second transparent pixel electrode ( 142 is configured above the color filter 140. That is, the color filter 140 is positioned between the first transparent pixel electrode 138 and the second transparent pixel electrode 142, and the second transparent pixel electrode 142 is drained through the first transparent pixel electrode 138. Indirect contact with the electrode 130.

In addition, the first and second transparent pixel electrodes 138 and 142 are connected in parallel with the storage capacitor C _ST formed on the gate line 122.

The storage capacitor C _ST includes the first capacitor electrode 116 connected to the active layer 114 as the first electrode, and the second capacitor electrode 132 formed in the transverse direction as the second electrode. . As described above, the first capacitor electrode 116 is connected to one end of the “L” shaped active layer 114 and is made of polysilicon (p-Si), which is the same material as the active layer 114. have. The second capacitor electrode 132 is formed of the same material as the source and drain electrodes 128 and 130.

The first and second transparent electrodes (first and second pixel electrodes) 138 and 142 are connected to the drain electrode 130, and the drain electrode 130 is connected to the active layer 114. Since the layer 114 is connected to the first capacitor electrode 132, the storage capacitor C _ST is connected in parallel with the pixel electrode 144 of the bilayer.

As illustrated, the COT structure includes a black matrix 136 and a red, green, and blue color filter 140 formed on the thin film transistor (T) array unit.

The black matrix 136 covers the light leakage region and is configured to correspond to the gate wiring 122, the data wiring 134, and the thin film transistor T.

The black matrix 136 is formed by applying an opaque organic material, and serves to block light and serve as a protective film to protect the thin film transistor.

In the above-described configuration, when the second transparent electrode (second pixel electrode) 142 is formed on the color filter 140, since a separate photo process is not used, the lower color filter pattern is damaged. Can be prevented.

5 is a cross-sectional view of an array substrate having a COT structure and a top gate type thin film transistor according to the present invention, cut along V-V of FIG. 4.

As illustrated, a buffer layer 112 is formed on the substrate 110, and the semiconductor layer 114 and the first capacitor electrode 116 are connected to each other on the buffer layer 112. The semiconductor layer 114 includes an active region, a source region and a drain region positioned around the active region, and the first capacitor electrode 116 is substantially connected to the drain region. The material constituting the semiconductor layer 114 is selected from a polysilicon material, and the source region and the drain region of the semiconductor layer 114 and the first capacitor electrode 116 correspond to an impurity treated region. Although not shown in the drawing, since the region between the first capacitor electrode 116 and the semiconductor layer 114 is not impurity treatment, the first capacitor electrode 116 and the semiconductor layer 114 are formed to be electrically separated. .

A gate insulating layer 118 is formed in a region covering the semiconductor layer 114 and the first capacitor electrode 116, and a gate electrode 120 is formed at a position covering an active region above the gate insulating layer 118. . In addition, a second capacitor electrode 132 is formed in a region corresponding to the first capacitor electrode 116 on the gate insulating layer 118.

Although not shown in FIG. 5, as shown in FIG. 4, the gate wiring 120 122 is formed by being connected to the gate electrode 120.

An interlayer insulating layer 124 is formed at a position covering the gate electrode 120 and the second capacitor electrode 132, and a source region and a drain of the semiconductor layer 114 are formed in the interlayer insulating layer 124 and the gate insulating layer 118. Contact holes 126a and 126b exposing regions are formed, respectively.

For convenience of description, the contact hole exposing the source region of the semiconductor layer 114 is referred to as the second contact hole 126b to expose the first contact hole 126a and the drain region.

A source electrode 128 and a first electrode connected to the source region of the active layer 114 through the first contact hole 126a on the interlayer insulating layer 124 including the first and second contact holes 126a and 126b. A drain electrode 130 connected to the drain region of the active layer 114 is formed through the two contact holes 126b.

The data line 134 is connected to the source electrode 128, and although not illustrated, the data line 134 is formed to cross the gate line to define a pixel area. The source electrode 128 extends from the data line 134, and the drain electrode 130 is formed to be spaced apart from each other with the gate electrode 120 interposed therebetween.

The semiconductor layer 114, the gate electrode 120, the source electrode 128, and the drain electrode 130 form a top gate type thin film transistor T, and a data line on the top gate thin film transistor T. The black matrix 136 is formed in the region covering the portion 134 and the gate electrode 120 and the source electrode 128. Therefore, although not shown in the drawings, the black matrix 136 is formed in an integrated pattern having an open part corresponding to the pixel area defined by the gate line and the data line at a position surrounding the pixel area boundary.

A protective layer 125 is formed on the entire surface of the substrate covering the black matrix 136, and a third contact hole 126c exposing a portion of the drain electrode 130 penetrates the protective layer 125. It is. The first transparent pixel electrode 138 is positioned in the pixel area above the passivation layer 125, and the first transparent pixel electrode 138 is exposed through the third contact hole 126c. Contact with Color filters 140a and 140c are formed on the first transparent pixel electrode 138, and each color filter 140 is positioned to correspond to an open portion of the black matrix 136. It is formed corresponding to the pixel region defined by the gate wiring (122 in FIG. 4) and the data wiring 134. As shown in FIG. Each color filter 140 has any one of red, green, and blue, and the red, green, and blue color filters 140 are alternately positioned in the pixel area.

Meanwhile, the first capacitor electrode 116 and the second capacitor electrode 122 and the gate insulating layer 118 inserted therebetween form a storage capacitor C _ST , and the first transparent pixel electrode 138 is active. It is connected to the storage capacitor C _ST through the drain electrode 130 in contact with the layer 114.

A second transparent pixel electrode 142 is disposed to cover the color filter 140 and contact the first transparent pixel electrode 138 exposed at the periphery of the color filter 140. Since the second transparent pixel electrode 142 is connected to the first transparent pixel electrode 138, the second transparent pixel electrode 142 is electrically connected to the drain electrode 130 of the top gate thin film transistor T. Connected to the storage capacitor (C _ST ).

The first and second transparent pixel electrodes 138 and 142 formed with the color filter 140 interposed therebetween constitute a double layer pixel electrode 144. The double layer pixel electrode 144 is a sandwich type pixel electrode. Also called a pixel electrode.

In the COT liquid crystal display device including the top gate thin film transistor according to the present invention, since the polysilicon thin film transistor is used, optical leakage due to light inflow is different from that of the amorphous silicon thin film transistor having an inverted stagger type structure. Since the deterioration caused by the current is relatively small, an additional black matrix process may be omitted in the thin film transistor unit.                     

In the present invention, the black matrix 136 is positioned in the region VII covering the data line 134 to minimize parasitic capacitance between the pixel electrode 144 and the data line 134. It was.

Hereinafter, a manufacturing process of an array substrate having a COT structure will be described with reference to FIGS. 6 and 7A-7B.

6 is a process flow chart showing a manufacturing process for a liquid crystal display array substrate having a COT structure step by step according to the present invention, Figures 7a to 7i is a liquid crystal display having a top-gate thin film transistor and a COT structure according to the present invention Sectional drawing showing the manufacturing process of the array substrate for apparatus.

As shown in ST1 of FIG. 6 and FIG. 7A, a buffer layer 112 is first formed on a substrate 110. The semiconductor layer 114 and the first capacitor electrode 116 are formed on the buffer layer 112 by using a polysilicon material.

The semiconductor layer is divided into an active region of a central portion, a source region and a drain region of both sides, and impurities are doped into the source and drain regions and the first capacitor electrode 116. The doping process is active It may proceed immediately after the layer 114 is formed, and may also proceed after the gate electrode is formed in a subsequent process. During the doping process, a mask is used to cover the areas of the active layer 114 and the first capacitor electrode 116 so that doping is not performed on the areas of the active layer 114 and the first capacitor electrode. This is to electrically separate (116).                     

As an example of forming the active layer 114 and the first capacitor electrode 116, the buffer layer 112 and the amorphous silicon material are successively deposited, and then, through dehydrogenation, laser crystallization and thermal crystallization are performed. The active layer 114 and the first capacitor electrode 116 may be formed by forming polysilicon and patterning polysilicon.

Since the polysilicon has a high mobility characteristic, it is possible to minimize the deterioration of the switching electrical characteristics caused by the light leakage current.

Next, as illustrated in ST2 and FIG. 7B of FIG. 6, a gate insulating layer 118 is formed in a region covering the semiconductor layer 114 and the first capacitor electrode 116. On the gate insulating layer 118, the gate electrode 120 is formed at a position covering the active region of the active layer 114, and the second capacitor electrode 132 is formed at a position covering the first capacitor electrode 116. do.

As mentioned above, in this step, the source region and the drain region of the exposed semiconductor layer 114 and the first capacitor electrode 116 are treated with p-type ions or n-type ions using the gate electrode 120 as a mask. It may include the step. In this case, an undoped boundary region is defined between the semiconductor layer 114 and the first capacitor electrode 116. As mentioned above, the undoped boundary region is for electrically separating the semiconductor layer 114 and the first capacitor electrode 116.

Next, as shown in FIG. 7C, an interlayer insulating layer 124 is formed on the entire surface of the substrate 110 to cover the gate electrode 120 and the second capacitor electrode 132. The gate insulating film 118 and the interlayer insulating film 124 are patterned together to form first and second contact holes 126a and 126b. The first contact hole 126a exposes the left region (source region) of the active layer 114, and the second contact hole 126b exposes the right region (drain region) of the active layer 114. In particular, the second contact hole 126b is positioned between the gate electrode 120 and the second capacitor electrode 132.

As illustrated in ST3 and FIG. 7D of FIG. 6, the source and drain regions of the semiconductor layer 114 are respectively contacted through first and second contact holes 126a and 126b on the interlayer insulating layer 124. The data line 134 connected to the source electrode 128, the drain electrode 130, and the source electrode 128 is formed. As shown in FIG. 4, the data line 134 is formed perpendicular to the gate line 122. In FIG. 7D, the source electrode 128 extending from the data line 134 contacts the active layer 114 through the first contact hole, and is spaced apart from the source electrode 128 with the gate electrode 120 interposed therebetween. The formed drain electrode 130 contacts the active layer 114 through the second contact hole.

In this step, before the source electrode 128 and the drain electrode 130 and the data wiring 134 are formed, the step of hydrogenating the exposed semiconductor layer 114 and the first capacitor electrode 116 is performed. May contain

The semiconductor layer 114, the gate electrode 120, the source electrode 128, and the drain electrode 130 form a top gate type thin film transistor. The gate wiring and the data wiring cross each other to define the pixel region.

In FIG. 6, FIG. 7 and FIG. 7E illustrate the steps of forming the black matrix 136. The black matrix 136 is formed in the region covering the thin film transistor except the pixel region boundary and the drain electrode 130 defined by the gate wiring 122 (refer to FIG. 4) and the data wiring 134. In this step, the black matrix 136 is formed in an integrated pattern having an open portion that exposes the pixel region. That is, the black matrix 136 is formed to cover the source electrode 128, the gate electrode 120, the data wiring 134, and the gate wiring 122. In particular, the black matrix 136 is preferably formed in an area completely covering the data line. The material constituting the black matrix 136 is selected from an insulating material, preferably black resin.

After the black matrix 136 is formed, the protective layer 125 is formed on the entire surface of the substrate. The protective layer 125 has a shape covering the black matrix 136 and the exposed drain electrode 130. In addition, as shown in FIG. 7E, the protective layer 125 is patterned to form a third contact hole 126c to expose a part of the drain electrode 130.

6 and 7F illustrate a step of forming a first transparent conductive layer. The first transparent conductive layer 138a is formed of a thin film on the entire surface of the substrate on which the protective layer 125 is formed. Therefore, the first transparent conductive layer 138a comes into contact with the drain electrode 130 through the third contact hole 126c.

Next, ST6 and 7g of FIG. 6 are a process of forming the color filter 140.

The color filters 140a and 140b have red, green, and blue colors, respectively, and are formed in the upper pixel region of the first transparent conductive layer 138a. That is, it is positioned to correspond to the open part of the black matrix 136. Therefore, the color filter has a shape separated by each pixel region by the black matrix 136. The color filter 140 is not formed on the black matrix 136, and the red, green, and blue color filters 140 are alternately positioned on the pixels.

Next, as shown in ST7 and FIG. 7H of FIG. 6, the second transparent conductive layer 142a is formed on the color filter layer 140 and the entire surface of the exposed first transparent conductive layer 138a. In the present invention, the first and second transparent conductive layers 138a and 142a are formed of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO).

Next, as shown in FIG. 7I, the first and second transparent conductive layers 138a and 142a are simultaneously patterned to form a double layer pixel electrode 144. The pixel electrode 144 of the double layer includes a first transparent pixel electrode 138 and a second transparent pixel electrode 142. The color filter 140 is inserted between the two pixel electrodes 138 and 142 to sandwich the pixel. Also called a sandwich pixel electrode.

In the step illustrated in FIG. 7I, the pixel electrode 144 of the double layer may be formed to be spaced apart from a neighboring data line 134 by a predetermined distance, and positioned between the data line 134 and the pixel electrode 144. The black matrix 136 described above may minimize the parasitic capacitance between the two conductive materials.

In addition, in FIG. 7I, the first and second transparent pixel electrodes are simultaneously formed by the same pattern process, but the first transparent pixel electrode 138 is formed first, the color filter 140 is formed, and then the second transparent pixel is formed. The electrode 142 may be formed later.

Since the second transparent pixel electrode 142 is in contact with the first transparent pixel electrode 138 exposed around the color filter 140, the second transparent pixel electrode 142 is electrically connected to the thin film transistor.

In the array substrate of the COT structure according to the present invention, the process can be simplified by using a black matrix as a protective layer for a high-aperture structure, unlike the existing high-aperture structure.

However, the present invention is not limited to the above embodiments and can be practiced in various ways without departing from the spirit of the present invention.

 As described above, according to the COT liquid crystal display device including the top gate type thin film transistor according to the present invention and a method of manufacturing the same, the COT structure minimizes the bonding margin to increase the aperture ratio, and by using the polysilicon thin film transistor, The separate black matrix pattern can be omitted, and since the black matrix is formed as a protective layer, a high opening ratio structure can be easily applied through the process simplification, thereby increasing the production yield.

Claims (16)

A top gate thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode, and formed on a substrate; A storage capacitor including a first capacitor electrode and a second capacitor electrode and formed adjacent to the top gate type thin film transistor; A black matrix formed on the top gate thin film transistor; A first transparent pixel electrode in contact with the drain electrode and formed in the pixel region; A color filter formed on the first transparent pixel electrode in the pixel region; A second transparent pixel electrode formed on the color filter in contact with the first transparent pixel electrode Wherein the active layer and the first capacitor electrode are integrally formed on the same layer with the same material, and the first transparent pixel electrode and the second transparent pixel electrode are positioned on the black matrix so that their ends coincide with each other. And a color filter on thin film transistor (COT) structure, wherein the first transparent pixel electrode is formed to overlap the second capacitor. The method of claim 1, A buffer layer between the top gate thin film transistor and the substrate, a gate insulating layer between the active layer and the gate electrode, and between the first capacitor electrode and the second capacitor electrode; A substrate for a COT structure liquid crystal display device including an interlayer insulating film covering the gate electrode and the second capacitor electrode. The method of claim 2, First and second contact holes are formed in the gate insulating layer and the interlayer insulating layer to expose an active layer, the source electrode contacts the active layer through the first contact hole, and the drain electrode contacts the second contact hole. A substrate for a liquid crystal display device having a COT structure in contact with the active layer. The method of claim 1, A protective layer covering the drain electrode and the black matrix and having a third contact hole exposing the drain electrode, wherein the protective layer is in contact with the drain electrode of the top gate type thin film transistor through the third contact hole. 1 A substrate for a liquid crystal display device having a COT structure formed under the transparent pixel electrode. The method of claim 1, The black matrix is a substrate for a COT structure liquid crystal display device consisting of a light blocking insulating material and a black resin. The method of claim 1, The active layer is divided into a first region corresponding to the gate electrode and a second region on both sides of the first region, and the second region is formed of polysilicon doped with impurities, and has an "L" shape. COT structure liquid crystal display substrate consisting of. delete The method of claim 1, The second capacitor electrode is a substrate for a COT structure liquid crystal display device configured in parallel with the gate wiring. Forming a top gate type thin film transistor including an active layer, a gate electrode, a source electrode, and a drain electrode on the substrate; Forming a storage capacitor comprising a first capacitor electrode and a second capacitor electrode and adjacent to the top gate type thin film transistor; Forming a black matrix on the top gate thin film transistor; Forming a first transparent pixel electrode in the pixel region in contact with the drain electrode; Forming a color filter on the first transparent pixel electrode in the pixel region; Forming a second transparent pixel electrode on the color filter and in contact with the first transparent pixel electrode Wherein the active layer and the first capacitor electrode are integrally formed on the same layer of the same material, and the first transparent pixel electrode and the second transparent pixel electrode are simultaneously patterned so that their ends coincide with each other on the black matrix. And the first transparent pixel electrode is formed to overlap the second capacitor. The method of claim 1, wherein the first transparent pixel electrode is formed to overlap the second capacitor. The method of claim 9, Forming a buffer layer between the top gate type thin film transistor and the substrate, forming a gate insulating film between the active layer and the gate electrode and between the first capacitor electrode and the second capacitor electrode; And forming an interlayer insulating film formed on the substrate and covering the gate electrode and the second capacitor electrode. The method of claim 10, And forming first and second contact holes exposing an active layer on the gate insulating film and the interlayer insulating film, wherein the source electrode contacts the active layer through the first contact hole, and the drain electrode is formed of the first and second contact holes. 2 A method of manufacturing a substrate for a COT structure liquid crystal display device formed to contact the active layer through a contact hole. The method of claim 9, Forming a protective layer under the first transparent pixel electrode, the protective layer covering the drain electrode and the black matrix and having a third contact hole exposing the drain electrode; A method of manufacturing a substrate for a liquid crystal display device having a COT structure to contact the drain electrode of the top gate thin film transistor through a contact hole. The method of claim 9, And the black matrix is formed of one selected from a light blocking insulating material and a black resin. The method of claim 9, The active layer is formed of polysilicon to have an "L" shape, and is divided into a first region corresponding to the gate electrode and a second region on both sides of the first region, and doping the second region with impurities. Method of manufacturing a substrate for a COT structure liquid crystal display device comprising the step of). delete The method of claim 9, And the second capacitor electrode is parallel to the gate wiring.

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