KR100728556B1 - Data output circuit of semiconductor memory device - Google Patents

Abstract

The present invention provides a data output circuit of a semiconductor memory device that reduces current loss by simplifying a process of generating an output enable signal generated for data output.

The data output circuit of the semiconductor memory device of the present invention comprises delay means for generating and outputting an output enable clock signal by giving different delay times to the input clock according to CAS latency; First output enable signal generation means for receiving the input clock and the output enable initial signal and generating and outputting a first output enable signal having a different generation time according to the CAS latency; And second output enable signal generation means for receiving the first output enable signal and the output enable clock signal to generate and output a second output enable signal.

Semiconductor memory device, data output, output enable

Description

Circuit for Outputting Data in Semiconductor Memory Apparatus

1 is a block diagram showing the configuration of a data output circuit of a semiconductor memory device according to the prior art;

FIG. 2 is a block diagram showing a detailed configuration of a data output circuit of the semiconductor memory device shown in FIG. 1;

3 is an internal configuration diagram of the output enable clock signal generating means shown in FIGS. 1 and 2;

4 is a timing diagram for explaining an operation of a data output circuit of a semiconductor memory device according to the prior art;

5 is a block diagram showing a configuration of a data output circuit of a semiconductor memory device according to the present invention;

6 is an internal configuration diagram of a delay unit shown in FIG. 5;

7 is an internal configuration diagram of the first output enable signal generating means shown in FIG. 5;

FIG. 8 is an internal configuration diagram of the second output enable signal generating means shown in FIG. 5;

9 is a timing diagram for describing an operation of a data output circuit of a semiconductor memory device according to the present invention.

<Description of the symbols for the main parts of the drawings>

10/40: delay means

20: output enable clock signal generating means

30: output enable signal generating means

50: first output enable signal generating means

60: second output enable signal generating means

The present invention relates to a data output circuit of a semiconductor memory device, and more particularly, to a data output circuit of a semiconductor memory device that reduces current loss by simplifying a process of generating an output enable signal generated for data output.

In general, a semiconductor memory device outputs an output enable signal to output data according to clock cycles according to CAS column address strobe latency based on a clock transmitted from a delay locked loop (DLL) circuit when outputting data. Generate and perform data output operation. A CAS latency signal is generated that is synchronized with the rising edge of the clock in accordance with the CAS latency input by the CAS latency decoder provided to accept CAS latency.

Hereinafter, a data output circuit of a semiconductor memory device according to the related art will be described with reference to FIGS. 1 to 4.

1 is a block diagram illustrating a configuration of a data output circuit of a semiconductor memory device according to the related art, and illustrates an example of generating an output enable signal for outputting data up to a CAS latency of 9. It is also assumed that six output enable clock signals are generated, resulting in eight output enable signals.

The data output circuit of the semiconductor memory device may receive a clock (hereinafter referred to as a DLL clock dll_clk) transmitted from a DLL circuit and generate and output a plurality of CAS latency clock signals CL_clk having different delay times. 10) receiving a CAS latency signal CL_sig enabled and delivered from a CAS latency decoder according to a CAS latency input from an outside of a chip, and receiving the plurality of CAS latency clock signals CL_clk from the delay means 10. An output enable clock signal generation means 20 for generating and outputting an output enable clock signal oe_clk for outputting data at an edge time and an output enable initial signal oe_i and the output enable clock signal oe_clk. Number of output enable signals generated by receiving) and generating and outputting an output enable signal (oe) for data output. It is composed of 30.

The delay means 10 generates a plurality of CAS latency clock signals CL_clk for generating an output enable signal oe for each CAS latency by delaying the input DLL clock dll_clk. As shown in the figure, the DLL clock (dll_clk), CAS latency 3 clock signal (CL3_clk), CAS latency 45 clock signal (CL45_clk), CAS latency 67 from the delay means 10 to the output enable clock signal generation means 20. The clock signal CL67_clk and the CAS latency 89 clock signal CL89_clk are respectively transmitted. In this case, the CAS latency 3 clock signal CL3_clk is a signal for generating an output enable signal oe for outputting data to CAS latency 3. The CAS latency 45 clock signal CL45_clk is a signal for generating an output enable signal oe for outputting data at CAS latency 4 or CAS latency 5 and is a CAS latency 67 clock signal CL67_clk and a CAS latency 89 clock. The signal CL89_clk can be understood similarly.

The output enable clock signal generating means 20 receives the plurality of CAS latency clock signals CL_clk and the CAS latency signals CL_sig and outputs an output enable 60 clock signal from an output enable 10 clock signal oe10_clk. Generates six output enable clock signals (oe <10:60> _clk) up to oe60_clk. The output enable 10 clock signal oe10_clk is inputted to the output enable signal generating means 30 and output delayed 10 signal which is delayed with respect to the DLL clock dll_clk relative to the output enable initial signal oe_i. Used to generate (oe10). Similarly, the output enable 20 clock signal oe20_clk generates an output enable 20 signal oe20 that occurs later than the output enable 10 signal oe10 based on the DLL clock dll_clk. The output enable 30 clock signal to the output enable 50 clock signal (oe <30:50> _clk) also generate the output enable 30 signal to the output enable 50 signal (oe <30:50>) in the same manner. However, the output enable 60 clock signal oe60_clk is input to the output enable signal generating means 30 to generate an output enable 60 signal to an output enable 80 signal oe <60:80>.

An operation of the data output circuit of the semiconductor memory device will be described in more detail with reference to FIG. 2.

FIG. 2 is a block diagram illustrating a detailed configuration of a data output circuit of the semiconductor memory device shown in FIG. 1.

The delay means 10 includes a plurality of delay units, and the DLL clock dll_clk is input to the plurality of delay units, respectively, and converted into a plurality of clock signals having different delay times. That is, the illustrated first delay unit 101 generates and outputs the CAS latency 3 clock 10 signal CL3_clk10 for generating the output enable 10 signal oe10 at CAS latency 3 by delaying the DLL clock dll_clk. . The second delay unit 102 receives a CAS latency 45 clock 10 signal CL45_clk10, the third delay unit 103 receives a CAS latency 45 clock 20 signal CL45_clk20, and the fourth delay unit 104 transmits a CAS latency 45. The clock 30 signal CL45_clk30, the fifth delay unit 105, CAS latency 67 clock 10 signal (CL67_clk10), the sixth delay unit 106, CAS latency 67 clock 20 signal (CL67_clk20), the seventh delay unit. Reference numeral 107 denotes a CAS latency 67 clock 30 signal CL67_clk30, an eighth delay unit 108 denotes a CAS latency 67 clock 40 signal CL67_clk40, and a ninth delay unit 109 denotes a CAS latency 89 clock 10 signal CL89_clk10. ), The tenth delay unit 110 receives the CAS latency 89 clock 20 signal CL89_clk20, the eleventh delay unit 111 receives the CAS latency 89 clock 30 signal CL89_clk30, and the twelfth delay unit 112 receives the CAS Each of the latency 89 clock 40 signal CL89_clk40 and the thirteenth delay unit 113 output the CAS latency 89 clock 50 signal CL89_clk50 to the DLL clock dll_clk, respectively. It generates the grant.

The output enable clock signal generating means 20 generates and outputs six output enable clock signals oe <10:60> _clk from the plurality of CAS latency clock signals CL_clk according to the input CAS latency. .

The six output enable clock signals oe <10:60> _clk are transmitted to the output enable signal generating means 30. The output enable signal generating means 30 has eight flip flops. The first flip-flop 301 receives the output enable initial signal oe_i and the output enable 10 clock signal oe10_clk, and generates and outputs the output enable 10 signal oe10. The second flip-flop 302 receives the output enable 10 signal oe10 and the output enable 20 clock signal oe20_clk and generates and outputs the output enable 20 signal oe20. In addition, the third flip-flop 303 receives the output enable 20 signal oe20 and the output enable 30 clock signal oe30_clk, and generates and outputs the output enable 30 signal oe30. In the same manner, the fourth to eighth flip-flops 304 to 308 generate and output the output enable 40 signals to the output enable 80 signals oe <40:80>, respectively. However, at this time, the output enable 60 clock signal to the output enable 80 clock signal oe <60:80> _clk are respectively input to the sixth to eighth flip-flops 306 to 308.

3 is an internal configuration diagram of the output enable clock signal generating means shown in FIGS. 1 and 2.

The output enable clock signal generating means 20 includes six selectors for generating and outputting different output enable clock signals oe_clk according to the CAS latency input. The first selector 210 of the six selectors includes a first passgate 211 that is turned on when the CAS latency is 2 so that the DLL clock is turned on when the first passgate 211 is turned on. Pass (dll_clk) to an even array of inverters connected in series. In addition, the first selector 210 includes a second passgate 212 that is turned on when the CAS latency 3 is set. When the second passgate 212 is turned on, the first selector 210 supplies the CAS latency 3 clock 10 signal CL3_clk10. It delivers to the array of even numbers of inverters connected in series. Similarly, a third passgate 213 may output the CAS latency 45 clock 10 signal when the CAS latency is 4 or 5, and a fourth passgate 214 may output the CAS latency 67 clock 10 signal when the CAS latency is 6 or 7. The five passgate 215 delivers the CAS latency 89 clock 10 signal to the series of even-numbered inverter arrays when the CAS latency is 8 or 9. Each signal driven by the even-numbered inverter array connected in series becomes the output enable 10 clock signal oe10_clk and is transmitted to the output enable signal generation means 30.

In the same manner, the second selector 220 uses the DLL clock dll_clk when the CAS latency is 2 or 3, the CAS latency 45 clock 20 signal CL45_clk20 when the CAS latency is 4 or 5, and the CAS latency is 6 or 7. The CAS latency 67 clock 20 signal CL67_clk20 is transmitted to the CAS latency 89 clock 20 signal CL89_clk20 when the CAS latency 8 or 9 is transmitted to an even number of inverter arrays connected in series. Each signal driven by the even-numbered inverter array connected in series becomes the output enable 20 clock signal oe20_clk and is transmitted to the output enable signal generating means 30.

Similarly, the third selector 230 uses the DLL clock dll_clk when the CAS latency is 2 or 3, the CAS latency 45 clock 30 signal CL45_clk30 when the CAS latency is 4 or 5, and the CAS latency is 6 or 7. The CAS latency 67 clock 30 signal CL67_clk30 is transferred to the CAS latency 89 clock 30 signal CL89_clk30 when the CAS latency is 8 or 9, respectively. Each signal driven by the even-numbered inverter array connected in series becomes the output enable 30 clock signal oe30_clk and is transmitted to the output enable signal generation means 30.

In addition, the fourth selector 240 selects the DLL clock dll_clk when the CAS latency is 2, 3, 4, or 5, and uses the CAS latency 67 clock 40 signal (CL67_clk40) when the CAS latency is 6 or 7. Alternatively, when 9, the CAS latency 89 clock 40 signal CL89_clk40 is transmitted to an even number of inverter arrays connected in series. Each signal driven by the even-numbered inverter array connected in series becomes the output enable 40 clock signal oe40_clk and is transmitted to the output enable signal generation means 30.

The fifth selector 250 converts the DLL clock signal dll_clk when the CAS latency is 2, 3, 4, 5, 6, or 7, and the CAS latency 89 clock 50 signal when the CAS latency is 8 or 9 (CL89_clk50). ) Are delivered to an even array of inverters each connected in series. Each signal driven by the even-numbered inverter array connected in series becomes the output enable 50 clock signal oe50_clk and is transmitted to the output enable signal generation means 30.

Finally, the sixth selector 260 generates the output enable 60 clock signal oe60_clk by driving the DLL clock dll_clk in an even number of inverter arrays connected in series regardless of the CAS latency inputted to generate the output enable. It passes to the signal generating means 30.

In this case, each of the passgates included in the first to sixth selectors 210 to 260 has a phase opposite to that of the CAS latency signal CL_sig and the CAS latency signal CL_sig transmitted from the CAS latency decoder. It is turned on or off by the CAS latency signal CL_sigb. For example, the first passgate 211 of the first selector 210 is turned on when the CAS latency 2 signal CL_sig2 and the sub CAS latency 2 signal CL_sig2b are enabled when the CAS latency 2 is set. . However, if the CAS latency changes and has a different value, it is turned off.

4 is a timing diagram for describing an operation of a data output circuit of a semiconductor memory device according to the related art.

When the DLL clock dll_clk, the output enable initial signal oe_i and the output enable 10 clock signal oe10_clk are input to the output enable signal generating means 30, the output enable initial signal oe_i. When is enabled, it can be seen that the output enable 10 signal oe10 is generated by the output enable 10 clock signal oe10_clk having a rising edge time. At this time, the output enable 10 signal oe10 is enabled after a slight delay compared to the rising edge time of the output enable 10 clock oe10_clk. In addition, when the output enable 10 signal oe10 is enabled, the output enable 20 signal oe20 is generated by the output 20 clock signal oe20_clk having a rising edge time and is enabled after a slight delay time. You can see that. In the same manner, the output enable 30 signal to the output enable 60 signal oe <30:60> are generated. However, the output enable 70 signal and the output enable 80 signal oe <70:80> are generated by the output enable 60 clock signal oe60_clk. That is, all of the output enable 60 to output enable 80 signals oe <60:80> are generated by the output enable 60 clock signal oe60_clk.

As such, the output enable signal oe for outputting data according to the input CAS latency is sequentially generated by each output enable clock signal oe_clk. However, when the CAS latency is long, such as CAS latency 8 or 9, an output enable clock signal (oe_clk) and an output enable signal (oe) are also generated to output data of short CAS latency, such as CAS latency 2 or 3. . Therefore, the unnecessary output enable clock signal oe_clk and the output enable signal oe are generated, resulting in a loss of current and a problem such as noise due to unnecessary flowing current.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and the semiconductor device can reduce the current loss by simplifying the generation of the output enable signal by generating an output enable signal generated for data output at different time points for each CAS latency. There is a technical problem in providing a data output circuit of a memory device.

According to another aspect of the present invention, there is provided a data output circuit of a semiconductor memory device, comprising: delay means for generating and outputting an output enable clock signal by giving different delay times to input clocks according to CAS latency; First output enable signal generation means for receiving the input clock and the output enable initial signal and generating and outputting a first output enable signal having a different generation time according to the CAS latency; And second output enable signal generation means for receiving the first output enable signal and the output enable clock signal to generate and output a second output enable signal.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of a data output circuit of a semiconductor memory device according to the present invention, and illustrates an example of generating an output enable signal for outputting data up to CAS latency 9. FIG.

As shown, the data output circuit of the semiconductor memory device according to the present invention provides a delay time to the DLL clock dll_clk according to the CAS latency CL <2: 9> so that the output enable clock signal oe_clk is different. Delay means 40 for generating and outputting a signal, an output enable initial signal oe_i, and the DLL clock dll_clk are inputted, and output enable 10 whose delay time varies according to the CAS latency CL <2: 9>. A first output enable signal generating means 50 for generating and outputting a signal oe10 and the output enable 10 signal oe10 and the output enable clock signal oe_clk are received and output enable 20 signal oe20 ) And second output enable signal generating means (60) for generating and outputting the &quot;

The operation of the data output circuit of the present invention configured as described above shows an internal configuration diagram of the delay means 40, the first output enable signal generating means 50 and the second output enable signal generating means 60. A description with reference to the drawings below.

6 is an internal configuration diagram of the delay means shown in FIG.

The delay means 40 delays the DLL clock dll_clk when the CAS latency is 3 to generate and output an output enable clock signal oe_clk, and when the CAS latency is 4 or 5. A second delay unit 420 which generates and outputs an output enable clock signal oe_clk by delaying the DLL clock dll_clk, and outputs the clock enable signal by delaying the DLL clock dll_clk when the CAS latency is 6 or 7. a third delay unit 430 for generating and outputting (oe_clk) and a fourth delay unit for generating and outputting an output enable clock signal oe_clk by delaying the DLL clock dll_clk when the CAS latency is 8 or 9. 440 and a fifth delay unit 450 that outputs the DLL clock dll_clk as an output enable clock signal oe_clk when CAS latency 2 is obtained.

Here, the first delay unit 410 may have a first passgate 411 passing through the DLL clock dll_clk when CAS latency 3 and the DLL clock dll_clk transferred from the first passgate 411. The first delay unit 413 is configured to generate and output the output enable clock signal oe_clk by giving a predetermined delay time. Similarly, the second to fourth delay units 410 to 440 also include second to fourth delayers 423 to 443 and second to fourth passgates 421 to 441, respectively. Thus, when the CAS latency is 4 or 5, the second delay unit 420 has a CAS latency of 4 or 5, and the third delay unit 440 has a CAS latency of 8 when the CAS latency is 6 or 7. Alternatively, when 9, the output enable clock signal oe_clk is generated and output. The fifth delay unit 450 includes a fifth passgate 451 to output the DLL clock dll_clk as the output enable clock signal oe_clk when the CAS latency is 2. In this case, since the first to fourth delayers 413 to 443 give different delay times, the output enable clock signals oe_clk having different timings are generated according to CAS latency.

Here, each of the passgates included in the first to fifth delay units 410 to 450 has a negative phase having a phase opposite to that of the CAS latency signal CL_sig and the CAS latency signal CL_sig transmitted from the CAS latency decoder. It is turned on or off by the CAS latency signal CL_sigb. For example, the first pass gate 411 of the first delay unit 410 is turned on when the CAS latency 3 signal CL_sig3 and the sub CAS latency 3 signal CL_sig3b are enabled when the CAS latency is 3. . However, if the CAS latency changes and has a different value, it is turned off.

FIG. 7 is an internal configuration diagram of the first output enable signal generating means shown in FIG. 5.

The first output enable signal generating means 50 includes a first passgate 510 for passing the output enable initial signal oe_i when CAS latency 2 and the output enable initial signal when CAS latency 3. The output enable initial state when the DLL clock signal dll_clk is enabled by receiving the second passgate 520 that passes oe_i, the output enable initial signal oe_i, and the DLL clock signal dll_clk. A first flip-flop 530 for delaying and outputting a signal oe_i for a predetermined time; a third pass gate 540 for passing a signal transmitted from the first flip-flop 530 when the CAS latency is 4 or 5; Delay the signal transmitted from the first flip-flop 530 when the DLL clock signal dll_clk is enabled by receiving the signal transmitted from the first flip-flop 530 and the DLL clock signal dll_clk. To output A second pass-flop 550, a fourth passgate 560 for passing a signal transmitted from the second flip-flop 550 when the CAS latency is 6 or 7, and a signal transmitted from the second flip-flop 550 And a third flip-flop 570 that receives the DLL clock signal dll_clk and outputs the delayed signal from the second flip-flop 550 by a predetermined time when the DLL clock signal dll_clk is enabled. When the CAS latency is 8 or 9, the fifth passgate 580 passes a signal transmitted from the third flip-flop 570.

The first to fifth passgates 510 to 580 are turned on by a CAS latency signal CL_sig transmitted from a CAS latency decoder and a negative CAS latency signal CL_sigb having a phase opposite to that of the CAS latency signal CL_sig. It is turned on or off.

In this case, the signal passing through the first and second passgates 510 and 520 is an output enable 10_a signal oe10_a, and the signal passing through the third passgate 540 is an output enable 10_b signal oe10_b. ), The signal passing through the fourth passgate 560 is an output enable 10_c signal oe10_c, and the signal passing through the fifth passgate 580 is an output enable 10_d signal oe10_d. The four output enable 10 signals oe10_ <a: d> are all the output enable 10 signals oe10. That is, according to the above configuration, the output enable 10 signal oe10 is generated after being delayed for a different time from the output enable initial signal oe_i according to the CAS latency for a different time. Can be inferred. That is, the timing at which the output enable 10 signal oe10 is enabled when the CAS latency is short is closer to the output enable initial signal oe_i than when the CAS latency is long.

8 is an internal configuration diagram of the second output enable signal generating means shown in FIG.

The second output enable signal generating means 60 is the output enable 10 signal oe10 transmitted from the first output enable signal generating means 50 and the output in delivered from the delay means 40. The flip-flop 610 is configured to receive the enable clock signal oe_clk and generate and output an output enable 20 signal oe20 when the output enable clock signal oe_clk is enabled.

When the CAS latency is long, the output enable clock signal oe_clk and the output enable 10 signal oe10 have a CAS latency due to the structural characteristics of the delay means 40 and the first output enable signal generation means 50, respectively. It will occur later because it will have a larger delay time than when it is short. Accordingly, a time point at which the output enable 20 signal oe20 output from the flip-flop 610 occurs according to CAS latency varies.

Since the CAS latency is flexible, the data output operation when the CAS latency is greater than 9 is expected, and a constant delay time is given to the output enable clock signal oe_clk output from the delay means 40 to enable the output. The clock signal oe20_clk may be generated. In addition to the flip-flop 610 in the second output enable signal generating means 60, another flip-flop is provided so that the output enable 20 signal oe20 when the output enable 20 clock signal is enabled. Delays a predetermined time to generate an output enable 30 clock signal oe30. This method can also be appropriately applied depending on the length of CAS latency.

9 is a timing diagram for describing an operation of a data output circuit of a semiconductor memory device according to the present invention.

In the figure, a DLL clock dll_clk and an output enable initial signal oe_i are shown. When the output enable initial signal oe_i is enabled, an output enable 10 signal oe10 is generated by the DLL clock dll_clk having a rising edge time. In this case, the time at which the output enable 10 signal oe10 is generated depends on the CAS latency. That is, when the CAS latency is short, the output enable 10_a signal oe10_a is generated and according to the length of the CAS latency, the output enable 10_b signal oe10_b, the output enable 10_c signal oe10_c, or the output enable 10_d signal. Since oe10_d is generated, the output enable 10 signal oe10 is a signal in which the time of occurrence is flexible according to the length of the CAS latency. This operation is due to the delay time given by the first to third flip-flops 530, 550, and 570 of the first output enable signal generating means 50. When the output enable 10 signal oe10 is enabled, an output enable 20 signal oe20 is generated by an output enable clock signal oe_clk having a rising edge time and finally used for a data output operation. The output enable 20 signal oe20 shown in FIG. 9 is generated by the output enable 10 signal oe10 when the CAS latency is 8 or 9. FIG. Since the generation time of the output enable 10 signal oe10 is flexible according to the CAS latency, the generation time of the output enable 20 signal oe20 also changes according to the CAS latency.

As described above, in the data output circuit of the present invention, only two output enable signals oe are generated and only one output enable clock signal oe_clk is generated so that the current loss can be reduced. It became. That is, the generation time of the output enable clock signal oe_clk and the output enable signal oe is changed flexibly according to the input CAS latency, thereby reducing current loss due to unnecessary current, thereby reducing side effects such as noise. Can be reduced. In addition, since the output enable signal (oe) can be generated using only a small number of components (for example, flip-flops), the timing margin between each signal and the component may be reduced in a high speed semiconductor memory device. Malfunctions were prevented.

However, the output enable signal oe and the output enable clock signal oe_clk described above are not limited to the form shown in the drawing. That is, the number of the output enable signal oe and the number of the output enable clock signal oe_clk may be different from those described above. Accordingly, it is a feature of the present invention to reduce the current loss by preventing the generation of the output enable signal and the output enable clock signal by changing the output enable signal according to the CAS latency. .

As such, those skilled in the art will appreciate that the present invention can be implemented in other specific forms without changing the technical spirit or essential features thereof. Therefore, the above-described embodiments are to be understood as illustrative in all respects and not as restrictive. The scope of the present invention is shown by the following claims rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalents should be construed as being included in the scope of the present invention. do.

The data output circuit of the semiconductor memory device according to the present invention described above generates an output enable signal generated for data output at different points in time for each CAS latency, thereby simplifying the generation of the output enable signal, thereby reducing current loss. Since the output enable signal can be generated using only a small number of components, there is an effect of preventing a malfunction that may occur due to a decrease in timing margin between each signal and the component in a high speed semiconductor memory device.

Claims (7)

Delay means for generating and outputting an output enable clock signal by giving different delay times to the input clock according to the CAS latency; First output enable signal generation means for receiving the input clock and the output enable initial signal and generating and outputting a first output enable signal having a different generation time according to the CAS latency; And Second output enable signal generation means for receiving the first output enable signal and the output enable clock signal to generate and output a second output enable signal; And a data output circuit of the semiconductor memory device. The method of claim 1, The delay means, And a plurality of delay units configured to generate and output an output enable clock signal by giving a delay time to the input clock for each CAS latency. The method of claim 2, The delay unit, A passgate configured to pass the input clock in response to an input of a CAS latency signal; And A delayer for generating and outputting the output enable clock signal by giving a predetermined delay time to the input clock transferred from the passgate; And a data output circuit of the semiconductor memory device. The method of claim 3, wherein And said passgate is turned on or off by a CAS latency signal and a negative CAS latency signal having an enable timing different according to CAS latency. The method of claim 1, The first output enable signal generating means, At least one flip-flop connected in series to receive the input clock and the output enable initial signal and to sequentially delay the output enable initial signal when the input clock is enabled; And A plurality of passgates configured to selectively pass the output enable initial signal and a signal delayed by the at least one flip-flop in response to an input of a CAS latency signal to output the first output enable signal; And a data output circuit of the semiconductor memory device. The method of claim 5, And the plurality of passgates are turned on or off by a CAS latency signal and a secondary CAS latency signal having different enable points according to CAS latency. The method of claim 1, The second output enable signal generating means, A second output enable when the output enable clock signal is enabled by receiving the first output enable signal delivered from the first output enable signal generation means and the output enable clock signal delivered from the delay means; And a flip-flop for generating and outputting a signal.

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