KR100609995B1 - Semiconductor memory device - Google Patents

Abstract

The present invention discloses a semiconductor memory device. The present invention relates to a memory cell array; A block sense amplifier; A dummy block sense amplifier configured to receive a power supply voltage and generate the same dummy sense data pair at all times regardless of a read or write operation; A dummy main sense amplifier for differentially amplifying the dummy sense data pairs to generate dummy output data pairs; A reference voltage generator configured to generate a first reference voltage having a predetermined level and a second reference voltage having a lower level than the first reference voltage; A level comparison unit comparing the dummy output data pairs with the levels of the first and second reference voltages to generate a plurality of control signals; First and second junction transistors having a base to which the sense data pairs from the block sense amplifier are applied one by one, and connected to the collectors of the first and second junction transistors one by one to receive resistors according to the plurality of control signals. Comprising a first and a second variable resistor having a variable value to compensate for the change in the resistance value generated in the process, and a differential amplification of the sense data pair in the state that the change in the resistance value is compensated for the main to generate an output data pair It is equipped with a sense amplification unit, and automatically compensates for a change in the resistance value of the main sense amplifier in the semiconductor process, thereby minimizing the change in gain of the main sense amplifier. Therefore, memory due to an increase in sensing margin, current, or speed delay, etc. There is an effect that the characteristic change of the chip is prevented.

Description

A semiconductor memory device             

1 is a circuit diagram of a typical main sense amplifier,

2 is a block diagram illustrating some components of a semiconductor memory device according to an embodiment of the present invention;

3 is a circuit diagram of the main sense amplifier shown in FIG.

The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device having a main sense amplifier.

In today's high-volume semiconductor process, unexpected changes in the process (process variation) or corresponding conditions change the characteristics of the memory chip, one of which is the main sense amplifier provided in the semiconductor memory device The resistance value of is changed and the gain of the main sense amplifier is changed.

The change in the resistance value of the main sense amplifier has a direct effect on the gain of the main sense amplifier, so that the gain becomes worse or better than the set value, which is caused by an increase or a speed of sensing margin, current, or the like. This can cause delays, etc., resulting in changes in the characteristics of the memory chip.

However, conventionally, when the resistance value of the main sense amplifier changes due to an unexpected process change in the semiconductor process, there is a problem in that the value cannot be corrected.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and an object thereof is to provide a semiconductor memory device capable of minimizing a change in gain of a main sense amplifier by automatically compensating for a change in resistance value of a main sense amplifier generated in a process. have.

In order to achieve the above object, a semiconductor memory device according to the present invention comprises a memory cell array; A block sense amplifier for amplifying data read from the memory cell array to generate a sense data pair; A dummy block sense amplifier configured to receive a power supply voltage and generate the same dummy sense data pair at all times regardless of a read or write operation; A dummy main sense amplifier for differentially amplifying the dummy sense data pairs to generate dummy output data pairs; A reference voltage generator configured to generate a first reference voltage having a predetermined level and a second reference voltage having a lower level than the first reference voltage; A level comparison unit comparing the dummy output data pairs with the levels of the first and second reference voltages to generate a plurality of control signals; First and second junction transistors each having a base to which the sense data pairs are applied one by one, and a first one connected to the collectors of the first and second junction transistors one by one to change resistance values according to the plurality of control signals. And a main sense amplifier configured to compensate for the change in the resistance value generated in the process by a second variable resistor part and to differentially amplify the sense data pair in the state where the change in the resistance value is compensated. It features.

Prior to the description of the present invention, the configuration and operation of a general main sense amplifier will be described.

1 is a circuit diagram of a general main sense amplifier, in which the main sense amplifier includes eleventh and twelfth resistors R11 and R12, first to fourth NPN transistors Q1 to Q4, and eleventh to sixteenth NMOS transistors. It consists of (N11-N16).

The eleventh and twelfth resistors R11 and R12 have one end to which a power supply voltage is applied.

The first NPN transistor Q1 includes a collector connected to the other end of the eleventh resistor R11 and a base to which non-inverted sense data DATA is applied among sense data pairs from a block sense amplifier (not shown). Have

The second NPN transistor Q2 includes a collector connected to the other end of the twelfth resistor R12, an emitter connected to the emitter of the first NPN transistor Q1, and inverted sense data among sense data pairs from the block sense amplifier. It has a base to which (DATAb) is applied.

The third NPN transistor Q3 has a base commonly connected to the other end of the eleventh resistor R11, the collector of the first NPN transistor Q1, an emitter connected to the inverting output terminal, and a collector to which a power supply voltage is applied.

The fourth NPN transistor Q4 has a base commonly connected to the other end of the twelfth resistor R12 and the collector of the second NPN transistor Q2, an emitter connected to the non-inverting output terminal, and a collector to which a power supply voltage is applied. .

The eleventh NMOS transistor N11 has a drain connected to a common emitter of the first and second NPN transistors Q1 and Q2 and a gate to which a reference voltage Vref is applied.

The twelfth NMOS transistor N12 has a drain connected to a source of the eleventh NMOS transistor N11, a source connected to ground, and a gate to which a sense amplifier enable signal PSA is applied.

The thirteenth NMOS transistor N13 has a drain connected to an inverting output terminal and a gate to which a reference voltage Vref is applied.

The fourteenth NMOS transistor N14 has a drain connected to a source of the thirteenth NMOS transistor N13, a source connected to ground, and a gate to which a sense amplifier enable signal PSA is applied.

The fifteenth NMOS transistor N15 has a drain connected to a non-inverting output terminal and a gate to which a reference voltage Vref is applied.

The sixteenth NMOS transistor N16 has a drain connected to a source of the fifteenth NMOS transistor N15, a source connected to ground, and a gate to which a sense amplifier enable signal PSA is applied.

The reference voltage Vref is applied to the eleventh and twelfth NMOS transistors N11 and N12, the thirteenth and fourteenth NMOS transistors N13 and N14, and the fifteenth and sixteenth NMOS transistors N15 and N16. And when the sense amplifier enable signal PSA is enabled to a "high" level, it acts as a constant current source.

The operation of the general main sense amplifier configured as described above is as follows.

A sense amplifier during a data read operation in a state in which the reference voltage Vref is applied to the gates of the eleventh, thirteenth, and fifteenth NMOS transistors N11, N13, and N15 so that the NMOS transistors N11, N13, and N15 are turned on. When the enable signal PSA is enabled at the "high" level, the twelfth, fourteenth and sixteenth NMOS transistors N12, N14, and N16 are turned on to enable the operation of the main sense amplifier.

As described above, when the sense data pairs DATA and DATAb from the block sense amplifier are applied to the bases of the first and second NPN transistors Q1 and Q2 while the operation of the main sense amplifier is enabled, the sense data pairs are applied. The voltage difference between DATA and DATAb causes a difference in the currents I11 and I12 flowing through the eleventh and twelfth resistors R11 and R12, and the eleventh and twelfth resistors R11 and R12. Voltages caused by the currents I11 and I12 are generated in the data pairs SAS0 and SAS0b.

Thereafter, one of the third and fourth NPN transistors Q3 and Q4 is turned on by the data pairs SAS0 and SAS0b to generate the final output data pairs SAS and SASb through the inverted and non-inverted output terminals. .

Meanwhile, when the resistance values of the eleventh and twelfth resistors R11 and R12 of the main sense amplifier are lower than the preset value due to an unexpected process change or a corresponding condition change in the semiconductor process, the eleventh and twelfth resistors ( The voltages of the data pairs SAS0 and SAS0b are increased by increasing the currents I11 and I12 flowing through R11 and R12, so that the gain of the final output data pairs SAS and SASb is smaller. You lose. On the other hand, when the resistance of the eleventh and twelfth resistors R11 and R12 of the main sense amplifier is higher than the set value, the currents I11 and I12 flowing through the eleventh and twelfth resistors R11 and R12 are set. As a result, the voltage level of the data pairs SAS0 and SAS0b is decreased, thereby increasing the gain of the final output data pairs SAS and SASb. The gain change of this main sense amplifier is one factor of the speed delay.

As described above, when the resistance value of the main sense amplifier in the semiconductor process is different from the set value, the gain of the main sense amplifier changes, resulting in a change in characteristics of the memory chip due to an increase in sensing margin, current, or speed delay. In the related art, the change in resistance value of the main sense amplifier generated in the process cannot be corrected.

2 is a block diagram illustrating some components of a semiconductor memory device in accordance with an embodiment of the present invention, wherein the semiconductor memory device includes a memory cell array (not shown), a block sense amplifier 10, and a dummy block sense amplifier. 20, a dummy main sense amplifier 30, a reference voltage generator 40, a level comparator 50, and a main sense amplifier 60 are provided.

The block sense amplifier 10 amplifies data read from the memory cell array to generate sense data pairs DATA and DATAb.

When power is applied, the dummy block sense amplifier 20 receives a power supply voltage regardless of a read or write operation to always generate the same dummy sense data pairs DDATA and DDATAb.

The dummy main sense amplifier 30 differentially amplifies the dummy sense data pairs DDATA and DDATAb from the dummy block sense amplifier 20 to generate dummy output data pairs DSAS and DSASb.

The reference voltage generator 40 generates the first and second reference voltages V1 and V2 at preset levels. Here, the first reference voltage V1 is set at a level higher than the predetermined output level of the main sense amplifier 60, and the second reference voltage V2 is at a level lower than the output level of the predetermined main sense amplifier 60. Is set to. For example, when the output level voltage of the main sense amplifier 60 is set to 2.5V, the first reference voltage V1 may generate 3V, and the second reference voltage V2 may generate 2V.

The level comparator 50 compares the level of the dummy output data pairs DSAS and DSASb from the dummy main sense amplifier 30 with the levels of the first and second reference voltages V1 and V2 from the reference voltage generator 40. To generate the first to third control signals G1 to G3.

The main sense amplifier 60 includes first and second NMOS transistors having a base to which sense data pairs DATA and DATAb from the block sense amplifier 10 are applied one by one, and collectors of the first and second NMOS transistors. Compensated for the change in the resistance value generated in the process by having a first and a second variable resistor unit connected to each one and the resistance value is changed in accordance with the first to third control signals (G1 to G3) from the level comparator 50 The output data pairs SAS and SASb are generated by differentially amplifying the sense data pairs DATA and DATAb while the change of the resistance value is compensated.

3 is a circuit diagram of the main sense amplifier illustrated in FIG. 2, wherein the main sense amplifier 60 may include a first variable resistor unit instead of an eleventh resistor R11 in the collector of the first NPN transistor Q1 illustrated in FIG. 1. 61 is connected, and the second variable resistor 62 is connected to the collector of the second NPN transistor Q2 instead of the twelfth resistor R12.

The first variable resistor unit 61 varies the collector resistance of the first NPN transistor Q1 according to the first to third control signals G1 to G3 from the level comparator 50 shown in FIG. 2. . The first variable resistor unit 61 includes a first resistor R1 having one end to which a power supply voltage is applied, a second resistor R2 having one end connected to the other end of the first resistor R1, and the first resistor R1. A third resistor R3 having one end connected to the other end of the second resistor R2, a gate connected between the first and second resistors R1 and R2, and a gate to which the first control signal G1 is applied; 1 NN transistor N1 having a source connected to the collector of 1 NPN transistor Q1, a drain connected between the second and third resistors R2 and R3, and a gate to which the second control signal G2 is applied. And a second NMOS transistor N2 having a source connected to the source of the first NMOS transistor N1, a drain connected to the other end of the third resistor R3, and a gate to which the third control signal G3 is applied. To a third NMOS transistor N3 having a source connected to the sources of the first and second NMOS transistors N1 and N2; It is sex.

The second variable resistor unit 62 varies the collector resistance of the second NPN transistor Q2 according to the first to third control signals G1 to G3 from the level comparator 50 shown in FIG. 2. . The second variable resistor unit 62 includes a fourth resistor R4 having one end to which a power voltage is applied, a fifth resistor R5 having one end connected to the other end of the fourth resistor R4, and the fifth resistor R5. A sixth resistor R6 having one end connected to the other end of the fifth resistor R5, a drain connected between the fourth and fifth resistors R4 and R5, and a gate to which the first control signal G1 is applied; A fourth NMOS transistor N4 having a source connected to the collector of the second NPN transistor Q2, a drain connected between the fifth and sixth resistors R5 and R6, and a gate to which the second control signal G2 is applied. And a fifth NMOS transistor N5 having a source connected to the source of the fourth NMOS transistor N4, a drain connected to the other end of the sixth resistor R6, and a gate to which the third control signal G3 is applied. To a sixth NMOS transistor N6 having a source connected to the sources of the fourth and fifth NMOS transistors N4 and N5. It is sex.

In addition, although not shown in the drawing, the dummy main sense amplifier 30 has a circuit configuration similar to that of the main sense amplifier 60 shown in FIG. 3. That is, in the case of the dummy main sense amplifier 30, a power supply voltage is applied to the gates of the twelfth, fourteenth and sixteenth NMOS transistors N12, N14, and N16 illustrated in FIG. 3 instead of the sense amplifier enable signal PSA. The ground voltage is applied instead of the first and third control signals G1 and G3, and the power supply voltage is applied instead of the second control signal G2, so that the first NPN transistor is applied by the first and second resistors R1 and R2. A constant dummy output is always constant regardless of read or write operation in a state in which the collector resistance value of Q1 is determined and the collector resistance value of the second NPN transistor Q2 is determined by the fourth and fifth resistors R4 and R5. It is configured to generate data pairs (DSAS, DSASb).

Referring to the operation of the semiconductor memory device according to an embodiment of the present invention configured as described above are as follows.

First, when power is applied to the semiconductor memory device, the dummy block sense amplifier 20 generates dummy sense data pairs DDATA and DDATAb and outputs the dummy sense data pairs DDATA and DDATAb to the dummy main sense amplifier 30. The dummy sense data pairs DDATA and DDATAb received are differentially amplified to generate dummy output data pairs DSAS and DSASb and output to the level comparator 50.

The level comparator 50 then compares the voltage levels of the dummy output data pairs DSAS and DSASb with the levels of the first and second reference voltages V1 and V2 from the reference voltage generator 40. At this time, when the resistance value change occurs due to an unexpected process change or a corresponding condition change in the semiconductor process, the voltage level of the dummy output data pairs DSAS and DSASb generated by the dummy main sense amplifier 30 is set to zero. If the level is higher than the level of the first reference voltage V1 or lower than the level of the second reference voltage V2, and there is no change in the resistance value, the voltage level of the dummy output data pairs DSAS and DSASb is the first reference. The level is between the voltage V1 and the second reference voltage V2.

Accordingly, the level comparator 50 may enable the first control signal G1 and the low level to be “high” when the level of the dummy output data pairs DSAS and DSASb is higher than the level of the first reference voltage V1. The second and third control signals G2 and G3 of the level are generated and output to the main sense amplifier 60, and the level of the dummy output data pairs DSAS and DSASb is lower than the level of the second reference voltage V2. In this case, the third control signal G3 enabled at the "high" level and the first and second control signals G1 and G2 at the "low" level are generated and output to the main sense amplifier 60, and the dummy output data. If the level of the pair DSAS, DSASb is a level between the first reference voltage V1 and the second reference voltage V2, the second control signal G2 and the "low" level enable the "high" level. The first and third control signals G1 and G3 are generated and output to the main sense amplifier 60.

As a result, when the first control signal G1 is applied at the "high" level, the first and fourth NMOS transistors N1 and N4 of the main sense amplifier 60 are turned on and turned on by the first resistor R1. The collector resistance value of the first NPN transistor Q1 is determined, the collector resistance value of the second NPN transistor Q2 is determined by the fourth resistor R4, and the second control signal G2 is set to the "high" level. When applied, the second and fifth NMOS transistors N2 and N5 are turned on, and the collector resistance values R1 + R2 of the first NPN transistor Q1 are determined by the first and second resistors R1 and R2. And the collector resistance value R4 + R5 of the second NPN transistor Q2 is determined by the fourth and fifth resistors R4 and R5, and the third control signal G3 is applied at the "high" level. The third and sixth NMOS transistors N3 and N6 are turned on to determine the collector resistance values R1 + R2 + R3 of the first NPN transistor Q1 by the first to third resistors R1 to R3. 4th mine The collector resistance value R4 + R5 + R6 of the second NPN transistor Q2 is determined by the sixth resistors R4 to R6.

The above process is performed when the collector resistor values of the first and second NPN transistors Q1 and Q2 of the main sense amplifier 60 are larger than the set values, so that the gain of the output data pairs SAS and SASb is increased. The fourth NMOS transistors N1 and N4 are turned on to decrease collector resistance values of the first and second NPN transistors Q1 and Q2, and the collector resistance values of the first and second NPN transistors Q1 and Q2 are reduced. When the gain of the output data pairs SAS and SASb is lower than the set value, the third and sixth NMOS transistors N3 and N6 are turned on to collect the first and second NPN transistors Q1 and Q2. It is a process of automatically minimizing the gain change of the main sense amplifier 60 due to the process change by increasing the resistance value.

When the read operation of the data as described above is performed while the gain of the main sense amplifier 60 is determined through the above process, the main sense amplifier 60 is generated even if the resistance value change due to the process change occurs. The gains of the output data pairs SAS and SASb do not change.

Accordingly, in the semiconductor memory device according to an embodiment of the present invention, the resistance values of the resistors R1 to R6 included in the main sense amplifier 60 may be increased due to an unexpected process change or a corresponding condition change in the semiconductor process. Even if the gain is changed, the gain of the main sense amplifier 60 does not change, and thus, as in the prior art, no increase in sensing margin, current, or speed delay is caused.

In addition, although only one block sense amplifier and one main sense amplifier are shown in FIG. 2 for convenience of description, since the semiconductor memory device typically includes a plurality of block sense amplifiers and a plurality of main sense amplifiers, the level comparator 50 includes: The generated first to third control signals G1 to G3 are applied to all main sense amplifiers to compensate for the resistance value change due to the process change.

As described above, the semiconductor memory device according to the present invention automatically compensates for a change in the resistance value of the main sense amplifier due to an unexpected process change or a corresponding condition change in the semiconductor process to compensate for the gain change of the main sense amplifier. This minimizes the change in memory chip characteristics due to increased sensing margins, currents, or speed delays.

Claims (3)

A memory cell array; A block sense amplifier for amplifying data read from the memory cell array to generate a sense data pair; A dummy block sense amplifier configured to receive a power supply voltage and generate the same dummy sense data pair at all times regardless of a read or write operation; A dummy main sense amplifier for differentially amplifying the dummy sense data pairs to generate dummy output data pairs; A reference voltage generator configured to generate a first reference voltage and a second reference voltage which are preset; A level comparator configured to generate a plurality of control signals by comparing the dummy output data pairs generated from the dummy main sense amplifier with the levels of the first and second reference voltages; First and second junction transistors each having a base to which the sense data pairs are applied one by one, and a first one connected to the collectors of the first and second junction transistors one by one to change resistance values according to the plurality of control signals. And a main sense amplifier configured to compensate for the change in the resistance value generated in the process by a second variable resistor part and to differentially amplify the sense data pair in the state where the change in the resistance value is compensated. A semiconductor memory device characterized by the above-mentioned. The method of claim 1, The first variable resistor unit A first resistor having one end to which a power supply voltage is applied; A second resistor having one end connected to the other end of the first resistor, A third resistor having one end connected to the other end of the second resistor, A first MOS transistor having a drain connected between the first and second resistors, a gate to which a first control signal from the level comparison unit is applied, and a source connected to a collector of the first junction transistor; A second MOS transistor having a drain connected between the second and third resistors, a gate to which a second control signal from the level comparison unit is applied, and a source connected to a source of the first MOS transistor; A third MOS transistor having a drain connected to the other end of the third resistor, a gate to which a third control signal from the level comparison unit is applied, and a source connected to the sources of the first and second MOS transistors, The second variable resistor unit A fourth resistor having one end to which a power supply voltage is applied; A fifth resistor having one end connected to the other end of the fourth resistor; A sixth resistor having one end connected to the other end of the fifth resistor; A fourth MOS transistor having a drain connected between the fourth and fifth resistors, a gate to which the first control signal is applied, and a source connected to a collector of the second junction transistor; A fifth MOS transistor having a drain connected between the fifth and sixth resistors, a gate to which the second control signal is applied, and a source connected to a source of the fourth MOS transistor; And a sixth MOS transistor having a drain connected to the other end of the sixth resistor, a gate to which the third control signal is applied, and a source connected to the sources of the fourth and fifth MOS transistors. Device. The method of claim 2, The level comparison unit If the voltage level of the dummy output data pair is higher than the level of the first reference voltage, only the first control signal is enabled to turn on the first and fourth MOS transistors, If the voltage level of the dummy output data pair is a level between the first and second reference voltages, only the second control signal is enabled to turn on the second and fifth MOS transistors, And when the voltage level of the dummy output data pair is lower than the level of the second reference voltage, only the third control signal to enable the third and sixth MOS transistors.

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