KR100427716B1 - A magnetic random access memory to use diode fabricated by MILC ( metal-induced lateral crystallization ) and a method for the same - Google Patents

Abstract

The present invention is M.I.L.C. (magnetic RAM, hereinafter referred to as MRAM) using metal-induced lateral crystallization (hereinafter referred to as MILC) and a method of forming the same, and a read / write operation ^{Since only 5} to 10 ⁶ times is limited to use, the word line is formed on the substrate and M.T.J. (magnetic tunnel junction, hereinafter referred to as MTJ) A cell is formed, a diode is formed on top of the MTJ cell by a MILC method and a bit line is formed thereon to form an MRAM cell, thereby forming a connection layer forming process and the thermal It is a technology that enables MTJ cell formation process after diode formation process without deterioration of characteristics, and stacks a large number of diode and MTJ cell connection pairs to enable high integration and simplicity of devices.

Description

A magnetic random access memory to use diode fabricated by MILC (metal-induced lateral crystallization) and a method for the same}

The present invention is M.I.L.C. (magnetic RAM, hereinafter referred to as MRAM) and its formation method, in particular diodes using metal-induced lateral crystallization (hereinafter referred to as MILC), and methods of forming the same. The present invention relates to a technology of having a characteristic of a nonvolatile memory such as a flash memory, but having a large number of diodes and a resistance change device connected to each other to increase the storage capacity thereof.

Most semiconductor memory manufacturers are developing MRAM using ferromagnetic materials as one of the next generation memory devices.

The MRAM is a memory device that reads and writes information by forming ferromagnetic thin films in multiple layers to sense current changes according to the magnetization direction of each thin film. The MRAM not only enables high speed, low power, and high integration, The device is capable of operating a nonvolatile memory such as a flash memory.

The MRAM has a method of implementing a memory device using a giant magnetoresistive (GMR) phenomenon or a spin polarization magnetic permeation phenomenon, which occurs because spin has a great effect on electron transfer.

In the MRAM using the giant magnetoresistance (GMR) phenomenon, the GMR magnetic memory device is implemented by using a phenomenon in which the resistance in the case where the spin directions are different in the two magnetic layers having a nonmagnetic layer therebetween is significantly different.

The MRAM using the spin polarization magnetic permeation phenomenon is a magnetic permeation junction memory device using a phenomenon that current permeation occurs much better than two cases in which the spin directions are the same in two magnetic layers having an insulating layer interposed therebetween.

However, the research on the MRAM is currently in an early stage, mainly focused on the formation of the multilayer magnetic thin film, and the research on the unit cell structure and the peripheral sensing circuit is still insufficient.

In general, the cell structure of the MRAM has a structure consisting of one transistor and one MTJ cell or one diode and one MTJ cell.

Since the structure consisting of the one diode and one MTJ cell requires a high temperature heat treatment process in the deposition process of the doped polysilicon to form the diode, the MRAM is formed by forming the diode and then forming the MTJ cell.

Here, when the diode is formed after the MTJ cell formation process, the MTJ cell is deteriorated due to a high temperature heat treatment process.

1 and 2 are a cross-sectional view and a plan view showing a magnetic ram according to an embodiment of the prior art, which is described with reference to US Patent Nos. 5,640,343 and 6,180,444. 2 is a plan view schematically illustrating an operation principle of an MRAM array.

Referring to FIG. 1, the MRAM includes a word line 13 provided with a semiconductor substrate 11, a diode 19 formed of an N / p impurity layer 15 and 17 on the word line 11, and The MTJ cell 25 provided above the diode 19 and the connection layer 21 for connecting the MTJ cell 25 and the diode 19 are provided.

Here, the method of forming the MRAM is as follows.

First, the word line 13 is formed on the semiconductor substrate 11, and the diode 19 is formed on the word line 13.

In this case, the diode 19 is formed of the N / type impurity layers 15 and 17. The impurity layers 15 and 17 are formed of doped polysilicon by ion implantation after deposition of a polysilicon layer, and a method of depositing a doped amorphous silicon layer and heat-treating it to crystallize the doped polysilicon layer. It was. .

However, when the ion implantation process is used, a subsequent high temperature heat treatment process is involved, and when the doped amorphous silicon layer is used, the characteristics of the MTJ cell are degraded at a temperature above a certain limit, thereby destroying the thermal stability of the MTJ cell. To form a connection layer and to perform the MTJ forming process accordingly. This makes the structure of the device complicated and makes high integration difficult.

Next, tungsten is formed by depositing the connection layer 21 and then planarized etching is performed. After the MTJ cell is deposited, the MTJ, the connection layer, and the diode are etched to form a first interlayer insulating film 23. Alternatively, as shown in FIG. 1, the deposition layer is etched and then etched to form a first interlayer dielectric layer 23. The planarization etch is performed until the tungsten connection layer 21 is exposed, and the MTJ 25 is deposited and etched. The method of forming the insulating film 27 is also possible.

In addition, the operation of the MRAM is as follows.

In the write operation of the MRAM, a magnetic field is formed by flowing a current of the bit line current I _B and the word line current I _W , but only a cell where I _B and I _W intersect is selected to perform a write operation.

In the read operation of the MRAM, when a voltage is applied to the bit line of the selected cell, current flows to the word line through the resistance of the MTJ cell and the PN junction diode, which is sensed and executed.

Referring to FIG. 2, a word line control circuit 31 having both ends of word line 1 33, word line 2 35, and word line 3 37 is provided. And bit line adjustment circuit 41 connected to both ends of bit line 1 43, bit line 2 45, and bit line 3 47 of the design crossing 3, 33, 35 and 37. It is. In particular, a unit cell including MTJ cells ⓑ and PN junction diodes ⓒ is provided at a portion where the word line and the bit line cross each other.

Here, the magnetic field is caused by the current flow of I _B which is the current flowing in the bit lines 1, 2, 3 (43, 45, 47) and I _{W which} is the current flowing in the word lines 1, 2, 3 (33, 35, 37). Is formed, and only a cell in which the currents of I _B and I _W intersect is selected to perform a write operation.

In addition, a read operation is performed by sensing current due to the difference between the voltage applied to the bit line of the selected cell and the reference voltage to the word line through the resistance of the MTJ cell and the diode. .

As described above, the magnetic RAM according to the related art forms a magnetic RAM using a single PN junction diode and an MTJ cell, which is a resistance change element, so that only two bits can be stored in one cell, thereby making it difficult to integrate the device. There is a problem, and since the connection layer must be formed to prevent deterioration of characteristics due to the high temperature heat treatment process that is involved in the manufacturing process of the device, there is a problem in that the structure of the device becomes complicated and thus high integration of the device is difficult.

The present invention to solve the problems of the prior art as described above, M.I.L.C. By using the metal-induced lateral crystallization (hereinafter referred to as MILC), the diode can be formed after the MTJ cell formation process by lowering the temperature used in the diode formation process so that a large number of diode-MTJ cell connection pairs can be stacked. The purpose of the present invention is to provide a magnetic ram using a diode using a MILC and a method of forming the same, thereby enabling high integration of the device.

For reference, the MILC is a thin layer of Pd, Ni, Cu or the like deposited on the N + or P + doped-amorphous Si to a thickness of 10 ~ 1000 Å and then heat-treated at low temperature heat treatment, usually 450 degrees Celsius or less to form poly-Si Say something.

1 is a cross-sectional view showing a magnetic ram according to an embodiment of the prior art

2 is a plan view showing the operation principle of the MRAM array;

3A to 3C are cross-sectional views showing a magnetic ram and a method of forming the same according to the first embodiment of the present invention.

4 is a sectional view showing a magnetic ram and a method of forming the same according to a second embodiment of the present invention;

5A and 5B are cross-sectional views illustrating a method of forming a magnetic ram according to a third embodiment of the present invention.

6 is a cross-sectional view showing a method of forming a magnetic ram according to a fourth embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

11,51,71,111,131: Semiconductor substrate 13,53,73,113,133: Word line

15,61: N + polysilicon layer 17,66: P + polysilicon layer

19,67: PN junction diode 21: connection layer

23,56,116,120,137: First interlayer insulating film 25,55,115: MTJ cell

27, 68, 122, 141: second interlayer insulating film 31: word line control circuit

33: word line 1 35: word line 2

37: word line 3 41: bit line adjustment circuit

43: bit line 1 45: bit line 2

47: bit line 3 57: N + amorphous silicon layer

59: first metal layer 63: P + amorphous silicon layer

65: second metal layer 69,123: bit line

73,133: first layer word line 75,135: first layer MTJ cell

77: first layer N + polysilicon layer 76,137: first layer first interlayer insulating film

78: first layer P + polysilicon layer 79: first layer PN junction diode

80,141: first layer and second interlayer insulating film 81,143: first layer, first bit line

83,145: First layer Third interlayer insulating film 97,147: Nth layer word line

99,149: n-th layer MTJ cell 100,151: n-th layer first interlayer insulating film

101: nth layer N + polysilicon layer 102: nth layer P + polysilicon layer

103: nth layer PN junction diode 104,155: nth layer second interlayer insulating film

105,157: nth layer bit line 107,159: nth layer third interlayer insulating film

117: doped amorphous silicon layer 119: metal layer

121: doped polysilicon layer

139: first layer doped polysilicon layer

153: nth layer doped polysilicon layer

Magnetic RAM using a diode using a MILC according to the present invention for achieving the above object,

A word line provided in the active region on the semiconductor substrate,

An MTJ cell provided above the word line;

A diode connected to the MTJ cell and formed and connected by a MILC method;

Consisting of a bit line connected to the diode,

The first feature of the diode is a PN junction diode or a Schottky diode.

In addition, the magnetic RAM used a diode using a MILC according to the present invention for achieving the above object,

Patterning the MTJ cell on the substrate on which the word line is formed;

Forming a planarized first interlayer insulating film exposing the MTJ cell;

Stacking an N + amorphous silicon layer connected to the MTJ cell and stacking a first metal layer thereon;

Performing a low temperature heat treatment of the N + amorphous silicon layer to crystallize into an N + polysilicon layer and removing the first metal layer;

Stacking a P + amorphous silicon layer on the N + polysilicon layer and forming a second metal layer thereon;

Performing a low temperature heat treatment of the P + amorphous silicon layer to crystallize it into a P + polysilicon layer and removing the second metal layer to form a PN junction diode;

Forming a planarized second interlayer insulating film exposing the PN junction diode;

Forming a bit line connected to the PN junction diode;

Forming a third interlayer insulating film to planarize the upper part of the bit line;

MRAM cells are formed by repeating the word line, the MTJ cell, the first interlayer insulating film, the doped polysilicon layer, the second interlayer insulating film, the bit line, and the third interlayer insulating film n times to form an MRAM cell. A second feature is that n MRAM cells are formed in one MRAM cell area by being connected to different wirings in the peripheral circuit part.

In addition, the method of forming a magnetic ram using a diode using a MILC according to the present invention to achieve the above object,

Patterning the MTJ cell on the substrate on which the word line is formed;

Forming a planarized first interlayer insulating film exposing the MTJ cell;

Stacking an N + amorphous silicon layer connected to the MTJ cell and stacking a first metal layer thereon;

Performing a low temperature heat treatment of the N + amorphous silicon layer to crystallize into an N + polysilicon layer and removing the first metal layer;

Stacking a P + amorphous silicon layer on the N + polysilicon layer and forming a second metal layer thereon;

Performing a low temperature heat treatment of the P + amorphous silicon layer to crystallize it into a P + polysilicon layer and removing the second metal layer to form a PN junction diode;

Forming a planarized second interlayer insulating film exposing the PN junction diode;

Forming a bit line connected to the PN junction diode;

Forming a third interlayer insulating film to planarize the upper part of the bit line;

The word line, the MTJ cell, the first interlayer insulating film, the PN junction diode, the second interlayer insulating film, the bit line, and the third interlayer insulating film are formed by repeating n times to form an MRAM cell.

Wherein the substrate is one of which is arbitrarily selected from a semiconductor substrate or a glass substrate is used,

The first metal layer and the second metal layer is formed of one selected from Pd, Ni or Cu,

The low temperature heat treatment step is carried out at a temperature of 100 ~ 450 ℃,

The low temperature heat treatment process is carried out at a temperature of 100 ~ 450 ℃, the first feature is to be carried out while applying an electric or magnetic field.

In addition, the method of forming a magnetic ram using a diode using a MILC according to the present invention to achieve the above object,

Patterning the MTJ cell on the substrate on which the word line is formed;

Forming a planarized first interlayer insulating film exposing the MTJ cell;

Forming a doped amorphous silicon layer connected to said MTJ cell,

Forming a metal layer on the doped amorphous silicon layer;

Performing a low temperature heat treatment of the doped amorphous silicon layer to crystallize the doped polysilicon layer and removing the metal layer;

Patterning the doped polysilicon layer to form a doped polysilicon layer pattern used as a Schottky diode;

Forming a planarized second interlayer insulating film exposing the doped polysilicon layer pattern;

Forming a bit line connected to said doped polysilicon layer,

Forming a third interlayer insulating film to planarize the upper part of the bit line;

MRAM cells are formed by repeating the word line, the MTJ cell, the first interlayer insulating film, the doped polysilicon layer, the second interlayer insulating film, the bit line, and the third interlayer insulating film n times to form an MRAM cell. N MRAM cells are formed in one MRAM cell area by being connected to different wirings in the peripheral circuit part.

The substrate may be any one selected from a semiconductor substrate or a glass substrate,

The first metal layer and the second metal layer is formed of one selected from Pd, Ni or Cu,

The low temperature heat treatment step is carried out at a temperature of 100 ~ 450 ℃,

The low temperature heat treatment step is a second feature that is performed by applying an electric or magnetic field at a temperature of 100 ~ 450 ℃.

On the other hand, in the prior art, the magnetic RAM composed of one diode and one resistance-transfer device has limited read / write operation by about 10 ⁵ to 10 ⁶ times, thereby limiting its use. Therefore, the principle of the present invention for improving the performance of the device is as follows.

The low temperature deposition of the doped polysilicon layer used as a diode to maintain the thermal stability of the MTJ by the MILC method to perform the MTJ cell formation process subsequent to the diode formation process, the word in one MTJ cell area Multiple stacked structures of lines, MTJ cells, diodes, and bit lines can be stacked, each of which acts as a unit cell of the MRAM, but is formed by forming an MRAM device having a three-dimensional structure so as to be connected and operated independently in a peripheral circuit portion. By forming a plurality of MRAM cells stacked in the MRAM cell region, the storage capacity of the device is improved and the device can be highly integrated.

In particular, it is possible to easily form a laminated structure by forming a diode without forming a MOS, and the manufacturing process of the device can be performed at a low temperature by the MILC method, so it is not only applied to a semiconductor substrate but also to a liquid crystal display (LCD) device It is also possible to use a substrate.

Here, the resistance change element is MTJ, AMR, GMR, spin valve, ferromagnetic / metal / semiconductor hybrid structure, III-V magnetic semiconductor composite structure, metal (metalloid) / semiconductor composite structure, CMR (Colossal) Magneto-Resistance) and the like is formed of a magnetoresistive element whose resistance value changes due to magnetization or magnetism, and a phase change element whose resistance value changes due to a material phase change by an electric signal.

Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

3 to 6 are cross-sectional views illustrating a method of forming a magnetic ram using a diode using MILC according to the first to fourth embodiments of the present invention.

3A to 3C are cross-sectional views illustrating a method of forming a magnetic ram according to a first embodiment of the present invention.

Referring to FIG. 3A, a word line 53 is formed on the semiconductor substrate 51.

The MTJ cell 55 is patterned on the word line.

In this case, the MTJ cell 55 is formed of a laminated structure of a fixed ferromagnetic layer (not shown), a tunnel oxide layer (not shown) and a free ferromagnetic layer (not shown), wherein the tunnel oxide layer is made of alumina (Al ₂ O ₃ ). The fixed ferromagnetic layer and the free ferromagnetic layer are formed using an alloy mainly composed of platinum (Pt), nickel (Ni), manganese (Mn), cobalt (Co), iron (Fe), and the like.

Next, a planarized first interlayer insulating film 56 exposing the MTJ cell 55 is formed.

In addition, an amorphous silicon layer (hereinafter, referred to as N + amorphous silicon layer) 57 doped with a high concentration of en-type impurities is formed on the MTJ cell 55.

In addition, a first metal layer 59 connected to the N + amorphous silicon layer 57 is formed. In this case, the first metal layer 59 is formed of a metal such as Pd, Ni, Cu, etc. to a thickness of 10 to 1000 mm 3.

Referring to FIG. 3B, the N + amorphous silicon layer 57 is annealed to crystallize into a polysilicon layer (hereinafter, referred to as an N + polysilicon layer) 61 doped with a high concentration of en-type impurities.

At this time, the annealing step is carried out at a temperature of 100 ~ 450 ℃.

In addition, in order to increase the mobility of the metal atoms in the annealing process may be carried out while applying an electric or magnetic field.

Next, the first metal layer 59 is removed, and an amorphous silicon layer (hereinafter referred to as P + amorphous silicon layer) 63 doped with a high concentration of impurities on the N + polysilicon layer 61 is formed. And a second metal layer 65 connected to the P + amorphous silicon layer 63. At this time, the second metal layer 65 is formed of a metal such as Pd, Ni, Cu, etc. to a thickness of 10 ~ 1000 Å.

Referring to FIG. 3C, the P + amorphous silicon layer 63 is annealed to crystallize the P + amorphous silicon layer 63 into a polysilicon layer (hereinafter referred to as P + polysilicon layer) 66 doped with a high concentration of impurities. Let's do it.

At this time, the annealing step is carried out at a temperature of 100 ~ 450 ℃.

In addition, in order to increase the mobility of the metal atoms in the annealing process may be carried out while applying an electric or magnetic field.

Next, the second metal layer 65 is removed, and the N + polysilicon layer 61 and the P + polysilicon layer 66 stacked structures are patterned to form a PN junction diode 67.

A planarized second interlayer insulating film 68 exposing the upper portion of the PN junction diode 67 is formed.

The word line 53, the MTJ cell 55, the PN junction diode 67 and the bit line are formed on the semiconductor substrate 51 by forming the bit line 69 connected to the second interlayer insulating layer 68. An MRAM cell provided with the stacked structure of 69 is formed.

In this case, the MTJ cell 55 is connected to an upper portion of the word line 53 where the word line 53 and the bit line 69 cross each other.

4 is a cross-sectional view illustrating a method of forming a magnetic ram using a diode using M.I.L.C according to a second embodiment of the present invention, wherein the magnetic ram is formed according to the first embodiment of the present invention. By using the method, a structure in which word lines, PN junction diodes, and bit lines are stacked is repeatedly formed.

Referring to Figure 4, the magnetic RAM

A first word line 73 is formed on the semiconductor substrate 71, and a first MTJ cell 75 is formed on the semiconductor substrate 71. Then, a planarized first interlayer insulating layer 76 is formed to expose the first MTJ cell 75. A first PN junction diode 79 connected to 75 is formed by a MILC method, and then a planarized second interlayer insulating film 80 exposing it is formed and connected to the first PN junction diode 79; The first word line 73, the first MTJ cell 75, connected to the semiconductor substrate 71 by forming the first bit line 81 and then forming a third interlayer insulating film 83 to planarize the upper portion thereof. A stacked structure of the first PN junction diode 79 and the first bit line 81 is formed.

Next, the first word line 73, the first MTJ cell 75, the first interlayer insulating layer 76, the first PN junction diode 79, and the second interlayer insulating layer are formed on the third interlayer insulating layer 83. (80), the first bit line 81 and the third interlayer insulating film 83 are formed in order to form an MRAM having a stacked structure repeated n times.

Here, the elements forming the first stacked structure to the nth stacked structure are connected to each other by metal wirings in the peripheral circuit portion, and are stacked in one cell area and operated with n MRAM cells.

5A and 5B are cross-sectional views illustrating a method of forming a magnetic RAM using a diode using M.I.C.C according to a third embodiment of the present invention. Sectional view of the ram.

Referring to Figure 5a, the magnetic ram

The word line 113 connected to the semiconductor substrate 111 is formed and the MTJ cell 115 is formed thereon. In this case, the MTJ cell 115 is formed by patterning a portion where the word line 113 and a bit line to be formed in a subsequent process intersect. The MTJ cell 115 is formed of a laminated structure of a fixed ferromagnetic layer (not shown), a tunnel oxide layer (not shown), and a free ferromagnetic layer (not shown), wherein the tunnel oxide layer is made of alumina (Al ₂ O ₃ ). The ferromagnetic layer and the free ferromagnetic layer are formed using an alloy mainly composed of platinum (Pt), nickel (Ni), manganese (Mn), cobalt (Co), iron (Fe), and the like.

Next, a planarized first interlayer insulating film 116 exposing the MTJ cell 115 is formed.

In addition, a doped amorphous silicon layer 117 connected to the MTJ cell 115 is formed.

Then, a metal layer 119 is formed thereon. In this case, the metal layer 119 is formed of a metal such as Pd, Ni, Cu, etc. to a thickness of 10 ~ 1000 1000.

Referring to FIG. 5B, the doped amorphous silicon layer 117 is subjected to low temperature heat treatment to crystallize the doped polysilicon layer 121.

At this time, the low temperature heat treatment step is carried out at a temperature of 100 ~ 450 ℃.

In addition, in order to increase the mobility of the metal atoms in the annealing process may be carried out while applying an electric or magnetic field.

Next, the metal layer 119 is removed and the doped polysilicon layer 121 is patterned to form a doped polysilicon layer 121 pattern used as a Schottky diode.

In addition, a planarized second interlayer insulating layer 122 exposing the doped polysilicon layer 121 pattern is formed.

The doped poly used as the word line 113, the MTJ cell 115, and the Schottky diode is formed on the semiconductor substrate 111 by forming the bit line 123 connected to the doped polysilicon layer 121. An MRAM having a stacked structure of a silicon layer 121 and a bit line is formed.

FIG. 6 is a cross-sectional view illustrating a method of forming a magnetic RAM using a diode using M.I.C.C according to a fourth embodiment of the present invention, wherein the cell structures formed by the processes of FIGS. 5A and 5B are stacked. It is formed.

Referring to Figure 6, the magnetic ram

A first word line 133 is formed on the semiconductor substrate 131, a first MTJ cell 135 is formed on the semiconductor substrate 131, and then a planarized first interlayer insulating layer 137 is formed to expose the first MTJ cell 135. A first doped polysilicon layer 139 to be used as a Schottky diode connected to the 135 is formed by a MILC method, and then a planarized second interlayer insulating film 141 is formed to expose the first doped polysilicon layer 141. The first word line 133 connected to the semiconductor substrate 131 is formed by forming a first bit line 143 connected to the silicon layer 139 and then forming a third interlayer insulating layer 145 to planarize an upper portion thereof. ), A first MTJ cell 135, a first doped polysilicon layer 139, and a first bit line 143 are formed.

Next, a first word line 133, a first MTJ cell 135, a first interlayer insulating layer 137, a first doped polysilicon layer 139, and a second interlayer are disposed on the third interlayer insulating layer 145. The process of forming the insulating film 141, the first bit line 143, and the third interlayer insulating film 145 is repeatedly performed n times in order to form a multi-layer MRAM.

Here, the elements forming the first stacked structure to the nth stacked structure are connected to each other by metal wirings in the peripheral circuit portion, and are stacked in one cell area and operated with n MRAM cells.

Another embodiment of the present invention provides a doped polysilicon layer used as a MILC formed PN junction diode and a Schottky diode according to the first, second, third, fourth embodiments of the present invention, as well as between the MTJ cell and the bit line. It is also formed between the word line and the word line.

In addition, since the present invention is formed using the MILC method, a glass substrate applied to a liquid crystal display (LCD) device may be used instead of the semiconductor substrate.

As described above, the magnetic ram using the diode using M.I.L.C and the method for forming the same according to the present invention are easily subjected to a low temperature heat treatment process using the MILC method, thereby providing a PN junction diode without a connection layer. Alternatively, the Schottky diode can be formed on top of the MTJ to form a multi-layered MRAM cell driven by a separate circuit, thereby enabling high integration of the device and simplifying the device.

Claims (13)

A word line provided in the active region on the semiconductor substrate, An MTJ cell provided above the word line; A diode connected to the MTJ cell and formed and connected by a MILC method; Magnetic RAM using a diode using a MILC, characterized in that consisting of a bit line connected to the diode. The method of claim 1, Magnetic diode using a diode using a MILC, characterized in that the diode is a PN junction diode or a Schottky diode. Patterning the MTJ cell on the substrate on which the word line is formed; Forming a planarized first interlayer insulating film exposing the MTJ cell; Stacking an N + amorphous silicon layer connected to the MTJ cell and stacking a first metal layer thereon; Performing a low temperature heat treatment of the N + amorphous silicon layer to crystallize into an N + polysilicon layer and removing the first metal layer; Stacking a P + amorphous silicon layer on the N + polysilicon layer and forming a second metal layer thereon; Performing a low temperature heat treatment of the P + amorphous silicon layer to crystallize it into a P + polysilicon layer and removing the second metal layer to form a PN junction diode; Forming a planarized second interlayer insulating film exposing the PN junction diode; Forming a bit line connected to the PN junction diode; Forming a third interlayer insulating film to planarize the upper part of the bit line; The process of forming the word line, the MTJ cell, the first interlayer insulating film, the PN junction diode, the second interlayer insulating film, the bit line, and the third interlayer insulating film is repeated n times to form an MRAM cell. The method of forming a magnetic RAM using a diode using a MILC, characterized in that n MRAM cells are connected to different wirings in one MRAM cell region. The method of claim 3, wherein The substrate is a method of forming a magnetic ram using a diode using a MILC, characterized in that any one of a semiconductor substrate or a glass substrate is arbitrarily selected. The method of claim 3, wherein The first metal layer and the second metal layer is a method of forming a magnetic RAM using a diode using a MILC, characterized in that formed by one selected from Pd, Ni or Cu. The method of claim 3, wherein The low temperature heat treatment process is a method of forming a magnetic ram using a diode using a MILC, characterized in that carried out at a temperature of 100 ~ 450 ℃. The method of claim 3, wherein The low temperature heat treatment process is carried out at a temperature of 100 ~ 450 ℃, the method of forming a magnetic ram using a diode using a MILC, characterized in that performed by applying an electric or magnetic field. A magnetic ram formed by the method of claim 3. Patterning the MTJ cell on the substrate on which the word line is formed; Forming a planarized first interlayer insulating film exposing the MTJ cell; Forming a doped amorphous silicon layer connected to said MTJ cell, Forming a metal layer on the doped amorphous silicon layer; Performing a low temperature heat treatment of the doped amorphous silicon layer to crystallize the doped polysilicon layer and removing the metal layer; Patterning the doped polysilicon layer to form a doped polysilicon layer pattern used as a Schottky diode; Forming a planarized second interlayer insulating film exposing the doped polysilicon layer pattern; Forming a bit line connected to said doped polysilicon layer, Forming a third interlayer insulating film to planarize the upper part of the bit line; MRAM cells are formed by repeating the word line, the MTJ cell, the first interlayer insulating film, the doped polysilicon layer, the second interlayer insulating film, the bit line, and the third interlayer insulating film n times to form an MRAM cell. A method of forming a magnetic RAM using a diode using a MILC, wherein n MRAM cells are formed in one MRAM cell area by being connected to different wirings in a peripheral circuit part. The method of claim 9, The substrate is a method of forming a magnetic RAM using a diode using a MILC, characterized in that any one of a semiconductor substrate or a glass substrate is used. The method of claim 9, The first metal layer and the second metal layer is a method of forming a magnetic RAM using a diode using a MILC, characterized in that formed by one selected from Pd, Ni or Cu. The method of claim 9, The low temperature heat treatment process is a method of forming a magnetic ram using a diode using a MILC, characterized in that carried out at a temperature of 100 ~ 450 ℃. The method of claim 9, The low temperature heat treatment process is a method of forming a magnetic ram using a diode using a MILC, characterized in that performed by applying an electric or magnetic field at a temperature of 100 ~ 450 ℃.