KR100425956B1 - SEED Cipher and Decipher using on-the-fly pre-claculation schme of round key - Google Patents

Abstract

The present invention relates to a method and apparatus for implementing a symmetric encryption algorithm SEED encryption and decryption algorithm in hardware. The present invention relates to a 128-bit input register, key register, encryption and A round key generation unit for generating a round key required for the decoding operation by online precomputation, a round processing unit for performing a round operation, a control unit for generating a control signal, and an output register for storing a 128-bit output result.

According to the present invention, it is possible to reduce the amount of hardware and achieve high-speed operation by maximizing hardware sharing during encryption / decryption operations, by splitting a single round operation into three symmetric partial rounds, and performing online precomputation of a round key, pipeline calculation of a round key. It can be effective.

Description

SEED Cipher and Decipher using on-the-fly pre-claculation schme of round key}

The present invention relates to a SEED encryption and decryption circuit using a round key calculation method during operation, and to provide an efficient seed circuit in terms of hardware size and operation speed for application in electronic commerce, smart card and network fields. More specifically, it relates to the hardware implementation of the SEED cryptographic algorithm, in particular splitting the round operation of the SEED encryption and decryption algorithm into three symmetric partial rounds, pipelined round keys, and sharing of hardware during cryptographic and decryption operations. SEED encryption and decryption using an on-the-fly round-key calculation scheme and an on-the-fly round-key on-line precomputation scheme that improves speed by using pre-computing techniques. It is about a circuit.

The hardware implementation of the conventional SEED cryptographic algorithm implements one round operation in one clock cycle, and includes round key calculations in the round operation, which makes it impossible to share hardware, which requires a lot of hardware and slows down the operation speed. There is this.

In addition, the other type of conventional method uses a technique of calculating 16 round keys before starting encryption and decryption operations to solve the operation speed problem caused by the round key calculation. This technique has the drawback of requiring 16 separate 64-bit registers to hold 16 round keys.

In order to apply the SEED encryption algorithm to the field of electronic commerce, network and smart card, it is required to guarantee the proper operation speed while minimizing the amount of hardware.

Accordingly, in the present invention, in order to solve many hardware problems of the conventional method, three partial round processing of the round operation in the hardware implementation of the SEED encryption and decryption algorithm, pipeline calculation of the round key, and use of the same hardware in the encryption and decryption operation, etc. Minimize the amount of hardware by maximizing hardware sharing. In order to solve the problem of low operation speed of the conventional method, the present invention proposes a method using a combination of the online calculation of the round key and the round key precomputation technique required for the encryption and decryption operation.

1 is a block diagram showing the structure of the entire system of the present invention.

2 is a scheme for implementing one round operation of the SEED encryption algorithm into three partial rounds.

3 is a scheme for precomputing round keys.

Figure 4 illustrates a pipeline calculation technique using three clocks with round keys.

5 is a round processing block diagram

6 is a block diagram of a round key generation unit

7 illustrates a decryption operation round key generation technique.

8 is a control circuit block diagram

■ Explanation of symbols used in main part of drawing ■

10: input register to store password and decrypted data

11: round processing unit for implementing one round of SEED encryption and decryption algorithm

12: output register to store password and decrypted result

13: master key register

14: round key generation unit

15: control unit for generating a control signal

16: L register to store the upper 64 bits of the round operation input

17: R register to store the lower 64 bits of the round operation input

18: 32 bit exclusive-OR circuit

19: G function

20: 32-bit Modular Adder

21: L * register to store the top 64 bits of the round operation result

22: R * register to store the lower 64 bits of the round operation result

23: Adjusted master key register for round key calculation {D, C, B, A}

24: 32-bit multiplexer circuit

25: 3 Input Carry Preservation Adder

26: pipeline register

29: G function

30: round key register

31: 32-bit multiplexer

31: 32-bit exclusive-OR circuit

32: 32-bit multiplexer

33: G function

34: 32-bit Modular Adder

35: Save intermediate result of round operation L register (L1, L0)

36: Save intermediate result of round operation T register (T1, T0)

37: Save intermediate result of round operation R register (R1, R0)

38: 32-bit multiplexer

39: 32-bit multiplexer to select initial alignment value when decoding

40: circuit that receives two 32-bit data and moves it left or right

41: 3 Input Carry Preservation Adder

42: Carry Forward Adder

43: pipeline register

44: G function

45: round key register

46: Adjusted master key register to store the traversal movement value of the master key

48: 1 bit left circuit

49: 1 bit right circuit

50: 15 bit left circuit

51: key constant register to store round key constants

52: Finite State Machine

53: command decoder for generating a control signal

54: round counter

55: key counter

Hereinafter, the configuration and operation of the SEED encryption and decryption circuit of the present invention for achieving the above object will be described in detail with reference to the accompanying drawings.

1 is an overall block diagram of a SEED encryption and decryption circuit according to the present invention.

Referring to FIG. 1, the entire SEED encryption and decryption circuit includes an input register 10 and a master key register 13 for storing external data and a key, and a control unit for receiving an operation mode and a start signal to generate necessary control signals ( 15), a round key generation unit 14 for generating a round key for encryption and decryption operations online and a precomputation technique, and a round processing unit 11 for implementing 16 round operations of the SEED encryption algorithm, and storing result values. It consists of an output register 12.

2 illustrates a technique of dividing one round operation of the SEED algorithm into three partial rounds. The SEED encryption and decryption algorithm repeats the round operation of FIG. 16 six times to generate an encryption or decryption result. However, in the case of the decoding operation, the application order of the round keys is reversed.

Referring to FIG. 2, in the case where FIG. 2 is implemented as a single clock as in the conventional method, since hardware sharing of the G function 19 and the modulo 32-bit adder 20, which exist in three pairs, is impossible, a lot of hardware is used. Is needed.

In FIG. 2, the G function 19 and the modulo 32-bit adder 20 exist one by one in each sub round. Accordingly, the present invention uses a method of dividing one round operation into three partial rounds according to a dotted line and implementing each partial round operation with one clock.

However, in order to maximize the hardware similarity of the three partial rounds, the upper 32 bits and the lower 32 bits of the partial round result are changed and stored. In this case, since one pair of G functions and a modulo 32-bit adder are required in one round implementation of FIG. 2, the hardware is reduced by about one third compared to the conventional method. In addition, as shown in FIG. 3, the round key calculation, which requires a lot of computation time, is calculated using an online technique using three clocks of the previous round.

4 illustrates a technique for implementing the round key precomputation of FIG. 3 in a pipelined manner. The conventional round key calculation requires two G functions and four modules with a 32-bit adder, which creates many hardware and speed problems.

According to the present invention, the round key (K _i , 0, K _i , 1) is calculated in a pipelined manner that allows hardware sharing by utilizing three clock cycles for round key calculation according to the round key precomputing technique. do. In the first clock cycle of the round operation, using the carry preservation adder 25 and the carry transfer adder 26, the calculation of A + C-KC is performed and stored in the pipeline register 27, in the second clock cycle. In pipeline stage 2, the round key Ki, 0 is calculated by calculating the G function 28 using the pipeline register value (A + C-KC) as input.In pipeline stage 1, B + KC-D is calculated. This is done and stored in the pipeline register 27. In the final third cycle, the round key Ki, 1 calculation is performed by calculating the G function 28 in pipeline stage 2.

Since the round key calculation operation is performed at the round point before the round operation as shown in FIG. 3, the round key calculation can be excluded from the worst operation path, thereby enabling high operating frequency.

In pipeline stage 1, instead of using two mod 32-bit adders, the speed of operation is approximately doubled by using one 3-input carry preservation adder and one mod 32-bit adder.

FIG. 5 illustrates a round processor that implements the technique of FIG. 2 in hardware. Referring to FIG. 5, in the partial round 1, the Lx 35 and R37 register values storing the input data value or the intermediate round value connected to the input register of FIG. And then combine with the round keys (Ki, 0, Ki, 1) at the 32-bit XOR gate 31, then through the G function 33 and modulo 32-bit adder 34, the intermediate result registers T1, T0 36). In partial round 2, the intermediate result register values (T1, T0) 36 are selected by the multiplexer 32, again via the G function 33 and the modulo 32-bit adder 34, again to the intermediate result register ( T1, T0) (36). In the partial round 3, the intermediate result register values (T1, T0) 36 are selected by the multiplexer 32, and after passing through the G function 33 and the modulo 32-bit adder 34, the L register ( 35) and then stored in the R register 37. At the same time, the R registers R1 and R0 37 are contained in the L registers L1 and L0 35. This operation is repeated for sixteen rounds, and after the sixteenth round operation, the values of the L register 35 and the R register 37 are shifted from each other and stored in the output register 12 of FIG.

6 is an online encryption and decryption round key generation circuit employing the round key generation scheme of FIG. However, it maximizes hardware sharing during encryption and decryption round key generation. Unlike the encryption round key generation, the decryption round key generation is implemented in the manner of FIG.

Referring to FIG. 7, the round key generation for the decryption operation is different in three aspects from the round key generation method of the encryption operation.

First, the modified value 55 of the master key rather than the master key is used as the input value for the decryption round 1.

Second, the traversal direction of movement used to determine the adjusted key values {D, C, B, A} used to generate the round key is the opposite of the cryptographic operation.

Third, the sequence of generating key constants is the reverse of the round key of the cryptographic operation. Referring to FIG. 6 in which the decryption round key scheme and the cryptographic round key generation scheme of FIG. 7 are implemented in hardware, the input multiplexer 38 includes a master key and adjusted master key values {D, C, B, A} ( 46) to select. Four 64-bit left and right traversing mobiles 40 serve to generate the adjusted master key required for encryption and decryption, and to generate the decryption operation initial alignment operation values of FIG. {B || A} (40) represents the operation of concatenating two 32-bit data to produce 64-bit data. However, this circuit is implemented by fixed wiring without using a separate barrel shifter. However, in the decoding operation, as shown in FIG. 7, since the round key calculation for the first round requires the value of the right shift 55 of the upper 64 bits of the master key, not the master key, the multiplexer 39 is used. Selects the initial sorted value. Since the key constant in decryption must also be generated as opposed to the cryptographic operation, one-bit left or right traversal mobile circuits 48 and 49 are used to generate the key constant (KC) in an online manner to implement this.

However, since the initial key constant is not KC ₀ but KC ₁₅ is used for decoding, the 15-bit left traversal port 50 is used. The key constants generated in the online manner used for round key calculations are held in the key constant register 51.

8 shows a block diagram of a control circuit for implementing the SEED encryption and decryption operation. Since the round key calculation is made one round before the normal round operation, two counters indicating round progression, that is, round counter 54 and key counter 55, are used. The finite state machine 52 receives an operation mode and a start signal to determine state values for SEED encryption and decryption operations. Using the state value generated by the finite state and the two counter values, the command decoder 53 generates control signals necessary for the round processing section and the round key generation section in FIG.

As described in detail above, the present invention enables the round key calculation operation to be twice as fast as the conventional method by excluding the calculation operation of the round key from the worst path of the SEED encryption and decryption operation.

In addition, since hardware sharing is possible by splitting the round key pipeline processing and the first round operation into three partial rounds, the hardware size is reduced by about one third compared to the conventional method.

The initial 64 bits of the master key, the master key (D, C, B, A) traversal method in the opposite direction to the encryption operation, and the online key constant generation method, Maximized sharing of online round key generation hardware.

Claims (6)

SEED's round key generation operation (K _{i, 0} = G (A + B-KC), K _{i, l} = G (B + KC-B) consists of one carry preservation adder and one 32-bit modular adder Pipeline Phase 1, which implements 3-Operland addition, and Pipeline Phase 2, which consists of G blocks, to generate a round key for the previous round with an on-the-fly technique at 3 clocks. SEED encryption and decryption circuit using heavy round key calculation. The method of claim 1; A decoded round key generation circuit of FIG. 7 through initial right traversal of the upper 64 bits of the master key, cryptographic control of the adjusted master key (D, C, B, A) and traversal in the opposite direction SEED encryption and decryption circuit using ongoing round key calculation. delete delete delete delete