KR100209884B1 - High speed selection reproducing apparatus and method providing multi-output - Google Patents

Abstract

The present invention provides a high-speed sorting and reproducing apparatus capable of simultaneously listening to two languages simultaneously as well as fast searching and sorting reproduction of a desired section in a reproducing apparatus such as a language learner using a digital recording medium such as a CD or an IC card. It is about a method. The present invention divides a digital recording medium into a plurality of virtual tracks consisting of a plurality of segment areas, and separately records English, Japanese, German, Korean, and the like for each segment area within the virtual track. When data of a segment area in an arbitrary virtual track is selected by the user's key operation, data is continuously read from the recording medium at the head of the virtual track and stored in the memory. Then, the desired data can be accessed and played back from the memory, and data of a plurality of segment areas can be selected and played back so that two languages such as English and Korean can be listened to at the same time.

Description

High speed sorting and reproducing apparatus capable of multiple outputs and method thereof

FIG. 1 (a) is a diagram for explaining the recording format of a digital recording medium according to the present invention, and FIG. 1 (b) is a diagram for explaining the recording format of a TOC (Table Of Contents) area.

2 is a block diagram showing a high-speed sorting and reproducing apparatus capable of multiple outputs according to the present invention when using a CD (Compact Disk) as a recording medium.

3 is a block diagram showing a high-speed sorting and reproducing apparatus capable of multiple outputs according to the present invention when an IC card is used as a recording medium.

4 is a detailed view of a memory unit in the apparatus of FIGS. 2 to 3;

5 and 6 are operation timing diagrams for the respective components in the memory unit of FIG.

7 (a)-(c) are diagrams for explaining a data access process in the main memory of the memory section of FIG.

* Explanation of symbols for main parts of the drawings

11: CD 14: memory

15: data expansion unit 16: data output unit

17: key control unit 18: system control unit

21: IC card 41: buffer memory

42: read / write controller 43: main memory

44: input / output 45: data selector

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital recording medium reproducing system such as a CD or an IC card. In particular, the present invention is applied to a language learner or the like to individually select and reproduce a plurality of desired languages among multilingual languages recorded on a recording medium, and to search for desired contents at high speed. The present invention relates to a high-speed sorting and reproducing apparatus capable of multiple outputs capable of reproduction, and a method thereof.

Most of the commercially available devices as language learners use tape as a recording medium. However, when using a tape, you have to wait while winding the tape back and forth when specifying a specific section, and it is difficult to reach the desired part accurately. On the other hand, if multiple languages such as English and Korean are recorded on a track of a tape (for example, I am a boy, I am a boy), it is difficult to separate the recorded languages and select only one language.

Accordingly, an object of the present invention is to solve the above-mentioned problems and to search a desired section accurately at high speed, and to form an arbitrary virtual track on a recording medium so that a specific language can be selected and heard, and a plurality of segments in the virtual track. (Segment) is formed to record data for each segment area, and the data for each segment area is stored in the memory, and high-speed selective playback capable of multiple outputs to selectively reproduce desired recording contents by accessing the memory without accessing the recording medium. In providing a method.

Another object of the present invention is to provide an apparatus for implementing the above-described high speed selective playback method capable of multiple outputs.

In order to achieve the above objects, a multi-output high speed sorting reproducing method of the present invention is a method of reproducing using a digital recording medium. The digital recording medium is divided into a TOC area and a data area, and a plurality of data areas are included. A first step of dividing a plurality of virtual tracks into segment regions to record data for each segment region in each virtual track, wherein the TOC region defines a start address for each segment region in the virtual track and a pointer of the start address; A second virtual step of selecting at least one segment area to be reproduced in the virtual track on the first step of the digital recording medium; and an arbitrary virtual step including a part selected in the second step by using information defined in the TOC area. Read data of segment area in track one by one And a fourth step of reading data of the segment area in the random virtual track stored in the third step, and selecting data of the segment area corresponding to the portion selected in the second step, and the fourth step. And a fifth step of restoring and restoring the data selected in the original.

In order to achieve another object of the present invention, a multi-output high speed sorting and reproducing apparatus of the present invention is a reproducing apparatus using a digital recording medium, comprising a plurality of virtual tracks composed of a plurality of segment regions, and segmenting in a virtual track. A digital recording medium for recording data for each area, a key control unit, a system control unit for controlling the overall operation of each component in accordance with a key operation signal of the key control unit, and an arbitrary first of the digital recording medium under control of the system control unit A memory unit for reading data of the segment area in the virtual track and storing the data for each area and reading data of the segment area in the virtual track among the stored area data, and data read from the memory unit under the control of the system controller; Data to select and output at least one desired data among them Selector, and means for outputting the reproduced restored as the selected data from the data selector.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 (a) is a diagram for explaining the recording format of the digital recording medium according to the present invention, and FIG. 1 (b) is a diagram for explaining the recording format of the TOC area.

In FIG. 1 (a), the digital recording medium is largely divided into two areas, a TOC area for managing data and a data area in which actual data exists. The TOC area is the same as the first diagram (b), and the data area divides the start point S to the end point E into arbitrary virtual tracks, and the virtual tracks are divided into four segments A, B, C, and D. Separate into areas. Here, 1000 virtual tracks (1track to 1000track) are divided, and the four segment areas in the virtual tracks are the same size and each address is given. In addition, data can be recorded for each of four segment areas in 1000 virtual tracks. For example, in the 1000 virtual tracks, A segment areas A1 to A1000 are English, B segment areas B1 to B1000 are Japanese, C segment areas C1 to C1000 are German, and D segment areas D1 to D1000. ), Korean, etc. can be recorded.

Meanwhile, in FIG. 1 (b), the TOC area is largely divided into two areas, which are areas that define start addresses of segment areas in the virtual track and points of the start address definition area. In other words, A1 track start address on the recording medium and D1000 track start address are each defined as 4 bytes, and 1 track start address in the TOC area is defined (1track start). Defines 1 byte from address pointer) to the point where 1000 track start address is defined (1000track start address pointer).

2 is a block diagram showing a high speed sorting and reproducing apparatus capable of multiple outputs according to the present invention in the case of using a CD as a recording medium. As shown in the drawing, the reproducing apparatus of the present invention includes a CD 11, which is a digital recording medium having a structure as shown in Figs. 1 (a)-(b), and a pickup section 12 for reading data from the CD 11; And a digital signal processor (DSP) 13 for extracting only pure data from the read data. The DSP 13 stores a memory section 14 for storing data and reading the stored data, a data expansion section 15 for decompressing and restoring the data read out from the memory section 14, and restoring data. The data output section 16 to be output is connected in sequence. The reproducing apparatus of the present invention also controls not only the overall operation of each component in accordance with the key operation unit 17 and the key operation signal of the key operation unit 17, but also a system for controlling data reading and writing of the memory unit 14. It is configured to have a control unit 18.

3 is a block diagram showing a high-speed sorting and reproducing apparatus capable of multiple outputs according to the present invention when an IC card is used as a recording medium. As shown, the configuration is substantially the same as that in FIG. 2 and uses the IC card 21 instead of the CD 11 only, and includes a connector 22 for connecting the IC card 21 and the main body. Here, the same reference numerals are used for the same components as those in FIG.

The operation of the high-speed sorting and reproducing apparatus of the present invention configured as described above will be described in more detail with reference to FIGS. 4 to 7.

First, in the initial stage of reproduction according to the key operation of the key operation unit 17, the system control unit 18 records the TOC area from the CD 11 or the IC card 21 having the structure as shown in the first (a) to (b). Read the contents. The user selects a part to be played back through the key manipulation of the key manipulation section 17. For example, when the user selects the recording contents of the 100th virtual track, the system controller 18 which receives the key operation signal searches for the TOC area of FIG. First, find the 100th virtual track start address defined as 1 byte in the TOC area, and then find the A100 track start address defined as 4 bytes at that point in the TOC area. The system control unit 18 drives the pickup unit 12 or directly assigns an address to the A100, B100, C100 and D100 segments of the 100th virtual track stored at the start address of the CD 11 or the IC card 21. Read area data in order. In the case of reading from the CD 11, digital signal processing is carried out through the DSP 13, and only pure data is taken out and output to the memory unit 14. When reading from the IC card 21, the memory 22 is directly input to the memory 14 via the connector 22. Here, the memory unit 14 is configured as shown in FIG.

4 is a detailed view of the memory unit 14 in the apparatus of FIGS. 2 to 3. As shown, the memory unit 14 includes a buffer memory 41 comprising four buffers 41A to 41D for storing input data X from an arbitrary virtual track for each segment area, and the system controller 18. A plurality of logical AND elements AND1 to AND6, OR1 to OR5, and inverter INV1 for generating the read and write clocks by receiving the clock signals clk1 and clk2 and the read and write signals. A read / write controller 42 is provided. Between the buffer memory 41 and the read / write controller 42, the data of the segment area in the random virtual track read from the buffers 41A to 41D of the buffer memory 41 is read by the read / write controller 42. The main memory 43, which consists of four memories 43A to 43D, which are stored and read out in accordance with a clock and a write clock, is connected. Between the buffers 41A to 41D of the buffer memory 41 and the memories 43A to 43D of the main memory 43, a plurality of three-phase buffers and an inbuffer INV2 are provided to prevent data collision. The input / output unit 44 is connected. The input / output unit 44 includes a data selector including two multiplexers 45A and 45B for selectively outputting data read from the memories 43A to 43D of the main memory 43 under the control of the system controller 18. 45) is configured to be connected.

In FIG. 4, the input data X is simultaneously input to the buffers 41A to 41D of the buffer memory 41, and the buffers 41A to 41D are read / write controllers 42 and the system controller 18. According to the control of the corresponding segment area of the input data (X) stores only data. Here, the operation timings shown in FIGS. 5 and 6 will be described in more detail.

First, when the input data X is data of the A, B, C, and D segment areas in the 100th virtual track as shown in FIG. 5 (a), the system controller 18 uses the read / write controller 42 as the fifth data. The first clock signal clk1 as shown in (b) and the clock enable signal as shown by? to? in FIG. 5 (c) are output. In the read / write controller 42, the logical multipliers AND1 to AND4 are commonly inputted with the first clock signal clk1 in FIG. 5 (b), and the clock enable of? -④ in FIG. 5 (c). Each of the signals is input and logically operated to generate a valid write clock such as & tilde & The valid write clocks in the times of? (?) Of FIG. 5 (d) are input to the corresponding buffers 41A to 41D in the buffer memory 41 through the logic oligomers OR1 to OR4. Thus, the buffers 41A to 41D sequentially store the data of the corresponding segment area among the input data X. At this time, the system controller 18 assigns addresses to the buffers 41A to 41D through a common address bus. On the other hand, if the data of the A, B, C, and D segment areas in the 100th virtual track are all stored in the buffers 41A to 41D, the data of the A, B, C, and D segment areas in the 101st virtual track are buffer memory. The data of the A, B, C, and D segment areas in the 100th virtual track stored before the input to (41) are simultaneously read quickly. To this end, the system controller 18 is connected to the read / write controller 42 and the second clock signal clk2 as shown in FIG. 5 (e) having a period of half a period of the first clock signal clk1 of FIG. 5 (b). A clock enable signal as shown in? Of FIG. 5 (f) is output. The logical AND element AND6 of the read / write controller 42 is the clock enable signal and the clock enable signal of (6) of FIG. 5 (g) which inverted the clock enable signal of (5) of FIG. 5 (f) through the inverter INV1. An effective read clock is generated by performing an AND operation on the first clock signal clk2 of FIG. 5 (f). This is simultaneously input to the buffers 41A to 41D in the buffer memory 41 through the logic oligomers OR1 to OR4. Therefore, the buffers 41A to 41D simultaneously output data of the A, B, C, and D segment areas in the 100th virtual track stored as shown in ⑦ to 의 of FIG. 5 (h) according to the valid read clock input. do. The data of 7 to 9 of FIG. 5 (h) are input to corresponding three-phase buffers of the input / output unit 44. The input / output unit 44 applies an input / output control signal such as ⓐ in FIG. 5 (i) applied from the system controller 18 to four three-phase buffers connected to the output side of the main memory 43, and the fifth ( i) the input / output control signal of ⓐ in Fig. 4 is inverted through the inverter INV2 and four three-phase buffers connected to the output side of the buffer memory 41 and four three-phase buffers connected to the input side of the main memory 43. To prevent collision between data input and output. Here, the valid read clock is also input as a valid write clock to the memories 43A to 43D in the main memory 43 through the logical sum element OR5. Thus, the data of 7 to 9 of FIG. 5 (h) read from the buffers 41A to 41D of the buffer memory 41 are stored in the main memory 43 through the enabled three-phase buffers of the input / output 44. The memory is input to and stored in the corresponding memories 43A to 43D. At this time, the system controller 18 assigns addresses to the memories 43A to 43D in the main memory 43 through a common address bus. As such, after reading the data stored in the buffers 41A to 41D during the half cycle of the second clock signal clk2 of FIG. 5 (e) and storing the data in the memories 43A to 43D, the system control unit 18 passes the half cycle. Outputs the clock enable signal (5) of the first clock signal (clk1) and fifth (f) as shown in FIG. 5 (j) to the read / write controller 42. FIG. The AND product AND5 of the read / write controller 42 performs an AND operation on the first clock signal clk1 of FIG. 5 (j) and the clock enable signal of ⑤ of FIG. 5 (f) to obtain an effective read clock. Occurs. This valid read clock is input into the memories 43A to 43D in the main memory 43 through the logical sum element OR5. The memories 43A to 43D in the main memory 43 output data of the A, B, C, and D segment areas in the 100th virtual track stored in accordance with the valid read clock to the input / output unit 44. At this time, the input / output unit 44 only enables four three-phase buffers connected to the output sides of the memories 43A to 43D, and the remaining three-phase buffers are disabled and do not operate. Data read from the memories 43A to 43D of the main memory 43 are outputted to the data selector 45 through the enabled three-phase buffers of the input / output 44. The first multiplexer 45A of the data selector 45 receives data such as ˜˜ⓢ of FIG. 5 (k) and responds to the selection signal 0 such as ⓔ of FIG. 5 (l) applied from the system controller 18. Accordingly, data of the A segment area is selected and output. On the other hand, the second multiplexer 45B also receives the same data as those of the fifth (k) and the same as the signal ⓔ of the fifth (m) of FIG. Select and print the data. If the selection signal is 10, C is selected, and if it is 11, data of the D segment area is selected. The selected data is input to the corresponding MPEG decoders 15A and 15B of the data extension section 15, decoded, restored to its original state and finally output through the corresponding L and R channels of the data output section 16. As described above, when the user listens to the English stored in the A segment areas through the key control unit 17 and wants to hear the Korean stored in the D segment areas, the output of the English must be stopped. However, the data selector is shown in Table 1 below. Multiple outputs are possible in accordance with the selection signal of the multiplexers 45A and 45B at 45.

On the other hand, when the data of the A, B, C, and D segment areas in the virtual tracks such as the 100th, 101st, and 102th data are continuously read as shown in FIG. 6 (a), as described above, the buffer memory 41 The buffers 41A to 41D are divided by the first clock signal clk1 as shown in FIG. 6 (b) and the clock enable signal as shown in FIG. 6 to c in FIG. 6 (c). The same valid write clock is granted. Thus, the data of the A, B, C, D segment areas in the virtual tracks of the 100th, 101st, 102th, and the like of the input data (X) of FIG. 6 (a) are stored in the corresponding buffers 41A in the buffer memory 41. ~ 41D) in order. At this time, before the data of the A, B, C, and D segment areas in the 101st virtual track are stored in the buffer memory 41, the data of the A, B, C, and D segment areas in the 100th virtual track must be read. . Thus, the buffers 41A to 41D in the buffer memory 41 are composed of the second clock signal clk2 and the second clock signal as shown in FIG. 6 (e) of the half cycle period of the first clock signal clk1 in FIG. 6 (b). A, B, C, and D segment areas in the 100th virtual track stored during the second clock signal (clk2) in FIG. 6 (e) by receiving a valid read clock by the clock enable signal as shown in FIG. 6 (g). Read data at the same time. After that period, the data of the segment area in the 101st virtual track is stored in the buffer memory 41 as before. Here, a valid read clock of the buffer memory 41 is also applied as a valid write clock of the memories 43A to 43D of the main memory 43 and is read from the buffer memory 41 and stored in the main memory 43 at the same time. do. The same operation applies to the data of the segment area in the 102th virtual track. On the other hand, the memories 43A to 43D in the main memory 43 apply a valid read clock by the first clock signal clk1 in FIG. 6 (j) and the clock enable signal as ⑤ in FIG. 6 (f). The data of the segment area stored in the memories 43A to 43D of the main memory 43 is read out and output to the data selector 45 during the first clock signal clk1 in FIG. 6 (j). The multiplexers 45A and 45B in the data selector 45 receive data such as ˜ ~ ⓢ in FIG. 6 (k), and receive corresponding data according to ⓔ and ⓔ selection signals in FIG. 6 (l). Select and print. That is, if the ⓔ selection signals of ⓔ and (wave) in Fig. 6 (l) are 0 and 1, data of the A and B segment areas in each virtual track is selected. The memories 43A to 43D in the main memory 43 designate a track using the upper 3 bits as shown in Table 2 below, and designate an address at which actual data is recorded using the lower 7 bits.

As shown in Table 2 above, the memories 43A to 43D can store the data of the corresponding segment area in the eight virtual tracks, and know the address of the memory in which the data of the segment area in the previous virtual track is recorded. Data can be played back at any time. That is, it is effective when performing a back play function of replaying the part which has already been played back. For example, when the data of the A segment area in the 100th virtual track is currently being reproduced, and the data of the A, B, C, D segment area in the 98th or 97th virtual track is desired, the CD is conventionally picked up. Whereas the part has to be transported to its location, it is regenerated here. This will be described in more detail with reference to FIGS. 7 (a)-(c).

7 (a) to 7 (c) are diagrams for explaining a data access process in the main memory 43 of the memory unit 14 of FIG.

7 (a) shows a process in which A data is recorded among the data of the A, B, C, and D segment areas in the 100th virtual track. Here, one memory 43A constituting the main memory 43 stores data of the A segment area in the seven virtual tracks from the 99th to the 93rd, which are already reproduced portions. Thus, the buffer 41A in the buffer memory 41 stores data of the A segment area in the 100th virtual track of the input data by a valid write clock of the read / write controller 42, and stores the A segment in the 101st virtual track. The data of the area is intertwined by a valid read clock before it is entered. This valid read clock is applied as a valid write clock of the memory 43A in the main memory 43 to store data of the A segment area in the 100th virtual track read from the buffer 41A. The memory 43A reads data of the A segment area in the 100th virtual track stored by the valid read clock and outputs the data to the multiplexers 45A and 45B in the data selector 45. At this time, the multiplexers 45A and 45B selectively output data of the A segment area in the 100th virtual track input under the control of the system controller 18. On the other hand, Fig. 7 (b) shows a process in which data of the A segment area in the 101st virtual track is recorded. In this case, since the memory 43A is already full, the data of the A segment area in the 93th virtual track, which is the lowest track among the virtual tracks stored in the memory 43A, is erased, and the positions are shifted one by one to the A segment in the 101st virtual track. Save the data of the area. When the A data in the 101st virtual track is reproduced, the data of the 102th virtual track is recorded in the buffer memory 41. If data of the 102th virtual track is recorded in the buffer memory 41 and the output of the data in the 101st virtual track is completed, the lowest among the virtual tracks stored in the main memory 43 under the control of the system controller 18. The data in the 94th virtual track is erased so that the data in the 102nd virtual track can be stored. This operation is continuously maintained so that the memories 43A to 43D in the main memory 43 store data for each segment area in eight virtual tracks. Therefore, if the playback is to be performed again on the portion already played back as shown in FIG. 7 (c), the operation of the buffer memory 41 is stopped, and the playback is performed at any time when only the memories 43A to 43D in the main memory 43 are accessed. In addition to the high-speed search, it is possible to select and play back the desired part.

As described above, the present invention relates to a high-speed sorting and reproducing apparatus capable of multiple outputs, and a method thereof, which divides a digital recording medium into a plurality of virtual tracks of a plurality of segment regions, stores data for each segment region, and stores the data. Can be stored on the memory area by area, thereby reducing the access time by directly reading and reproducing data from the memory without directly accessing the recording medium. In addition, when a multilanguage is recorded, such as a language learner, at least one or more desired languages may be selectively reproduced and output simultaneously in multiple ways.

Claims (9)

A reproducing apparatus using a digital recording medium, comprising: a digital recording medium constituting a plurality of virtual tracks having a plurality of segment areas, and recording data for each segment area within the virtual track; Key control unit; A system controller for controlling the overall operation of each component according to the key operation signal of the key operator; A memory unit which reads data of a segment area in an arbitrary virtual track of the digital recording medium for each area under the control of the system controller and reads data of a desired segment in the virtual track from among the stored area data; A data selector for selecting and outputting at least one desired data from among data read from the memory unit under control of the system controller; And means for restoring and restoring the data selected by the data selector to its original state. The digital recording medium of claim 1, wherein the digital recording medium comprises a TOC area for managing data and a data area in which actual data exists, and the data area consists of a plurality of virtual tracks composed of a plurality of segment areas. The data is recorded separately, and the TOC area defines a start address for each segment area in the virtual track and a pointer to the start address. The memory unit of claim 2, wherein the memory unit receives data of a segment region in an arbitrary virtual track, sequentially stores data for each segment region according to a valid write clock, and stores and stores data of a segment region in a next virtual track. A buffer memory comprising a plurality of buffers for simultaneously reading data stored according to a valid read clock before being written to; Receiving a first click signal and a clock enable signal from the system controller to generate valid write clocks alternately in the buffers of the buffer memory, and a second clock having a period of half a cycle of the first click signal from the system controller A signal and its clock enable signal are applied to generate a valid read clock simultaneously in the buffers of the buffer memory. The read clock is generated as a valid write clock of the main memory, and the first clock signal and its clock are received from the system controller. A read / write controller configured to receive an enable signal and generate a valid read clock of the main memory; The main memory is composed of a plurality of memories in which data output to the buffers of the buffer memory are simultaneously stored for each segment area according to a valid write clock, and a segment area in a virtual track desired among the data stored according to the valid read clock reads the data simultaneously. Memory; And an input / output unit for preventing a collision between the data output from the buffers of the buffer memory and the data output from the memories of the main memory under the control of the system controller. Playback device. The data selector of claim 3, wherein the data selector comprises: a first multiplexer configured to select and output one desired data among data of a segment area in a desired virtual track output from memories of the main memory under control of the system controller; And a second multiplexer which selects and outputs one desired data from among the data of the segment area in the desired virtual track output from the memories of the main memory under the control of the system controller. Selective playback device. The apparatus of claim 4, wherein the input / output unit comprises: an inverter configured to reverse a state of a control signal of the system controller; Three-phase buffers connected to the output sides of the buffers in the buffer memory, and receiving and outputting data read from the buffers according to control signals inverted by the inverter; Respectively connected between an output side of the three-phase buffers and an input side of the memories in the main memory, and receiving the outputs of the three-phase buffers according to a control signal inverted by the inverter to output the memories of the main memory. Other three phase-buffers; And another three-phase buffers connected to the output layers of the memories in the main memory and receiving data read from the memories according to a control signal of the system controller and outputting the data to the multiplexer in the data selector. High-speed sorting and reproducing apparatus capable of multiple outputs. 4. The logical read operation of claim 3, wherein the read / write controller is commonly applied with a first clock signal of the system controller, and receives a clock enable signal alternately valid for every clock of the system controller. A plurality of AND products which result in a valid write clock of the buffers; A logical multiplication device configured to receive the first clock signal and the clock enable signal and perform a logical AND operation to generate a valid read clock of the memories; An inverter inverting the state of the clock enable signal applied to the logical AND device; A logic multiplication device configured to receive the second clock signal of the system controller and the clock enable signal of the inverter inverted state and perform an AND operation to generate a valid write clock of the memories and a valid read clock of the buffers; A plurality of logic elements for delivering valid write and read clocks of the buffers to the buffers; And a logic element for transferring effective read and write clocks of the memories to the memories. In a method of reproducing using a digital recording medium, the digital recording medium is divided into a TOC area and a data area, and the data area is divided into a plurality of virtual tracks consisting of a plurality of segment areas. Recording a TOC area, the first step of defining a start address for each segment area and a pointer of the start address in the virtual track; A second step of selecting at least one segment area to be reproduced in the virtual track in the digital recording medium of the first step; A third step of sequentially reading data of a segment area in an arbitrary virtual track including a portion selected in the second step by using the information defined in the TOC area and storing the data for each area; A fourth step of reading data of the segment area in the virtual track stored in the third step and selecting data of the segment area corresponding to the part selected in the second step; And a fifth step of restoring and restoring the data selected in the fourth step. The method of claim 7, wherein the third step comprises: storing data of a corresponding segment region among input data, and outputting the stored segment region data before the data of the segment region in the next virtual track is input and stored; And a third step of storing the data of the segment area output by the step 3a while moving the storage position of the data of the segment area in the previous virtual track. 9. The method of claim 8, wherein the fourth step comprises: a fourth step of reading data of the segment area in the current virtual track stored in the third step; Stopping the operation of the step 3a when the selected part is the previous virtual track, and reading the data of the segment area in the previous virtual track stored in the step 3b; And a fourth step (c) of selecting and outputting data of the corresponding segment area among the data of the segment area read in steps 4a to 4b.