JPS63190579A - Control circuit of servo motor - Google Patents

Abstract

PURPOSE:To enable the speed of a capstan motor to be controlled in good responsiveness and with high precision, by counting the phase difference digitally between the speed signal and synchronous speed of the capstan motor. CONSTITUTION:A phase difference detection circuit 15a outputs the phase difference output Za between a signal S2 resulting from dividing of an external synchronous signal S1 and a rotating speed signal 12a. A count circuit 1 counts the positive part of the phase difference output Za on the basis of synchronous signal S1. On the other hand, a count circuit 2 counts the phase difference between a synchronous signal 17a contained in a playback signal 16a outputted from a playback signal output section 16 and a synchronous signal Y1. Then, the output of the count circuit 1 in recording and that of the count circuit 2 in playback are given to a speed control circuit 21 through a D/A conversion circuit 3 and an amplifier 20.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a servo motor control circuit that controls a capstan motor for driving a capstan in a recorder/player to a constant speed.

(Prior Art) FIG. 6 is a block diagram showing a conventional servo motor control circuit. In the figure, reference numeral 11 is a capstan motor that moves a magnetic tape in a predetermined direction to be traced between a capstan roller and a pinch roller (not shown). transport at a constant speed. Reference numeral 12 denotes a rotation speed detection circuit (FG circuit) that detects the rotation speed of the capstan motor 11. For example, 13a is 10
The frequency of the synchronous signal X1 oscillated by a 0KHz crystal oscillator is divided by 1/100 by the frequency dividing circuit 14a, and the frequency of the rotation speed signal 12a output from the rotation detection circuit 12 (IKI
(z). A phase difference detection circuit 15a detects the phase difference between the frequency division output X2 output from the frequency division circuit 14a and the rotation speed signal 12a output from the rotation speed detection circuit 12. Reference numeral 16 denotes a reproduction signal output section, which outputs a reproduction signal 16a when a recorded signal on a magnetic tape or the like is reproduced.

Reference numeral 17 denotes a synchronization signal separation circuit that separates the synchronization signal included in the reproduction signal 16a output from the reproduction signal output section 16. 13b is a crystal oscillator, which receives the reproduction signal 1 from the magnetic tape.
6a is oscillated. A frequency dividing circuit 14b divides the frequency of the synchronizing signal Y1 to the same frequency as the reproduced signal 16a. 15b is a phase difference detection circuit, and a frequency dividing circuit 14b
The phase difference between the frequency-divided output Y2 outputted from the synchronization signal separation circuit 17 and the separated signal 17a outputted from the synchronization signal separation circuit 17 is detected. 1
A switch circuit 8 outputs either one of the phase difference outputs Za and Zb of the phase difference detection circuits 15a and 15b to the low-pass filter 19. The low-pass filter 19 receives the phase difference output Za output from the phase difference detection circuits 15a and 15b.
, Zb is smoothed. An amplifier 20 amplifies the output of the low-pass filter 19. 21 is a speed control circuit that controls the capstan motor 1 based on the output voltage from the amplifier 20;
The capstan motor 11 is rotated at a preset constant speed by varying the rotation speed of the capstan motor 11.

FIG. 7 is a circuit diagram illustrating the internal configuration of the phase difference detection circuit 15a shown in FIG. 6, and the same components as in FIG. 6 are given the same reference numerals. In this figure, 31a to 31c
is a D-type flip-flop circuit (DFF), and DFF3
The rotation speed signal 12a from the rotation speed detection circuit 12 is input to the D terminal of 1a, and the synchronization signal X1 from the crystal oscillator 13a is input to the clock input CK of the DFFs 31a and 31b. On the other hand, the frequency divided output X2 from the frequency dividing circuit 14a is inputted to the clock input CK of the DFF31c, and the NAND output N of the inverted output 4 of the DFF31a and the inverted output Q of the DFF311) is inputted to the reset terminal R.
AND is input, and a phase difference output is output from the output Q of the DFF 31c to the phase difference output circuit 32. 33 is a NAND circuit, which takes the NAND of the inverted output Q of DFF31a and the inverted output Q of DFF3 lb, and outputs the NAND output NAND to DFF3.
It is output to the reset terminal R of 1c.

Note that the phase difference detection circuit 15b also has a similar circuit configuration.

Next, while referring to the timing charts shown in FIGS. 8(a) to (d), FIGS. 9(a) to (d), and FIGS. 10(a) to (g), The operation will be explained in detail.

FIGS. 8(a) to 8(d) are timing charts explaining the signal sending timing of each part during audio signal recording, and FIG. 8(a) shows the synchronization signal Xl output from the crystal oscillator 13a. Figure (b) shows the frequency divided output x2 output from the frequency dividing circuit 14a, Figure (c) shows the rotation speed signal 12a output from the rotation speed detection circuit 12, and Figure (c) shows the rotation speed signal 12a output from the rotation speed detection circuit 12.
d) shows the phase difference output Za output from the phase difference detection circuit 15a.

FIGS. 9(a) to 9(d) are timing charts explaining the signal sending timing of each part during audio signal reproduction, and FIG. (b) in the same figure shows the frequency divided output Y2 output from the frequency dividing circuit 14b, (C) in the same figure shows the separated signal 17a output from the synchronization signal separation circuit 17, and (
d) shows the phase difference output zb output from the phase difference detection circuit 15a.

FIG. 1O<a) to (g) are phase difference outputs Za and Z output from the phase difference detection circuits 15a and 15b shown in FIG.
(a) shows the frequency-divided outputs X2.b of the crystal oscillators 13a and 13b. Y, and the same figure (b
), (d), and (f) show the rotational speed signal 12a outputted from the rotational speed detection circuit 12 or the separated signal 17a outputted from the synchronization signal separation circuit 17, and (c) and (e) in the same figure.

(g) shows the phase difference outputs Za, Zb output from the phase difference detection circuits 15a, 15b, and in particular, (C) shows the frequency-divided output x2. y, the rotational speed signal 12a shown in the same figure (b), and the separated signal 17a have a phase difference of 18
0", the figure (e) shows the divided outputs X, Y2 shown in the figure (a) and the rotational speed signal i2a and the separated signal 17a shown in the figure (d). Which phase difference is 23
4'', and (g) in the same figure shows the divided outputs X t and Y t shown in the same figure (a) and the same figure (f).
) shows the output waveform when the phase difference between the rotational speed signal 12a and the separated signal 17a is 126''.

Next, the operation will be explained. First, when recording an audio signal, the switch circuit 18 is connected to the phase difference detection circuit 15a, and the synchronizing signal x1 (see FIG. 8(a)) of, for example, 100 K) oscillated by the crystal oscillator 13a is frequency-divided. The frequency is divided by 1/100 by the circuit 14a, and IKHz
The frequency-divided output X2 (see FIG. 8(b)) is inputted to the phase difference detection circuit 15a. At this time, the rotational speed signal 12a (see FIG. 8(c)) detected by the rotational speed detection circuit 12 is input to the phase difference detection circuit 15a. At this time, the DFF 31a of the phase difference detection circuit 15a detects the rising edge of the rotation speed signal 12a, and the DFF 31a detects the rising edge of the rotation speed signal 12a.
Since a LOW level signal is output to the reset terminal (active low) of the DFF31c, the DFF31c is reset.
A phase difference signal Za shown in FIG. 8(d) is output to the low-pass filter 19. If the phase difference of this phase difference signal Za is 180@, the positive section of one phase difference signal Za becomes 50% (see Fig. 10 (c)), and there is no fluctuation in potential, and this rotational state is maintained. speed control circuit 2 so that
A predetermined potential is applied to 1, and the phase difference of the phase difference signal Za becomes 2.
In the case of 34°, the positive section of the phase difference signal Za is 65%
(see FIG. 10(e)), a potential higher than the predetermined potential is output to the speed control circuit 21, the rotational speed of the capstan motor 11 is increased, and the phase difference signal Z
When the phase difference of a is 126@, the positive section of the phase difference signal Za becomes 35% (see Figure 1O (g)), and a potential level lower than the above-mentioned predetermined potential is output to the speed control circuit 21. As a result, the rotational speed of the capstan motor 11 is reduced.

On the other hand, during audio signal reproduction, the switch circuit 18 is connected to the phase difference detection circuit 15b@, and the crystal oscillator 13b
synchronous signal Y oscillated by.

(see FIG. 9(a)) is frequency-divided by the frequency dividing circuit 14b, and becomes a frequency-divided output Y2 (see FIG. 9(b)), which is input to the phase difference detection circuit 15b. At this time, a separated signal 17a (see FIG. 9(c)) separated and detected by the synchronizing signal separating circuit 17 is input to the phase difference detecting circuit 15a. At this time, the rising edge of the separated signal 17a is detected by the DFF 31a of the phase difference detection circuit 15b, and the DFF 31a of the phase difference detection circuit 15b detects the rising edge of the separated signal 17a.
Since a LOW level signal is output to the reset terminal (active low) of 1c, the DFF 31c is reset, and the phase difference signal zb shown in FIG. 9(d) is output to the low-pass filter 19.

When the phase difference of this phase difference signal zb is 180'', the positive section of the phase difference signal zb becomes 50% (see Fig. 10(c)), and there is no fluctuation in the potential, and this rotational state is maintained. When a predetermined potential is applied to the speed control circuit 21 so that the phase difference signal zb has a phase difference of 234°, the positive section of the phase difference signal zb becomes 65% (see Fig. 10 (6)). , a potential at a level higher than the predetermined potential is output to the speed control circuit 21, the rotational speed of the capstan motor 11 is increased, and when the phase difference of the phase difference signal zb is 126°, the phase difference signal zb is The positive interval is 35% (Figure 1O (g
)), a potential lower than the predetermined potential is output to the speed control circuit 21, and the capstan motor 1
1's rotational speed is reduced.

(Problems to be Solved by the Invention) Since the conventional servo motor control circuit is configured as described above, the phase difference detection circuits 15a and 15 shown in FIG.
A low-pass filter 19 is required to smooth the phase difference signals Za and Zb, and the speed control signal 21a outputted to the speed control circuit 21 via the amplifier 20 has a lower detection waveform than the detected waveform input to the low-pass filter 19. The response becomes slow and the capstan motor 1 cannot respond to minute changes in the detected waveform input to the low-pass filter 19.
There was a serious problem that significantly reduced the speed accuracy of 1.

This invention was made to solve the above-mentioned problems, and by digitally counting the phase difference between the speed signal of the capstan motor and the synchronization signal, the speed of the capstan motor can be controlled with high responsiveness. , and with precise control.

The object of the present invention is to obtain a servo motor control circuit that can stably record/reproduce audio signals.

(Means for Solving the Problems) The servo motor control circuit according to the present invention converts the phase difference between the first external synchronization signal in the first control system and the rotational speed signal of the servo motor into the first external synchronization signal. The phase difference between the second external synchronization signal and the predetermined synchronization signal in the second control system is counted for a predetermined time based on the second external synchronization signal, and each counted count data The signal is D/A converted to generate a speed control signal for the servo motor.

[Effect]

In the servo motor control circuit of the present invention, the phase difference between the first external synchronization signal in the first control system and the rotational speed signal of the servo motor is determined based on the first external synchronization signal by the first counting means. The second counting means counts the phase difference between the second external synchronization signal and the predetermined synchronization signal in the second control system for a predetermined time based on the external synchronization signal @2, and converts the D/A. The means converts the count data counted by the first or second counting means from D/A to generate a speed control signal for the servo motor.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. 1st
In the figure, l is a counter circuit serving as the first counting means of the present invention, and a crystal oscillator 1 serving as an external synchronization signal source outputs the phase difference output Za detected by the phase difference detection circuit 15a.
3a (for example, the first external synchronization signal S oscillated from 288Kl(z)) for a predetermined time, that is, the rotation speed signal 12a of the rotation speed detection circuit 12 determined by the frequency division output S2 output from the frequency division circuit 14a. , and converts the counted count data into, for example, 8-bit bit data, and outputs it to the D/A converter circuit 3.The frequency divider circuit 14a converts the first signal oscillated from the crystal oscillator 13a into the D/A converter circuit 3. For example, the external synchronization signal S1 of
The frequency is divided into 56 and the divided frequency output S2 (1, 125
KHz) to the phase difference detection circuit Lea and counter circuit 1.
Output to. 2 is a counter circuit serving as the second counting means of the present invention, which is outputted from the reproduction signal output section 16.
For example, when a recording signal on a magnetic tape or the like is reproduced, a synchronization signal included in a reproduction signal 16a is transmitted to the synchronization signal separation circuit 1.
For example, the synchronizing signal yt (of 360 KHz) oscillated by the separated signal 17a separated by
The phase difference with the second external synchronization signal (second external synchronization signal) is counted during the rising time of the separation signal 17a, and the counted count value is converted into, for example, 8-bit bit data and output to the D/A conversion circuit 3. The D/A conversion circuit 3 converts the phase difference component data counted by the counter circuit 1 or the counter circuit 2 into an analog voltage signal (speed control signal) 3 a and outputs it to the speed control circuit 21 . In addition, above 1
1→12→15a→1-is→3→2O-P21→11
The first control system is configured by the above-mentioned 16→
A second control system is configured by 17→2→18→3→20→21→11, and the crystal oscillator 13b serves as an external synchronization signal source for the second control system.

Next, the servo motor control operation during audio signal recording according to the present invention will be explained with reference to FIGS. 2 and 3(a) to 3(f).

FIG. 2 is a circuit diagram illustrating the internal configuration of the counter circuit 1 shown in FIG. 1, and the same components as in FIG. 1 are given the same reference numerals.

In this figure, la is a NOT gate, and crystal oscillator 1
The first external synchronization signal Sl generated from 3a is inverted and outputted to the clock input CK of the synchronous counter lc. l
b is a NAND circuit which outputs a NAND output of the phase difference output Za of the phase difference detection circuit 15a and the frequency divided output S2 of the frequency dividing circuit 14a to the reset terminal R (active low) of the synchronous counter lc. ld is a D-type flip-flop (DFF
), the synchronous counter lc counts the rise time of the phase difference output Za of the phase difference detection circuit 15a input to the input terminal EP based on the first external synchronization signal Sl input to the clock input CK. The bit count data is input to the clock input CK by the divided output S2.
The signal is inputted and exchanged via the output terminal Q of DFFlc in synchronization with . DFFld outputs bit data corresponding to the phase difference sent and received from output Q to the D/A conversion circuit 3 via the switch circuit 18.

FIGS. 3(a) to 3(f) are timing charts illustrating the timing of the first counting operation according to the present invention.

3(a) shows the rotation speed signal 12a output from the rotation speed detection circuit 12, and FIG. (c) is the frequency divided output S2 output from the frequency dividing circuit 14a.
, (d) in the figure shows the phase difference output Za output from the phase difference detection circuit 15a, and (e) in the figure shows the phase difference output Za output from the crystal oscillator 1.
3a, and (f) of the figure shows the NAND output N output from the NAND circuit 1b.
AI, and this NAND output NAI is the synchronous counter I
It is input to the reset terminal R of C.

In FIG. 1, a rotational speed signal 12a (see FIG. 3(a)) outputted from the rotational speed detection circuit 12 to the phase difference detection circuit 15a, and a rotational speed signal 12a (see FIG. 3(a)) oscillated from a crystal oscillator 13a serving as an external signal source. Frequency division output S2 that is output when the rising edge of eight first external synchronization signals is detected by frequency division circuit 14a
are respectively input, the phase difference detection circuit 15a outputs the divided output S2 (see FIG. 3(c)) and the rotational speed signal 12.
Phase difference output Za (Fig. 3 (
d)) is output to the input terminal EP of the synchronous counter lc shown in FIG. For this reason, the synchronous counter lc starts counting the positive portion (rising section) of the phase difference output Za based on the synchronous signal S input to the clock input CK, and outputs, for example, 8-bit count data. The output Q of the synchronous counter lc is output to the input of DFFld. Since the frequency-divided output S2 obtained by dividing the frequency of the first external synchronization signal S from the frequency dividing circuit 14a is input to the clock input CK of DFFld, DFFld is latched when the frequency-divided output S2 rises. The count data is output to the D/A conversion circuit 3 via the switch circuit 18. At the same time as this latch operation, the reset terminal R of the synchronous counter IC shown in FIG.
W level, that is, the synchronous counter l is activated in synchronization with the rising edge of the NAND output NAI shown in FIG. 3(f).
Since the reset terminal R of c becomes LOW level, the data counted up to that point is cleared. Then, in synchronization with the fall of the NAND output NAl shown in FIG. 3(f), the reset state of the synchronous counter lc is released and a new counting operation is started.

On the other hand, when the 8-bit count data output to the D/A conversion circuit 3 is r128J (period T of the first external synchronization signal S) multiplied by 128, the half frequency M r of the divided output S2 is
2/2).

5(v) speed control signal 3a is output to the speed control circuit 21, the capstan motor 11 is rotated at a constant speed at the current speed, and if the count data is less than r128J (overspeed), the The speed control signal 3a is output to the speed control circuit 21, the capstan motor 11 is rotated at a lower speed than the current speed, and the count data becomes r12.
If the speed is higher than 8J (down speed), a speed control signal 3a of 5f or more is output to the speed control circuit 21, and the capstan motor 11 is digitally controlled so as to rotate the capstan motor 11 at a higher speed than the current speed. do.

Next, the servo motor control operation during audio signal reproduction according to the present invention will be explained with reference to FIGS. 4 and 5(a) to 5(d).

FIG. 4 is a circuit diagram illustrating the internal configuration of the counter circuit 2 shown in FIG. 1, and the same components as in FIG. 1 are given the same reference numerals.

In this figure, 2a and 2b are DFFs, and DFF2a
, 2b, the synchronization signal Y□ is input to the clock input CK of 2b.
(360KHz oscillated by the crystal oscillator 13b serving as an external synchronization signal source), the synchronization signal separation circuit 17
Detects the rising edge of the separation signal 17a output from. 2C is an AND circuit, which outputs the AND outputs of the outputs Q of DFF2a and 2b to the synchronous counter 2e, the R-S flip-flop 2', and the reset terminal R of the synchronous counter 2g.
and output to the clock input CK of DFF2h. Among these, clock input CK of synchronous counters 2e and 2g
The synchronizing signal Y oscillated from the crystal oscillator 13b is input to the synchronous counter 2e, and the count value of the synchronous counter 2e is r2.
31J, the setting force S of the R-S flip-flop 2f becomes HIGH, and the synchronous counter 2
The input terminal EP of g becomes HIGH, and counting begins after r231J. At that time, synchronous counter 2g
When counting rl 28J, the data is outputted to the D/A conversion circuit 3 via the switch circuit 18 as 8-bit count data similar to the synchronous counter lc shown in FIG. This means that when the frequency of 360 KHz of the separated signal 17a and the synchronizing signal Y1 is counted by the synchronous counters 2e and 2g, the same 8-bit signal as the synchronous counter lc is directly D-signaled without any preprocessing.
/A conversion allows the speed of the capstan motor 11 to be controlled during playback in the same way as the speed control of the capstan motor 11 during recording. Note that 2d is a NOT gate, and crystal oscillator 1
DFF2 inverts the synchronization signal Y output from DFF2.
Output to clock input CK of a and 2b.

FIGS. 5(a) to 5(d) are timing charts illustrating the second counting operation timing according to the present invention.

FIG. 4A shows a separated signal 17a output from the synchronization signal separation circuit 17, which is output to the input of the DFF 2a.

FIG. 5(b) shows the detected waveform EG2 of the separated signal 17a detected by the DFFs 2a and 2b, and FIG. Figure (d) shows the count-up signal UP of the synchronous counter 2e that is input to the set input S of the R-S flip-flop 2f.

A separated signal 17a (see FIG. 5(a)) is obtained by separating a synchronizing signal included in a reproduced signal 16a output from the reproduced signal output section 16, for example, when a recorded signal on a magnetic tape or the like is reproduced, by a synchronizing signal separation circuit 17 (see FIG. 5(a)). ) is input to the input of DFF2a, the rising edge shown in FIG. 5(b) is detected, the outputs Q of DFF2a and 2b become LOW and HIHG, and the AND circuit 2C becomes LOW. It becomes possible to count, and starts counting the synchronizing signal Y□ shown in FIG. 51(c). When this counting operation continues and the count value reaches r321J,
The R-S flip-flop 2f shown in FIG. 4 is shown in FIG.
It becomes a HIGH state at the timing shown in d), the input terminal EP of the synchronous counter 2g becomes a HIGH state, the counting operation by the synchronous counter 2g is taken over, and the detection waveform EG2 shown in FIG. 5(b) rises. case,
That is, it continues until the next separated output 17a is output from the synchronizing signal separating circuit 17. When the count by the synchronous counter 2g is completed, that is, when the detection waveform EG2 shown in FIG. The counted 8-bit count data is sent and received via the output Q of the synchronous counter 2g, and the D/A is sent via the switch circuit 18.
Output to conversion circuit 3.・For example, the 8-bit count data output to the D/A conversion circuit 3 is r128J (
Count up value r231J by synchronous counter 2e
+Count up value r by synchronous counter 2g 12
8'' (total 360), that is, if the phase difference between the separated signal lf a output from the synchronizing signal separation circuit 17 and the synchronizing signal Y1 is 180'' (7), then the speed control is 5 (v). The signal 3a is output to the speed control circuit 21, the capstan motor 11 is rotated at a constant speed at the current speed, and when the count data is 2 less than r128J (overspeed), the speed control signal 3a of 5V or less is output to the speed control circuit 21. Control circuit 21
When the count data is greater than r128J (down speed), a speed control signal 3a of 5V or more is output to the speed control circuit 21, and the capstan motor 11 is rotated at a lower speed than the current speed. The capstan motor 11 is digitally controlled so as to rotate the stan motor 11 at a higher speed than the current speed. In this way, even if the count value of the counter circuit 1.2 differs depending on the control system (even if the frequency of the external synchronization signal differs), one D
The speed of the capstan motor 11 can be digitally controlled by using the /A conversion circuit 3 in common.

In the above embodiments, the capstan motor servo system of a recording/playback device that records/plays audio signals was explained as an example, but the control system that drives the servo motor by synchronization from other external sources and the Needless to say, the invention can also be used in a system having two control systems, one controlled by a reproduction signal from the medium.

〔Effect of the invention〕

As described above, according to the present invention, the first control system counts the phase difference between the first external synchronization signal in the first control system and the rotational speed signal of the servo motor for a predetermined period of time based on the first external synchronization signal. and a second counting means for calculating the phase difference between the second external synchronization signal and the predetermined synchronization signal in the second control system.
a second counting means for counting a predetermined time based on an external synchronization signal; and a D/A converting means for generating a speed control signal for the servo motor based on the count data counted by the first or second counting means. 2, the phase difference between the external synchronization signal and the feedback signal from the servo motor controlled by the external synchronization signal can be digitally processed and counted in the servo system where the recording system and playback system exist. It has the excellent advantage of being able to output a speed control signal according to the phase difference to the servo-motor drive system with high precision and high speed, and realizing accurate and stable recording and reproduction of audio signals.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the configuration of a servo motor control circuit showing an embodiment of the present invention, FIG. 2 is a circuit diagram explaining the internal configuration of the counter circuit l shown in FIG. 1, and FIG. a) to (f) are timing charts explaining the first counting operation timing according to the present invention, and FIG.
5(a) to 5(d) are timing charts illustrating the second counting operation timing according to the present invention;
The figure is a block diagram explaining the configuration of a conventional servo motor control circuit, Figure 7 is a circuit diagram explaining the internal configuration of the phase difference detection circuit shown in Figure 6, and Figures 8 (a) to (d) are Timing charts for explaining signal sending timings of each part during audio signal recording; FIGS. 9(a) to (d) are timing charts for explaining signal sending timings of each part during audio signal reproduction; FIGS. 1O(a) to 10(d) (g) is a diagram showing the output waveform of the phase difference output output from the phase difference detection circuit shown in FIG. 6. In the figure, 1 and 2 are counter circuits, 3 is a D/A conversion circuit, 11 is a capstan motor, 12 is a rotation speed detection circuit, 13a and 13b are crystal oscillators, 15 is a phase difference detection circuit, and 16 is a reproduction signal Output section. 17 is a synchronization signal separation circuit.

Claims (3)

[Claims] (1) Among the first and second external synchronization signals of different frequencies generated from two external synchronization signal sources, the first one controls the rotation speed of the servo motor to a constant speed based on the first external synchronization signal. and a second control system that controls the rotation speed of the servo motor to a constant speed based on the second external synchronization signal.
a servo motor control circuit having a control system, wherein a phase difference between the first external synchronization signal in the first control system and a rotational speed signal of the servo motor is determined based on the first external synchronization signal. a first counting means for counting time; and a second counting means for counting a phase difference between the second external synchronization signal and a predetermined synchronization signal in the second control system for a predetermined time based on the second external synchronization signal. A servo motor control comprising: counting means; and D/A conversion means for generating a speed control signal for the servo motor based on count data counted by the first or second counting means. circuit. (2) The servo motor control circuit according to claim (1), wherein the second counting means has the same number of bits as the number of bits of the count data counted by the first counting means. (3) If the phase difference counted by the second counting means based on the second external synchronization signal and the phase difference counted by the first counting means based on the first external synchronization signal are the same, then The servo motor control circuit according to claim 1, wherein the servo motor control circuit outputs the count data of 1 to the D/A conversion means.