JPS63196961A - Data transfer controlling method - Google Patents

Abstract

PURPOSE:To inhibit an unnecessary data from being transferred to an arithmetic and control unit, and to improve the data transfer efficiency by providing a request address receiving register, a request designating part receiving register, a request processing circuit, etc. CONSTITUTION:When an arithmetic and control unit 3 sends out a block read request for instructing to discontinue a data transfer at a block boundary, it is set to a request address receiving register 25 and a request designating part receiving register 26. Subsequently, a buffer memory 20 is indexed through a request processing circuit 21, and when a request data exists on the memory 20, a request partition is set as the head and a data up to the last partition of a block boundary is transferred to the unit 3, and the subsequent data transfer is discontinued. Also, when no request data exists on the memory 20, the request partition is set as the head and the data up to the last partition of the block boundary is transferred from a main memory device 1, and it is unnecessary data is not transferred to the unit 3, and the transfer efficiency of a data can be improved.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a data transfer control method between an arithmetic control unit and a main memory device.

〔overview〕

The present invention provides a method in which an arithmetic and control unit obtains required data all at once from a main memory device in response to a block read request. By transferring the transfer section data up to the end of the boundary to the arithmetic control unit and aborting the transfer of the remaining transfer section data, it prevents the decline in data transfer efficiency caused by transferring unnecessary data to the arithmetic control unit. It was made so that it could be done.

This application is an improvement of the patent application of the same name by the same applicant (filed on December 29, 1986).

[Conventional technology]

In large-scale information processing systems, high-speed data processing is required in both the fields of business processing calculations and scientific and technical calculations, and a high-speed buffer memory that stores a copy of a portion of the data in the main memory is installed in the memory control unit. provided.

To obtain the data required by the arithmetic control unit, the buffer memory in the memory control unit is first indexed, and if the required data exists, it is transferred from the buffer memory to the arithmetic control unit, and if it does not exist, it is transferred to the main memory device. A block data transfer request is made to the memory control device, and the block data starting with the required data is transferred to the memory control device in several parts. Within the memory control device, this block data is written to the buffer memory, and the required data at the beginning is directly transferred to the arithmetic control device.

Here, in order to obtain the data required by the arithmetic and control unit all at once, a block data transfer request is made to the memory control unit (hereinafter, a block data transfer request made by the arithmetic and control unit to the memory control unit is called a block read request). ) may be carried out. In this case, in the conventional data transfer control method, when the required data exists on the buffer memory in the memory control device, the required block data on the sofa memory is divided into multiple sections, and the data is transferred at the accessed address. All required block data is transferred to the arithmetic and control unit in several batches, starting with the segmented data. If the block data does not exist, a block data transfer request is made to the main memory device, the required block data read from the main memory device is divided into multiple sections, and the transfer section data at the accessed address is the first section. , transfer to the memory controller. In the memory control unit, this block data is written to the buffer memory, and all of the required block data is transferred directly to the arithmetic control unit in several batches, starting with the transfer classification data at the accessed address. I was in control.

[Problem that the invention seeks to solve]

Incidentally, array calculation processing is an example of frequent block read requests for the purpose of obtaining data required by the calculation control device all at once. In the field of scientific and technical computing, it is desired to perform the same processing at high speed on large amounts of array data regularly arranged in memory, and it is necessary to transfer data at high speed to the arithmetic unit in the arithmetic control unit. Therefore, the arithmetic and control unit reads the necessary data all at once in response to a block read request.

In this case, in the conventional data transfer control method described above,
All block data will be transferred starting with the transfer classification data on the accessed address. for example,
When one block of data is 64 bytes, as shown in Figure 4, this 64-byte block data is the data length determined by the data transfer width between the arithmetic control unit and the memory control unit (this byte is 8 bytes). It is divided into
All the block data is transferred to the arithmetic and control unit in eight batches. Here, the 64-byte block data from the beginning of the block boundary to the end of the block boundary is defined as word numbers 0 to 7, and the array data required by the arithmetic control unit is continuous from the address position of word number 3 in the direction of increasing addresses. If the arithmetic and control unit wants to obtain the required array data all at once through a block read request, the memory control unit must send a block read request at the address corresponding to array data 0. In the conventional data transfer control method, word number 3 of array data O is sent to the arithmetic control unit, regardless of whether or not this array data 0 exists on the buffer memory in the memory control unit. Starting with the transfer classification data of , continue from word number 4 to
7. Transfer all program data of word numbers 0 to 2.

At this time, the transfer classification data with word numbers O to 2 is unnecessary data that is not needed by the arithmetic control unit, and the data of word numbers 0 to 2 of this unnecessary data is transferred to the buffer memory in the memory control unit or to the main memory. Disadvantages include an increase in unnecessary memory access time when reading data from the internal memory and transferring it to the arithmetic control unit, and processing to separate necessary data from unnecessary data within the arithmetic control unit. be.

Furthermore, if the required data does not exist on the buffer memory in the memory control device and the required block data is read from the main memory device, this read block data will be stored on the buffer memory in the memory control device. In this case, while this block data is being written to the buffer memory, processing of a new request sent from the arithmetic control unit is forced to wait within the memory control unit. Become. That is, writing block data containing unnecessary data onto the buffer memory has the disadvantage that processing of new requests is delayed and buffer memory usage efficiency is reduced.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data transfer method that can improve data transfer efficiency by prohibiting unnecessary data from being transferred to an arithmetic and control unit.

[Means for solving problems]

The present invention provides an arithmetic control means that issues a block transfer request via a buffer memory that holds part of the data stored in a main memory device in block units, and divides the block data held in the buffer memory into a plurality of sections. In a data transfer control method that sequentially transfers data in multiple sections starting with a request section out of sections divided into sections, when data related to a block transfer request is on the buffer memory, the data is stored in this buffer memory. The data starting from the requested segment and ending with the last segment at the block boundary is transferred to the arithmetic control means among the plurality of segments, and when the data requested by the block transfer request is not on the buffer memory, the data is transferred to the arithmetic control means. Data from the main memory device starting from the requested section to the last section of the block boundary is read out and transferred to the arithmetic control means, while the read data is prohibited from being stored in the buffer memory. .

[Effect]

When the data required by the arithmetic control unit is placed continuously from the middle of the block boundary and the required data is obtained all at once, transfer of data from the beginning of the required data to the end of the block boundary. and then terminates further data transfer.

Further, when required data is not present on the buffer memory in the memory control device and required block data is read from the main memory device, writing of block data containing this unnecessary data to the buffer memory is prohibited.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing memory data formats of various memories in the embodiment system of the present invention. In FIG. 2, young addresses are located on the left, word numbers O to 7 indicate word identification every 8 bytes, and 64-byte boundaries indicate address positions where addresses are divisible by 64.

First, the configuration of this embodiment system will be explained based on FIG. This embodiment system includes a main memory device 1, a memory control device 2, and an arithmetic control device 3. Here, the main memory device l includes a memory section 10 that stores instruction words, operand data, etc., an address register 1) that holds an address for accessing the memory section 10 sent from the memory control device 2, and a memory section 10. a data register 12 that holds data read from the data register 12;
and a data selection circuit 13 that selects the order in which the data read out to the memory control device 2 is sent.

FIG. 3 shows an example of the configuration of the address register 1) in FIG. 1. In the example shown in FIG. 3, the 0th bit is used as an instruction bit, and the 1st and subsequent bits are used as address data. In this embodiment method, the 0th bit instruction bit is always set to "0" in a normal request, and the address register 1) is rlJ is set when instructing an operation to read data from the address indicated by the first bit onwards to the last data at the block boundary and to inhibit reading of the remaining data within the block.

Next, the memory control device 2 has a buffer memory 20 that holds a part of the data read out from the memory unit 1O in the main memory device 1, and various types of calculations instructed by the device 3. A request processing circuit 21 that processes requests, a data register 22 that holds data sent from the main memory device l, and a data selection circuit 23 that selects the first half of the data and the second half of the data in the data register 22.
, a data selection circuit 24 that selects data read from the buffer memory 20 and data selected by the data selection circuit 23, and a memory for data sent from the arithmetic control device 3 and required by the arithmetic control device 3. A request address receiving register 25 and a request specifying part receiving register 26 are provided, each holding an address and a request specifying part indicating the contents of the request.

Although not shown, the arithmetic and control device 3 has a similar configuration to a known arithmetic and control device, and also includes a device that needs to read data from the main memory device 1, such as an input/output device. Further, the main memory device 1, memory control device 2, and arithmetic control device 3 are connected through interface lines 100 to 104.

Next, the operation of this embodiment device will be explained based on FIGS. 1 to 4.

First, the data width of the data transfer path 104 from the memory control device 2 to the arithmetic control device 3 is 8 bytes, and the data width of the data transfer path 101 from the main memory device l to the memory control device 2 is 16 bytes. 10 and buffer memory 20 are both 64 bytes in block size. That is, when transferring block data from the memory unit 10 and the buffer memory 20, one block of data is both 64-byte data from a 64-byte boundary. Further, the circuit elements of the main memory device 1 are connected to the memory control device 2.
It is slower than the circuit elements of the arithmetic and control unit 30, and its machine cycle time is set to double. That is, from the perspective of the memory control device 2, data transfer from the main memory device 1 is at a rate of 16 bytes in 2 machine cycles.

Now, suppose that the arithmetic control unit 3 needs to fetch an instruction or an operand, and a memory request is sent to the memory control unit 2.

Here, a case will be described in which a normal block read request is sent for the purpose of collectively obtaining block data including data required by the arithmetic and control unit 3. The arithmetic control unit 3 sends the memory address of the required data and a request specifying part specifying a normal block read request to the memory control unit 2, and the respective contents are stored in the request address receiving register 25 and the request specifying part receiving register 26. Each is set. Next, the contents of the request address receiving register 25 and the request specifying section receiving register 26 are transmitted to the request processing circuit 21. The request processing circuit 21 receives the contents of the request specifying section that specifies the memory address of the required data and a normal block read request, and first indexes the buffer memory 20 with the memory address of the required data. If the required data exists in the buffer memory 20, the required data is read out, and then the block data are sequentially read out.

That is, the 64-byte block data is divided into 8 transfer section data of 8 bytes each, and the 8 transfer section data with the 8-byte required data at the beginning are sequentially read out and sent to the arithmetic control unit 3 through the data selection circuit 24. sent to.

If the required data does not exist in the buffer memory 20,
The request processing circuit 21 sends a block data transfer request to the main memory device 1 along with the memory address of the required data, and the memory address of the required data is stored in the address register 1.
) is counted after the first bit. At this time, the request processing circuit 21 simultaneously outputs the address register 1).
Set the designated focus of the bit to 0.

In the main memory device 1, 64-byte block data is read from the memory unit 10, and first the accessed 8
The required data of the byte and the next 8 bytes of data (address plus 8) are read out simultaneously and set in the data register 12. Similarly, the 64-byte block data is sequentially read into the data register 12 every 16 bytes, and sent to the memory control device 2 in four parts via the data selection circuit 13. At this time, the order of data transfer of the 64-byte block data to the memory control device 2 is, for example, if the memory address of the required data from the arithmetic control device 3 indicates a position corresponding to word number 3, word number 3 ~7.0~2.

In other words, the transmission order is that the first word number of the required data is 3 and 4, and the second word number is 5 and 6.3.
The th word is word number 7, the 0th word is word number 1, and the 4th word is word number 1 and 2, and they are sequentially sent out in sets of two words each.

Now, in the memory control device 2, each 16-byte data sent from the main memory device 1 is stored in a data register 22.
The first 8 bytes and the latter 8 bytes are selected by the data selection circuit 23 in this order, and 64 bytes of data are sent directly to the arithmetic and control unit 3 via the data selection circuit 24 and written to the buffer memory 2G. .

The above is the operation of a normal block read request, which is similar to the conventional data transfer control method.

Next, the characteristic operation of the data transfer control system of the present invention will be described. Assume that the arithmetic and control unit 3 processes array data, and that the required array data is continuously arranged on the memory from the address position of word number 3 in the direction of increasing addresses as shown in FIG. The arithmetic control unit 3 sends a block read request to the memory control unit 2 for the purpose of pre-fetching array data when performing high-speed processing of array data. When sent, in addition to the necessary data of word numbers 3 to 7, unnecessary data of word numbers θ to 2 are transferred to the arithmetic and control unit 3, and therefore,
Reading and transferring unnecessary data increases wasteful memory access time, and processing is required to separate necessary data from unnecessary data within the arithmetic control unit 3.

Therefore, the arithmetic and control unit 3 issues a block read request (hereinafter referred to as block boundary block read request) instructing to terminate data transfer at the block boundary.
Send out. That is, the arithmetic control device 3 sends to the memory control device 2 a memory address indicating array data 0 and a request specifying section specifying a block boundary block read request. The memory address and request designation section are set in the request address receiving register 25 and the request designation section receiving register 26, respectively.

The contents of the request address receiving register 25 and the request specifying section receiving register 26 are transmitted to the request processing circuit 21, and the request processing circuit 21 first indexes the buffer memo 1J20 using the received memory address. If the required data exists in the buffer memory 20, the required data is read out, and then the block data are sequentially read out. At this time, the request processing circuit 21 starts with the required data of 8 bytes of the 64-byte block data and transfers the last transfer classification data of the block boundary according to the instruction of the request specifying section that specifies the received block boundary block read request. Read up to
Control is performed to inhibit subsequent reading of transfer classification data. In this example, the transfer section data of word numbers 3 to 7 corresponding to array data O to 4 are read out, and the subsequent unnecessary data of transfer section data of word numbers 0 to 2 are not read out. . The transfer classification data of word numbers 3 to 7, that is, array data 0 to 4, read from the buffer memory 20 are sent to the arithmetic and control unit 3 through the data selection circuit 24.

If the required data does not exist in the buffer memory 20,
The request processing circuit 21 sends a block data transfer request to the main memory device 1 along with the memory address of the required data, and the memory address of the required data is stored in the address register 1.
) is set after the first bit. At this time, the request processing circuit 21 simultaneously sets the 0th instruction bit of the address register 1) to 1 for the purpose of instructing data transfer from the required data to the last data at the block boundary.

In the main memory device 1, reading is performed from the memory unit 10 to the required data on the memory address indicated by the first bit and subsequent bits of the address register 1) up to the last data at the block boundary. First, the accessed 8-byte required data and the next 8-byte data (address plus 8) are read simultaneously. Thereafter, the data in the block is sequentially read out every 16 bytes, and when up to 16 bytes of data including the data of word number 7, which is the last data at the block boundary, is read out, the reading of data from the memory unit 10 ends. 0 In this embodiment, the data of word numbers 3 and 4 are read out at the beginning, then the data of word numbers 5 and 6, the data of word numbers 7 and 0 are read out sequentially, and the data of word numbers l and 2 is read out. will not be performed. here,
The data required by the arithmetic control unit 3 are word numbers 3 to 7.
Therefore, if the data paired with the data of word number 7 is unnecessary data as in this example, it does not matter what kind of data it is.
Data read from the memory section 10 is sequentially set in the data register 12 and sent to the memory control device 2 via the data selection circuit 13.

In the memory control device 2, each 16-byte data sent from the main memory device 1 is set in a data register 22, and the data selection circuit 23 selects the first 8 bytes and the latter 8 bytes in this order. Data transfer to the arithmetic and control unit 3 is performed by the request processing circuit 2 according to instructions from a request specifying section that specifies a block boundary block read request.
1, the last transfer segment data at the block boundary with the required data at the beginning, that is, word numbers 3 to 7.
Only the transfer classification data (array data θ to 4) is sent to the arithmetic and control unit 3 through the data selection circuit 24,
Unnecessary data (word number 0 data in this embodiment) that has been sent out together with word number 7 data (array data 4) is not sent out, and the data in the buffer memory 20 is managed for each program and data unit. Since the data sent from the main memory device 1 is less than l block data, writing to the buffer memory 20 is inhibited under the control of the request processing circuit 21.

As a result of this, a new arithmetic and control device! Requests sent from 3 are processed without waiting.

The above is the operation of the block boundary block read request, which is a feature of the data transfer control system of the present invention, and only the array data θ to 4 required by the arithmetic and control device 3 are sent to the arithmetic and control device 3.

〔Effect of the invention〕

As explained above, the present invention is applicable when processing data in which data required by an arithmetic and control unit is arranged continuously from the middle of a block boundary, for example when processing array data. In response to a block read request used by the arithmetic control unit to obtain the data it needs all at once, reads the required data from the beginning of the data to the end of the block boundary from the buffer memory or the memory section in the main memory device. Since a means for transferring the data to the arithmetic and control unit is added, unnecessary access time that occurs when reading unnecessary data from the buffer memory or the memory section in the main memory device and transferring it to the arithmetic and control unit is saved, and the unnecessary data is saved in the arithmetic and control unit. This has the effect of reducing wasteful processing associated with separating necessary data from unnecessary data.

Furthermore, if the required data does not exist on the buffer memory in the memory control device and the required data is read from the main memory device up to the last data at the block boundary, these data will not be written to the buffer memory. Therefore, there is an effect that processing can be performed without having to wait for a new request sent from the arithmetic and control unit.

[Brief explanation of the drawing]

FIG. 1 is a block configuration diagram showing the configuration of an embodiment system of the present invention. FIG. 2 is a conceptual diagram showing the memory data format. FIG. 3 is a configuration diagram of the address register shown in FIG. 1. FIG. 4 is an arrangement diagram of array data. 1... Main memory device, 2... Memory control device, 3.
...Arithmetic control unit, 10...Memory section, 1)...Address register, 12.22...Data register, 1
3.23.24...Data selection circuit, 20...Buffer memory, 21...Request processing circuit, 25...
-Request address receiving register, 26...Request specification section receiving register.

Claims (1)

[Claims] (1) The block data held in the buffer memory is divided into multiple sections by the arithmetic control means that issued the block transfer request via the buffer memory that holds part of the data stored in the main memory device in block units. In a data transfer control method that sequentially transfers data of multiple sections among the divided sections, starting with the request section, when the data related to the block transfer request is on the buffer memory, the data is stored in this buffer memory. out of the plurality of divisions in which the requested division is located, the data up to the last division at the block boundary is transferred to the arithmetic control means, and when the data requested by the block transfer request is not on the buffer memory, the data is transferred to the arithmetic control means. Data characterized in that the data from the request section to the last section of the block boundary is read from the memory device and transferred to the arithmetic control means, while the read data is prohibited from being stored in the buffer memory. Transfer control method.