JPS629290A - Voice recording and reproducing device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] [Technical field of invention] The present invention relates to a voice recording/playback device.

[Problems with conventional technology]

2. Description of the Related Art Conventionally, a digital audio recording method is known as a method for recording audio, in which input audio waveform data is sampled at a sampling frequency of, for example, 2 KHz or 4 KHz, and recorded as is. However, with this method, volume data must be stored for each sampling frequency, so even when recording for a short time, a huge amount of memory is required. If the timing is stored in 1 byte capacity, even if it is a 1 second recording, 2
It has a storage capacity of bytes.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an audio recording and reproducing device that can record and reproduce audio for a long time with a small amount of memory.

[Key points of the invention]

In order to achieve the above object, the present invention utilizes a recognition means and a speech synthesis means, writes and controls the code recognized by the recognition means in the memory during recording, and controls the code recognized by the recognition means during playback.
The gist of this system is to control the reading of the code recorded in the memory to the voice synthesis means, and to display the recorded voice in characters at least during recording.

〔Example〕

FIG. 1 shows an overall circuit block diagram of an embodiment in which the present invention is applied to an electronic watch. In addition to the functions of a normal electronic watch, the device shown in FIG. In mode, the audio signal input from the microphone is
The voice recognition device recognizes each voice one by one, records the resulting voice code by writing it into the voice storage RAM, and also displays the corresponding characters on the display. Furthermore, in the playback mode, the audio codes in the audio RAM are sequentially read out and sent to the speech synthesizer, the audio code is decoded and the audio signal is sent to the speaker to play back the audio. is displayed on the display. others.

It has a fast forward mode, a rewind mode, etc., and although it is digital recording, it appears to operate like a normal tape recorder.

The details of the operation will be described later, but first, the configuration of the device will be described in detail below.

The oscillation signal from the oscillation circuit 1 is input to the frequency division timing circuit 2.The 0 frequency division timing circuit 2 not only sends a clock signal for time measurement to the clock circuit 6, but also sends a clock signal of 2H7 (when in fast forward 7 rewind mode). , which is used to count up/down the counter CTR at high speed (details will be described later), to the address control section 4, and an 8H2 clock (used in the playback mode as described later) to the recording/playback control section 3. Similarly, a clock of 64 Hz to 32 Hz (used in the recording mode as described later) is also supplied to the recording/playback control section 3.

The key input unit 8 supplies key input signals to the clock circuit 6 via the bus B-2, and includes recording mode, playback mode, fast forward mode, rewind mode, rewinding during playback, and alarm setting (address counter). Automatic preset), stop, etc. can be entered by key operation, and the clock circuit can also be controlled.

In addition to the normal timekeeping function (receiving a timekeeping clock signal, counting the time, and sending this time information to the display section 7 via the bus B-1 to display the time), the clock circuit 6 also has a key human power section. Each key generates various signals according to human power. That is, for a recording input operation, first, a pulse is output from the CC output to clear the contents of the address counter CTR, and then a high-level signal, that is, a recording mode signal, is output from the R output, and this is used for recording/playback. It is sent to the control unit 3 and the voice recognition device VR. In response to a playback input operation, a high-level playback mode signal is output from the P output, and the recording/playback fi
The signal is sent to the control unit 3 and the speech synthesizer iVG. In addition, in response to a fast forward input operation, a high level fast forward mode signal is output from the F output, and in response to a 0 rewind input operation, which is sent to the address control section 4, a high level rewind mode signal is output from the B output. This is also sent to the address control section 4. For alarm setting operations, when the internal alarm circuit (not shown) is activated, that is, at the alarm time, the address bus A is
Outputs the preset address via B-2 and outputs the preset address to the address counter C by the output LD.
TR is preset, and playback is automatically performed from that preset address. Further, the clock circuit 6 receives address data outputted from the address counter CTR via the address bus AB-2 under the recording/playback/fast forward/7 rewind mode (when operating as a recording/playback device). Take it, decode it and display it! ! The address value is displayed in digital or analog form on A7. As a result, the current address position for the total recording capacity, that is, the recorded capacity and remaining capacity can be known. Furthermore, under the recording/playback mode, the voice code of each single note recognized by the voice recognition device (the code written in the voice storage RAM 5,
Alternatively, the code input to the speech synthesizer (that is, the code read from the speech storage RAM 5) is transferred to the data bus D.
The receiver is taken through B-5, decoded, and the corresponding character is displayed on the display section 7.

Next, the voice recognition device VR operates in the recording mode with the signal R, receives the voice signal from the microphone MC, recognizes it one by one, and then converts it into a character code such as an ASCII code (or similar recognition code). is sent to the data bus DB-3, and at the same time, an enable signal indicating the completion of single-note recognition is outputted from the output E and sent to the CP input of the latch 14 via the control line Ll, and the latch 14 is activated to latch the recognition code. output to bus DB-2. The enable signal from the output E is also sent to the recording/playback control section 3.

Reference numeral 18 denotes a 3-state gate, which operates at low level when the enable signal sent from the recording/playback control unit 3 via the control line L4 in the recording mode, reads the recognition code on the bus DB-2 as data. Output to bus DB-1. The voice recording RAM 5 performs voice recognition in recording mode! IVR
The recognition codes stored in the locations addressed by the address counter CTH are stored in the locations addressed by the address counter CTH, and in the playback mode, the recognition codes stored in the locations addressed by the address counter CTH are outputted to the speech synthesizer and clock circuit 6. is sent to the display section 7 via the RA.
In the recording mode, M5 is addressed by the address counter CTR via the address bus AB-1, and a write signal (low level) is sent from the recording/playback control section 3 via the control lines L4 and L5 to the chip. With the selection signal (low level) applied to the C8 input, the voice memory R
The recognition code (voice code) on the data bus DB-1 is written into AM5. Also, under playback mode,
With the τI large input active and the address specified by the address counter CTR, a recognition code is read out from the voice storage RAM 5 onto the data bus DB-1, and this recognition code is sent to the latch 16.

In the playback mode, this latch 16 is latched by an enable signal input from the recording/playback control unit 3 to the CP input via the control line L2, and transfers the recognition code on the data bus DB-1 to the data bus DB. -4 and sent to the voice synthesizer VG.

The voice synthesizer VG is connected to the voice storage RAM via the latch 16.
The recognition code sequentially read from 5 is decoded, converted into an audio signal, and sent to the speaker SP via the output line OUT.
Play the audio.

Also, during recording and playback, the recognition code on the data bus DB-1 is sent to the latch 15, and this latch 15 receives the voice recognition code on the data bus DB-1 in the recording/playback mode. When an enable signal is applied to the CP input from the recording/playback control section 3 via the control line L6, it is sent to the clock circuit 6 via the capture data bus DB-5 and corresponds to the display section via this. Next, the configuration of the address control section 4 and the address counter CTR will be explained with reference to FIG. 2.

The address counter CTR is a counter 11 for the lower 3 bits AO to A2, and a counter 1O1 for the middle 3 bits A3 to A5.
It consists of counters 9 (top 10 bits) A6 to A15, and has a total of 16 bits.

Therefore, RAM 5 can store 32,768 words.

The preset inputs of the counters 11, 10, and 9 are supplied from the clock circuit 6 via the address bus AB-2, and are preset when the load signal LD is supplied. Further, each count output of the counters 11 and 10.9 is supplied to the clock circuit 6 and the RAM 5 via the address bus AB-1 as described above. A clock given via the control line L5 is input from the recording/playback control section 3 to the CP input of the lower counter 11 in the recording/playback mode. As described above, the load signal is input from the 1 clock circuit to the LD large input of each counter at the time of presetting. Further, a clear signal is input to the CL large input of each counter from the clock circuit at the start of the playback mode. The C output of the lower counter 11 (the carry output is coupled to the CP input of the middle counter 10 via the OR gate 32, and the C output of the middle counter 10 is coupled to the CP input of the upper counter 9 via the OR gate 31). There is.

Further, the address control unit 4 receives a fast forward mode signal F, a rewind mode signal B, and a playback mode signal P from a clock circuit, and also receives a frequency division timing circuit. The 2H1 clock is input from the 2H1 clock. That is, the fast-forward mode signal F and the 2Hz clock are input to the two-man power AND gate 24, and its output is applied to the CP input of the upper address counter 9 via the three-man power OR gate. The three-man-powered AND gate 25 receives the rewind mode signal B, the 2Hz clock, and the playback mode signal (thus prohibited to operate in the playback mode) given via the inverter 35, and its output is fed through the three-manpower OR gate 31. and is added to the CP input of the upper counter 9. In addition, the reproduction mode signal P, the 2H2 clock, and the rewind signal are input to the three-man power AND gate 26.
Therefore, it operates in the rewind mode during playback, and its output is passed through the two-man OR gate 32 to the C of the intermediate counter 10.
Add to P input. Further, the rewind mode signal B is coupled to the upper and middle counters 9 and 10's UD large input via the inverter 36, and therefore, in the rewind mode, each of these counters performs a countdown operation.

Next, the recording/playback control section 3 will be explained with reference to FIG. The recording/playback control unit receives the playback mode signal P from the clock circuit, the 8H2 clock from the recording mode signal R frequency division timing circuit, any clock from 64Hz to 32KH2, and a single note from the voice recognition device. A signal L-1 indicating completion of recognition is input.

That is, the signal P and the 8H7 clock are input to the two-man power AND gate 23 (therefore, it operates in the reproduction mode), and its output is added to the two-man power OR game) 3(). 2 person AND
Gate 22 has recording mode signal R and 64Hz to 32KH.
2 clocks are input (therefore operating in recording mode)
, its output is input to a two-man OR gate 30. OR
The output of gate 30 is applied as a clock to the CP inputs of D flip-flops (D-FF) 12 and 13.

Both D-FFs 12 and 13 constitute a quaternary ring counter. That is, the Q output of D-FF12 is the D output of D-FF14.
The output of the D-FF 13 is coupled to the D input of the D-FF 12 as an input.

Furthermore, the two-output AND gate 21 is coupled to the recording mode signal R and the set output Q of the RS flip-flop (RS-FF) 17 (therefore, it operates only in the playback mode and when R3-FF17 is in the set state). do.)
The output is the R input (clear input) of D-FFI2.13
Add to. Therefore, while the two-man-powered AND game 21 is in operation, the operation of the ring counter constituted by the D-FFs 12 and 13 is stopped.

The output of D-FF12 and the Q output of D-FF13 are input to the two-man AND gate 28, and the output is R5-FF17.
is added to the S input of The R input of R3-FF is coupled to the single-sound recognition completion signal L-1 from the speech recognition device. 2
The manual AND gate 27 connects the Q output of D-FF l 2 and the D
- Combined with the output of FF13, the output is a two-man AND
is coupled to the first input of the gate and the control line L6
A latch 15 inserted into the data input side of the RAM via
It is connected to the CP input of 2 human power AND game) 19's i2 human power is combined with the playback mode signal P (therefore operates in the playback mode), and its output is sent to the CP input of the latch 16 (latch operation enable input) via the control line L2'. Add. One output of the D-FF 12 is sent to the sound input of the RAM 5 (as a chip selection signal) and the CP input of the lower counter 11 (as a black and red signal).

The two-man OR gate 29 is connected to the Q output of the D-FF 12 and the recording mode signal from the clock circuit via the inverter 33 (therefore, its output becomes active at low level only in the recording mode). , output to the CP input (enabled at low level) of the three-state gate 18. The two-man power AND gate 20 receives the output of the AND gate 27 and the R signal (therefore operates in recording mode), and its output is applied to the WE large input low level (active) of the RAM 5 via the inverter 34 control line L3. . The output of AND gate 27 is applied via control @L6 to the CP input of latch 15 (the latch on the data input side of the clock circuit).

The operation of the apparatus having the above configuration will be explained below.

When this mode is selected by operating the recording mode key manual section 18, the clock circuit 6 outputs an R signal, that is, a recording mode signal (
This R signal causes the voice recognition device 13 to operate, and each time a single sound input from the microphone 1 is recognized, an E pulse and a recognition code indicating completion of recognition are output. . Therefore, the latch 14 is activated and puts the latch output (recognition code) on the data bus DB-2, and at the same time, the E pulse resets R3-FF of the recording/playback control section. As a result, AND gate 2
1 is closed and D-FF12 constitutes a quaternary ring counter.
Since the clear input R of and 13 becomes "0", both flip-flops are released from the reset state and start operating as a ring counter. The timing chart of this operation is shown in FIG. 4. That is, when the timing is a and b in FIG.
The output of gate 29 becomes low level (3-state gate)
18 is opened and a recognition code is output on data bus DB-1. Similarly, at timings a and b, D-FF
When page 12 = 0, the control line L5 becomes low level, and the chip selection input C5 of the audio storage RAM 5 becomes active. Also, at timing 5L (7), D-FF12Q = 1.0-
When FF13Q=1, the AND gate 27 is open, and since the mode is recording, the AND gate 20 is open. Therefore, the control line L3 becomes low level, and the audio storage-RA
M5's writer fiWE becomes active. Therefore, the recognition code on the data base XDB-1, for example, the ASCII code of the character A in which the phoneme "a" has been recognized, is written in the location specified by the address counter CTR. At the same time, since a signal is applied to the enable input CP of the latch 15 via the control line L6, the recognition code is decoded via the clock circuit 6 and the character 1 corresponding to the recognized phoneme (phoneme) is displayed on the display section 7, for example, Display A.

The memory location in RAM that is addressed at this time, i.e.
The count value (binary data) of the address counter CTH is sent to l via the clock circuit 6 via the address bus An-1.
The address value is converted into O-adic and the display unit 7 displays the current address value.

Therefore, the user can visually confirm whether the voice recognition is correct or incorrect for each single note of the voice input into the microphone, and also know the storage location in the RAM where the single note is written.

In addition, 1 (negative pulse) of D-FFI2 is input as a clock to the clock input CP of the lower counter 11 of the 16-bit address counter CTR, and between timings b and C (
It is counted at the rising edge (trailing edge) of the negative pulse, and the next address (=current address +
1) Output. Furthermore, at timing C, D-FF12
When Q=1 and D-FF13Q=l, AND gate 28 is opened and R3-FFI 7 is set, and a clear input is input to both D-FF12.13 (ring counter) via AND gate 21. For this reason, the ring counter will continue until the next recognition code is issued from the voice recognition@flVR! !
b Stop the production.

Thereafter, each time the next recognition is completed, the above operation is repeated, and the data is stored in consecutive storage areas in the RAM.

A series of sound code strings representing audio information are stored.

A voice recording is made.

1 Main Eni J In this mode, the 1 clock circuit 6 outputs a high level P signal, that is, a reproduction mode signal. Furthermore, at the start of reproduction, a one-shot clear signal CC is output from the clock circuit 6 to clear the address counter CTR and set the address to address 0. The JR sound/playback control section 3 includes:
8Hz from the above P signal and 1 frequency division timing circuit 2
A clock signal is input, and an 8H2 clock is supplied to each clock input CP of the quaternary ring counter (D-FFI 2 and 13) via an AND gate 23 and an OR gate 30. Therefore, the output of D-FF12 is 2Hz.
The clock is supplied to 1 at the chip selection input of the RAM 5 and to the clock input CP of the lower counter 11 of the address counter CTR. Therefore, the address is incremented by 1 every 5 seconds, and the recognition code is sequentially read out from the voice memory RAM every % seconds, and the latch 16 also latches the code read every 5 seconds to synthesize speech. Supply to device VG. As a result, the voice synthesizer sends a corresponding voice signal to the speaker SP at intervals of 2 characters/2 characters.
The audio is played every second. In synchronization with the latch 16, the latch 15 also latches the code read out from the RAM, and sequentially displays the corresponding characters on the display section 7 via the clock circuit 6 at a rate of 2 syllables/second. The memory location read from the RAM, that is, the count value of the address counter CTH, is also displayed on the display section 7 via the clock circuit 6 (the count value increases sequentially like the tape counter of a tape recorder). , the user can confirm the sound output from the speaker SP in units of phonemes (phonemes) through the characters displayed on the display unit 7.

In this case, in addition to the P signal output from the clock circuit, the B signal is output. Therefore, in the address control unit 4, a low level signal from the gate 36 is applied as a down signal to the 7° up/down manual input UD of the counter 9.10, and the count is placed in the down mode. Also, the gate 26 is opened and the clock signal of 2H2 is at the middle level (A3 to A3).
Since it is added to the counter 10 of 5), it is rewound at a relatively low speed by 8 counts. Note that in the configuration shown in Figure 1, the recording/playback control section 3 operates in this mode, but the operation may be prohibited.
The two-man power AND gate 23 in the recording/playback control section 3 may be made into a three-man power AND gate, and the third man power (additional input) may be coupled to the 1@ signal (B signal via an inverter).

Preset Mode Enter this mode when an alarm time is detected in the clock circuit. In this mode, first, from the clock circuit 6, the LD
The @ number, that is, the load signal of the counter, and the preset address data that has been set in advance, that is, the RAM5
The address data for where to start playback is
It is added to the a-domain input LD and preset data input of the address counter CTR. Therefore, address counter CTR outputs a preset address onto address bus AB-1 coupled to RAM 5 (and clock circuit). Reproduction is performed from this address. That is, in the above playback mode, playback is performed starting from the top address, but in this case, the playback start address is a preset address. Other than this difference, the operation is the same as the playback mode described above, so further explanation will be omitted.

In this mode, the clock circuit 6 outputs the F signal, that is, the fast-forward mode signal. In this case, the bell tone/reproduction control section 3 does not participate in any operation.

The F signal is input to the address control unit 4 along with the 2H2 clock signal, and is input to the clock input CP of the counter 9 of the upper 10 bits via the AND gate 24 and the OR gate 31. Therefore, the entire 16-bit counter increments by 64 counts per one clock signal, resulting in fast forwarding. Then, an address signal (counter value) incremented by 64° is input to the clock circuit via the address bus and displayed on the display section 7 in decimal notation.

In this mode, the 1 clock circuit 6 outputs a high level B signal, that is, a rewind mode signal. In this case as well, the bell tone/playback control section does not participate in the operation.

Then, the B@ number and the 2H2 clock signal are input to the address control section 4. The B@ signal applies a low level signal to the U/D input of the upper 10 bits of the 7-dress counter through the inverter 36, causing the counter to operate as a down counter. In addition, the B signal and the 2H2 rip signal are ANDed.
3 through the gate 25 (the !JP signal is low level and a high level signal is applied to the remaining inputs of this gate via the inverter 35).
A clock signal of 2H2 is applied to the clock input CP of the address counter 9 of the upper 10 bits through 1. Therefore, the count value of the entire address counter is decremented by 64 counts, and rewinding is performed. The display of @back is performed by sending the count value on the address bus to the display unit 7 via the clock circuit 6.

When a stop is instructed by the M key operation, the signals that had been output from the 1 clock circuit (e.g. R@, P@, B signal, or F signal) disappear, and the recording/playback device continues in its current state. Each device is stationary 0. For example, when stopping from the ji sound mode, the address bus AB-1 at the time of stop is
The address (count value) on the top and the data bus DB-
5 is displayed on the display section 7, and the Jl sound/playback control section and address control section are stopped.

For example, even though you put the sound "a" into the microphone MC, the voice recognition device misidentifies it as the sound "o". In such a case, since the character 0 is displayed on the display section 7, the user can know that there has been a misidentification. At the same time, the location where the misidentification code was written in the RAM 5 can also be known via the display section. That is, the count value of address counter CTR (RAM address) is
1. Since it is displayed on the display unit 7 via a clock circuit, it is possible to know if there is a misidentification. Therefore, stop, a
After performing the return mode and stop operation, it is possible to perform correction recording by entering the recording mode again.

However, since the illustrated apparatus 1J performs high-speed rewinding (rewinding in 64-count increments) and reproducing from the top address, it is somewhat inconvenient for corrections. To make corrections easier 1. For example, after confirming a misidentification, use the correction key to perform slow rewind, and then rewind to a certain point (the user can confirm this position from the count value on the display). Playback starts from the rewound address (instead of the top address) by operating the playback key.

The configuration can be configured so that the user can stop at a point that can be checked (for example, at a syllable break), then start recording from there, and record for correction.For slow rewinding, address It is sufficient to input a low-speed clock to the clock input of the lower counter 11 of the counter CTH, and for playback from the rewind position, the clear signal CC to the address counter explained in the playback mode should not be generated from the clock circuit (for example, (using a gate).

One of the features of the embodiments described above is that, although the actual situation is different, it functions in the same way as a normal tape recorder and is very easy to use.

This invention is not limited to the embodiments described above, and various modifications and changes are possible.

In this example, the term "single note" is.

As a therapeutic drug, it is used in the sense of a unit of voice recognition result of a high-pitched tone recognition device.

〔Effect of the invention〕

As can be seen from the above description, according to the present invention, single sounds recognized by the speech recognition device are stored in the memory.

It is recorded in the form of a corresponding character code (which can therefore be composed of about 1 byte), and when played back, it is read out to a speech synthesizer, synthesized, and played back. Therefore, it is possible to record audio for a long time with a small amount of memory. moreover,
During recording and/or playback, the corresponding characters are displayed on the display unit in synchronization with writing and reading from the memory, so that the recorded/playback audio can be confirmed. Because audio information enters both the auditory and visual senses, 1. For example,
During playback, even if it is difficult to understand with just one side,
Both provide resolution and help in understanding the original audio information.

[Brief explanation of drawings]

FIG. 1 is a circuit block diagram of an embodiment in which the present invention is applied to an electronic watch, FIG. 2 is a diagram showing an example of the structure of the address control section and address counter shown in FIG. 1, and FIG. FIG. 4, which is a diagram showing an example of the configuration of the recording/playback control section, is a time chart regarding the storage of a single note in the recording mode. 2... Frequency division timing circuit, 3... Recording/playback control section, 4... Address control section, 5.
...Audio storage RAM, 8...Clock circuit,
7. Old... Display section, 8... Key human power section, CTR
...Address counter, VR...Voice recognition device, VG...Speech synthesis device, MC...
...Microphone, SP...Speaker. Patent applicant: Casio Computer Co., Ltd. Figure 3

Claims (1)

[Claims] a voice recognition means for recognizing a voice from the outside; a storage means for storing a voice code recognized by the voice recognition means;
A voice recording and reproducing device comprising: a voice synthesizing means for converting the voice code recorded in the storage means into voice; and a display means for displaying the voice code recognized by the voice recognition means.