JPS6243392B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel display device suitable for application to a television receiver equipped with an electronic channel selection device.

Recently, electronic tuning tuners using variable capacitance diodes as tuning elements have been widely used in place of conventional turret-type or rotary switch-type tuners. A frequency synthesizer-type electronic tuning device is known that includes a local oscillation circuit of this electronically tuned tuner to form a PLL loop. In such a channel selection device, in order to select a channel, it is necessary to input a channel number using a numeric keypad or to press a channel selection switch in ascending or descending order. However, when inputting a channel number, the user must memorize the channel number, and when selecting channels sequentially, there is a drawback that the user cannot know which channel will be selected next.

SUMMARY OF THE INVENTION In view of this, an object of the present invention is to provide a channel display device that facilitates channel selection by inputting a channel number or sequentially selecting channels.

According to the present invention, the channel numbers of a plurality of channels receivable in the area are simultaneously displayed at a predetermined position on the screen of a television receiver.

An embodiment of the present invention will be described below with reference to FIGS. 1 and 2. In FIG. 1 showing the overall configuration of this example, 1 is a tuner and a tuning control section. This tuner and channel selection control section 1 is
It is a PLL method (frequency synthesizer method).
A configuration in which a local oscillator signal from a local oscillator is supplied to a phase comparator via a prescaler and a programmable variable frequency divider, the phase is compared with a reference signal, and the comparison output is fed back to the local oscillator as a control voltage (tuning voltage). has been done. and for control
The frequency division ratio of the variable frequency divider is determined to correspond to a predetermined channel by a channel control signal from the ROM 7, and band switching is performed by a band switching signal from the control ROM 7. The video intermediate frequency signal from the tuner and channel selection control section 1 is supplied to the video detector 3 via the video intermediate frequency amplifier 2, and the video signal is supplied to the mixing circuit 5 via the video amplifier 4, which displays the display described later. The signal is mixed with the signal and applied to the cathode ray tube 6.

In this example, the VHF band and UHF band from channel 1 to channel 62 are first swept, the presence or absence of broadcast waves is detected, and the number of the channel where the broadcast wave is present is stored in the channel number memory 8. That is, the television receiver is switched to the auto search operating state by an auto search trigger signal generated a predetermined time after the power is turned on, and the channel number code Cn from the channel number counter 10 is switched to the control state by the switching circuit 9.
Now given to ROM. At the same time, the channel number counter 10 and address counter 16 are reset, and immediately after that, the pulse generator 1
1 by the start signal applied to the pulse generator 1
1, a pulse _S1 with a period of, for example, 500 [ms] is generated, and the channel number counter 10 is incremented by this.

In this example, the presence or absence of broadcast waves is detected based on the presence or absence of a horizontal synchronization signal. A horizontal synchronization signal separated from the video signal by a synchronization separation circuit 12 is supplied to a synchronization signal detection circuit 13. The synchronization signal detection circuit 13 integrates the horizontal synchronization signal and generates a detection pulse S ₂ when the integrated output reaches a certain level or higher. This detection pulse _S2 becomes a write pulse for the channel number memory 8,
Further, by passing through the delay circuit 14a, it is made into a write pulse _S3 for the display memory 17, and further by passing through the delay circuit 14b and the OR gate 15, it is made into a step pulse _S4u for the address counter 16. The channel number memory 8 is controlled by the address signal Ca generated from the address counter 16.
For example, a predetermined address among addresses 0 to 15 is designated.

Address signal Ca from address counter 16
The channel number code is written to the address of the display memory 17 designated by , and the address signal Ca is supplied to the character generation circuit 18 .
The character generating circuit 18 has terminals 19 and 20.
A synchronizing signal and a clock pulse are supplied from each of the display memory 17 and a number display signal for displaying a number corresponding to the channel number code read out from the display memory 17 at a predetermined position on the cathode ray tube 6. A marker signal for adding a marker to a corresponding signal is generated, mixed with a video signal in a mixing circuit 5 at the next stage, and supplied to a cathode ray tube 6.

When one pulse _S1 is generated from the pulse generator 11 in the above-mentioned auto search state, the channel number code Cn corresponding to the channel number "1" is supplied to the control ROM 7 via the switching circuit 9; The read data makes it possible to receive one channel. In the Tokyo area, there is a broadcasting station on channel 1, so the detection pulse _S2 is generated from the synchronization signal detection circuit 13, and the detection pulse
Channel number code Cn is written to address 0 of channel number memory 8 by _S2 . Next, the above-mentioned channel number code Cn is written into the display memory 17 at address 0 by the write pulse _S3 . Furthermore, the address counter 16 is incremented by the step pulse _S4u , and the addresses of the channel number memory 8 and the display memory 17 are changed to address 1.

Then pulse S ₁ occurs and channel number code
Cn changes to correspond to "2", thereby entering a state in which two channels are received in the same manner as described above. Since there is no broadcast station on channel 2, the detection pulse _S2 is not generated, so the channel number code Cn of channel 2 is stored in memories 8 and 1.
7 is not written, and the address counter 16 also does not increment. Furthermore, the third pulse S ₁
occurs, the channel number code Cn corresponds to "3", and a state is reached in which 3 channels can be received. Since there is a broadcasting station on channel 3, a detection pulse _S2 is generated and the memory 8 and 17 are
At address 1, there is a channel number code of "3" Cn.
is written.

Hereinafter, the same operation as described above is performed every time the pulse S ₁ is generated from the pulse generator 11, and a total of 62 pulses S ₁ are supplied.
The UHF band sweep operation ends. As a result of this automatic search operation, "1", "3", "4", "6", "8", "10", "12" are displayed for husbands at addresses (0 to 8) in the channel number memory 8 and display memory 17.
Channel number codes corresponding to each channel number "42" and "46" are written. When the 63rd pulse _S1 is generated from the pulse generator 11, a stop signal is generated from the channel number counter 10, and this stop signal stops the pulse generation operation of the pulse generator 11. Automatically switches to channel selection mode. In other words, the address counter 16 is reset, the channel number memory 8 is brought into a state where the channel number code at the address specified by the address signal Ca is read out, and the channel number codes at all addresses in the display memory 17 are simultaneously read out. It will be in a state where it is Furthermore, during sequential channel selection, the channel number code Cn read from the memory 8 is supplied to the control ROM 7, and during random channel selection, the channel number code Cn is supplied to the encoder 2.
Control channel number code from 1 to ROM7
The switching circuit 9 switches to a state where it supplies.

In such a tuning operation state, the display memory 17
The channel number codes stored in are simultaneously read out and supplied to the character generation circuit 18,
Therefore, the stored channel numbers are simultaneously displayed at the bottom of the image plane 6a of the cathode ray tube 6 as shown in FIG. In other words, as shown by broken lines in FIG. 2, 16 display positions are designated in correspondence with 16 addresses of the display memory 17, and each display position is assigned a channel stored at each address of the display memory 17. A number will be displayed. Among the displayed channel numbers, a marker, for example, a frame-shaped marker, is added to the selected channel number. When the auto search operation state ends and switches to the channel selection operation state,
The address counter 16 is reset, and therefore the channel number "1" stored at address 0 of the channel number memory 8 is supplied to the control ROM 7, and one channel is received. At this time, a marker is added to "1" among the channel numbers displayed on the video screen 6a.

At the time of random channel selection, a desired channel number is specified from among those displayed on the video screen 6a using the numeric keypad 22. A channel number code corresponding to this designated channel number is generated from the encoder 21, and the switching circuit 9 uses the channel number code from the encoder 21 for control purposes.
It is now in a state where it is supplied to ROM7. Therefore, the designated channel can be received. At the same time, the comparison circuit 23 detects a match between the channel number code from the encoder 21 and the channel number code from the memory 8, and the pulse generator 24 generates step pulses _S4u to the address counter 16 until they match. do. The period of the pulses generated by the pulse generator 24 is sufficiently short, so that the pulses generated by the encoder 21 almost instantaneously
The channel number codes of both the memory 8 and the memory 8 match. This coincidence causes the pulse generator 24 to stop generating pulses. Therefore, numeric keypad 2
2, when the received channel number matches the channel number from the memory 8, the address signal Ca is given to the character generation circuit 18, so a marker is added to the channel number being received. can do.

In addition, when sequentially selecting channels, a step pulse _S4u or _S4d generated each time a sequentially selecting switch (not shown) is pressed is applied to the terminal 25u or 25d to move the address counter 16 in the incrementing or subtracting direction. It would be better to make progress. The progressive pulse for performing this sequential channel selection may be continuously generated while the sequential channel selection switch is held down. However, the pulse period in that case is sufficiently long. When selecting channels sequentially like this, the video screen 6
Markers are sequentially added to the right or left of the channel numbers displayed in a.

As understood from the description of one embodiment above,
According to the present invention, the channel numbers of broadcast stations receivable in the area are simultaneously displayed on the image screen of the CRT. You can easily select a channel even if you do not remember any of them, and when you select channels sequentially, you can easily know the channel number to be selected next.
Furthermore, since the channel number is displayed on the image screen, there is no need to provide a separate channel display section in the television receiver.

In addition to the above-mentioned embodiments, various types of markers for displaying the channel number currently being received may be used, such as adding a dot pattern or identifying by color. Also,
In addition to the frequency synthesizer using PLL, there is also an electronic tuning device that converts the code stored in the memory into a D/A to form a tuning voltage, or uses data stored in the ROM or calculates this data. Therefore, the present invention can also be applied to an electronic tuning device that determines the local oscillation frequency, and similar benefits can be obtained. Furthermore, the channel number memory 8 and the display memory 17 may be configured as non-luminous memories so that the auto search operation is not repeated every time the power is turned on.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of one embodiment of the present invention, and FIG.
The figure is a schematic diagram showing channel display according to the present invention. 1 is a tuner and tuning control unit, 5 is a mixing circuit,
6 is a cathode ray tube, 6a is an image screen, 7 is for control
ROM, 8 is a channel number memory, 16 is an address counter, 17 is a display memory, and 18 is a character generation circuit.

Claims (1)

[Claims] 1 Using a variable reactance element as a tuning element,
In a television receiver equipped with an electronic tuning tuner that receives a predetermined channel by a tuning voltage applied to the variable reactance element, by sequentially supplying channel number codes from a channel number counter to a control memory, a sweeping means for changing the tuning voltage to sweep the receiving frequency band; a detecting means for detecting a channel on which a broadcasting station is located by detecting the received signal; and an address counter for detecting the plurality of detected channel numbers. a memory that performs address designation and storage using address signals generated from the memory;
Display character generating means for displaying the numbers of a plurality of channels stored in the memory at a predetermined position on a cathode ray tube screen, and the address signal being supplied to the character generating means,
identification means for identifying the broadcasting station channel currently being received by the electronic tuning tuner among the plurality of channel numbers displayed, and the display is stored in the memory together with the screen of the broadcasting station currently being received. A channel display device for a television receiver that displays a plurality of channels currently being received as well as the channel of the broadcasting station currently being received.